JPH0645888A - Delay circuit - Google Patents

Abstract

PURPOSE:To provide an active delay circuit whose fluctuation of delay time due to the dispersion on production is reduced. CONSTITUTION:Resistances R1 and R2 connected to power sources VDD and VSS are provided. An inverter 21 is provided which consists of an FET N11 which has the drain connected to the resistance R1 end an PET N12 which has the drain connected to the source of the FET N11 and has the source connected to the resistance R2. An inverter 22 is provided which consists of an FET P12 which has the drain connected to the resistance R2 and an FET P11 having the drain connected to the source of the FET P12 with the source connected to the resistance R1. An inverter 23 is provided which consists of an FET P13 which has the source connected to the resistance R1 having the gate connected to an input terminal with the drain connected to an output terminal and an FET N13 which has the source connected to the resistance R2 having the gate and the drain connected to those of the FET P13 in common respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit, and more particularly to an active delay circuit constructed by using a field effect transistor (FET) in an integrated circuit.

[0002]

2. Description of the Related Art A conventional delay circuit, as shown in FIG.
The n inverters 11 to 1n are connected in series to obtain a delay time which is the sum of the propagation delay times of the respective stages.

As shown in FIG. 3, each of the inverters 11 to 1n has a P-channel FET P1 whose source is connected to the power source VDD and an N-channel transistor whose source is connected to the power source VSS.
It is a complementary inverter including a channel FET N1. The gates of the FETs P1 and N1 are commonly connected to each other and the input IN is input, and the drains are commonly connected to each other to output the output OUT.

In general, the delay time of the complementary inverter in the integrated circuit changes within the range of -50% to + 100% due to the power supply voltage, the ambient temperature, the manufacturing variations and the like. The main manufacturing variations are variations in gate length and threshold voltage. With respect to the variation due to the gate length, the FE can be designed by designing the gate length longer.
The gm of TP1 and N1 is reduced, the propagation delay time of the inverter is increased, and the influence on the delay time can be reduced. However, it is said that no measures are taken to reduce the influence on the delay time due to the variation in the threshold voltage.

[0005]

The conventional delay circuit described above has a drawback in that it is not possible to reduce the variation in the threshold voltage of the FET, which greatly affects the delay time.

[0006]

The delay circuit of the present invention includes first and second constant current sources connected to first and second power supplies, respectively, for supplying predetermined currents, and gates, respectively. A first conductivity type first electric field transistor having a drain commonly connected and the first constant current source connected to the drain, a drain connected to a source of the first electric field transistor, and a source connected to the second power source. A first inverter composed of the second field effect transistor of the first conductivity type connected to the second conductivity type and a second conductivity type in which the gate and the drain are commonly connected and the second constant current source is connected to the drain. A second field-effect transistor of the second conductivity type, the third field transistor of which is connected to the source of the third field transistor, and the source of which is connected to the first power source. An inverter, the fifth field effect transistor of the second conductivity type, the source of which is connected to the output of the first constant current source, the gate of which is connected to the input terminal and the drain of which is connected to the output terminal, and the source of which is the second. A third inverter composed of the sixth field effect transistor of the first conductivity type, the gate and drain of which are commonly connected to the gate and drain of the fifth field effect transistor, respectively, which are connected to the output of the constant current source of It is configured with.

[0007]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the delay circuit of the present invention.

As shown in FIG. 1, the delay circuit of this embodiment comprises a complementary inverter 11 composed of FETs P1 and N1 similar to the conventional example, and N-channel FETs N11 and N12 whose gates and drains are commonly connected. A P-type inverter 22 composed of an N-type inverter 21 and P-channel FETs P11 and P12 whose gates and drains are commonly connected, a P-channel FET P13, and an N-channel FET
The driving circuit 12 includes a complementary inverter 23 formed of N13, and resistors R1 and R2 for supplying constant currents from the power supplies VDD and VSS to the driving circuit 12, respectively.

Next, the operation of this embodiment will be described.

Generally, the threshold voltages of FETs of the same channel in the same chip of a semiconductor integrated circuit vary in the same direction. For example, the FE of the inverter 23 of the drive circuit 12
When the output current of the inverter 23 decreases and the delay time increases due to the variation of the threshold values of TP13 and N13 to the larger one, the resistor R is commonly used with the inverter 23.
The power supply voltage of the inverters 21 and 22 of the drive circuit 12 supplied via 1, R2 rises. Therefore, the decrease of the output current of the inverter 23, that is, the drive circuit 12 is compensated, and the increase of the delay time is compensated.

The inverter 11 has a function of further inverting the output of the drive circuit 12 and non-inverting the entire delay circuit,
The output of the drive circuit 12 having a small amplitude is supplied to the power supply VDD to VSS.
And the function of amplifying to the amplitude of the difference voltage.

Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications can be made. For example, it is needless to say that a current mirror circuit may be used instead of the resistor as the constant current source of the drive circuit without departing from the gist of the present invention.

[0014]

As described above, the delay circuit of the present invention compensates for the output current by utilizing the fact that the threshold fluctuation directions of the FETs in the same chip are the same.
This has the effect of reducing fluctuations in delay time due to manufacturing variations in the threshold voltage of the FET.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a delay circuit of the present invention.

FIG. 2 is a circuit diagram showing an example of a conventional delay circuit.

FIG. 3 is a circuit diagram showing an example of an inverter of a conventional delay circuit.

[Explanation of symbols]

11-1n, 21-23 Inverter 12 Drive circuit N1, N11-N13, P1, P11-P13 FE
TR1, R2 resistance

Claims (1)

[Claims] 1. A first and second constant current source connected to a first power source and a second power source to supply a predetermined current, respectively, and a gate and a drain are commonly connected to each other, and the first and second constant current sources are connected to the drain. A first conductivity type first electric field transistor connected to the constant current source and a drain connected to the source of the first electric field transistor, and the source connected to the second power source. A first inverter composed of two field effect transistors, and a third electric field transistor of the second conductivity type in which the gate and the drain are commonly connected and the second constant current source is connected to the drain, and the drain is the third A second inverter comprising a third field effect transistor of the second conductivity type connected to the source of the third field transistor, the source being connected to the first power supply; and the source being the first field effect transistor. A fifth field effect transistor of the second conductivity type, the source of which is connected to the output of the constant current source, the gate of which is connected to the input terminal and the drain of which is connected to the output terminal, and the source of which is connected to the output of the second constant current source. A third inverter comprising a sixth field effect transistor of the first conductivity type whose gate and drain are commonly connected to the gate and drain of the fifth field effect transistor, respectively. circuit.