JPH0645576A - Solid-state image pick-up device - Google Patents

Solid-state image pick-up device

Info

Publication number
JPH0645576A
JPH0645576A JP4195730A JP19573092A JPH0645576A JP H0645576 A JPH0645576 A JP H0645576A JP 4195730 A JP4195730 A JP 4195730A JP 19573092 A JP19573092 A JP 19573092A JP H0645576 A JPH0645576 A JP H0645576A
Authority
JP
Japan
Prior art keywords
pitch
dummy
charge
coupled device
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4195730A
Other languages
Japanese (ja)
Other versions
JP2884929B2 (en
Inventor
Shigeru Toyama
茂 遠山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4195730A priority Critical patent/JP2884929B2/en
Publication of JPH0645576A publication Critical patent/JPH0645576A/en
Application granted granted Critical
Publication of JP2884929B2 publication Critical patent/JP2884929B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To impart a high transfer efficiency to a horizontal charge coupled device even if the picture element pitches in an image region are large while horizontal length is long. CONSTITUTION:The title solid-state image pick-up element is provided with a pitch decreased dummy region 4 wherein the pitches between the charge coupling element lines connecting from the vertical charge coupling element 2 lines become smaller toward a horizontal charge coupling element 5. With this decrease in the pitch, the stepped pitch of the horizontal charge coupled device 5 can be made finer thereby enabling the whole length thereof to be decreased.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、2次元像情報を時系列
電気信号に変換する固体撮像素子に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device for converting two-dimensional image information into a time series electric signal.

【0002】[0002]

【従来の技術】従来の固体撮像素子では、イメージ領域
内には、光検出素子が2次元に配列され、垂直電荷結合
素子が光検出素子列間に設けられており、その下部に
は、水平電荷結合素子との間にダミー領域が設けられて
いる。このダミー領域における電荷結合素子列ピッチ
は、イメージ領域中の垂直電荷結合素子列のピッチと同
一かつ一定になっており、従って、イメージ領域の画素
ピッチと水平電荷結合素子の段ピッチとは同一になって
いる。
2. Description of the Related Art In a conventional solid-state image pickup device, photodetection elements are two-dimensionally arranged in an image area, and vertical charge-coupled elements are provided between the photodetection element rows. A dummy region is provided between the charge coupled device and the charge coupled device. The pitch of the charge-coupled device rows in this dummy region is the same and constant as the pitch of the vertical charge-coupled device columns in the image region. Therefore, the pixel pitch of the image region and the step pitch of the horizontal charge-coupled devices are the same. Has become.

【0003】[0003]

【発明が解決しようとする課題】2次元の固体撮像素子
の駆動は、垂直転送1段毎に水平転送全段が行われるた
め、水平電荷結合素子の駆動周波数は極めて高い。一般
に電荷結合素子は駆動周波数が高くなるにつれて転送効
率が低下する。このため水平電荷結合素子の転送効率の
良否が素子性能を大きく左右する。電荷結合素子の転送
効率と強い相関を持つチャネル内部電界は、チャネル長
の2乗に逆比例するので、電荷結合素子の段数が同じで
も全長が長く段ピッチが大きいと、転送効率が加速度的
に劣化する。従来の固体撮像素子では、前述のようにイ
メージ領域の画素ピッチと水平電荷結合素子の段ピッチ
とが一致している。このため、画素ピッチが大きくなる
と水平電荷結合素子の転送効率が劣化してしまうという
欠点がある。
In driving a two-dimensional solid-state image pickup device, all the horizontal transfer stages are performed for each vertical transfer stage, so that the drive frequency of the horizontal charge coupled device is extremely high. Generally, the transfer efficiency of the charge coupled device decreases as the driving frequency increases. Therefore, the quality of the transfer efficiency of the horizontal charge coupled device greatly affects the device performance. Since the electric field inside the channel, which has a strong correlation with the transfer efficiency of the charge-coupled device, is inversely proportional to the square of the channel length, even if the number of stages of the charge-coupled device is the same, if the total length is long and the stage pitch is large, the transfer efficiency will accelerate. to degrade. In the conventional solid-state imaging device, the pixel pitch in the image region and the step pitch of the horizontal charge-coupled device match as described above. Therefore, there is a drawback that the transfer efficiency of the horizontal charge coupled device is deteriorated when the pixel pitch is increased.

【0004】本発明の目的は、イメージ領域の画素ピッ
チが大きく水平長が長い場合にも、水平電荷結合素子の
転送効率が劣化することのない固体撮像素子を提供する
ことにある。
An object of the present invention is to provide a solid-state image pickup device which does not deteriorate the transfer efficiency of the horizontal charge coupled device even when the pixel pitch of the image region is large and the horizontal length is long.

【0005】[0005]

【課題を解決するための手段】第1の発明は、光検出素
子が2次元に配列され、光検出素子から垂直電荷結合素
子及び水平電荷結合素子の組み合わせにより光信号電荷
を転送し、出力部から時系列電気信号として出力する固
体撮像素子において、光検出素子が2次元に配列された
イメージ領域と水平電荷結合素子との間に、イメージ領
域の垂直電荷結合素子列からつながる電荷結合素子列の
間のピッチが水平電荷結合素子へ近づくに従って減少す
るピッチ減少ダミー領域を備えることを特徴としてい
る。
According to a first aspect of the present invention, photo-detecting elements are arranged two-dimensionally, and photo-signal charges are transferred from the photo-detecting elements by a combination of vertical charge-coupled elements and horizontal charge-coupled elements. In the solid-state imaging device for outputting as a time-series electric signal from the photo-detector, the charge-coupled device array connected from the vertical charge-coupled device array in the image region is provided between the image region where the photodetector is two-dimensionally arranged and the horizontal charge-coupled device. It is characterized in that a pitch-reducing dummy region in which the pitch between them decreases as it approaches the horizontal charge coupled device is provided.

【0006】また、第2の発明は、第1の発明において
ピッチ減少ダミー領域の段数がイメージ領域の段数とイ
メージ領域に付随するダミーの段数とを合わせた数以上
であることを特徴としている。
A second aspect of the invention is characterized in that, in the first aspect of the invention, the number of stages of the pitch-reduced dummy region is equal to or more than the total number of stages of the image region and dummy stages associated with the image region.

【0007】さらに、第3の発明は、第1の発明におい
てイメージ領域とピッチ減少ダミー領域との間に第1の
読出し制御ゲートを備え、ピッチ減少ダミー領域と水平
電荷結合素子との間に蓄積部および第2の読出し制御ゲ
ートを備え、イメージ領域とピッチ減少ダミー領域とが
別の駆動系統になっていることを特徴としている。
Furthermore, a third aspect of the present invention is the first aspect of the present invention, further comprising a first read control gate between the image area and the pitch-reducing dummy area, and storing between the pitch-reducing dummy area and the horizontal charge coupled device. And a second read control gate, and the image region and the pitch reduction dummy region are separate drive systems.

【0008】[0008]

【作用】第1の発明の固体撮像素子では、イメージ領域
と水平電荷結合素子との間にイメージ領域の垂直電荷結
合素子列からつながる電荷結合素子列の間のピッチが水
平電荷結合素子へ近づくに従って減少するピッチ減少ダ
ミー領域を具備しているので、画素ピッチが大きくなっ
ても水平電荷結合素子の段ピッチを細かくすることがで
き、全長も短くすることができる。従って、高い転送効
率を持たせることができる。
In the solid-state imaging device of the first aspect of the invention, as the pitch between the charge coupled device rows connected from the vertical charge coupled device row in the image area between the image area and the horizontal charge coupled element approaches the horizontal charge coupled element. Since the dummy area for decreasing the pitch is provided, the step pitch of the horizontal charge coupled device can be made fine and the total length can be shortened even if the pixel pitch becomes large. Therefore, high transfer efficiency can be provided.

【0009】ピッチ減少ダミー領域のピッチ減少量が大
きい場合、段数が少ないと端の方の電荷結合素子の段ピ
ッチが極めて大きくなり、転送不良を起こしてしまう危
険が発生する。このためピッチ減少ダミー領域の段数は
ピッチ減少量に伴って多くする必要がある。信号出力期
間と垂直ブランキング期間とが定められた状況下で、ピ
ッチ減少ダミー領域の段数とイメージ領域の垂直段数と
の割合が垂直ブランキング期間と信号出力期間との割合
を越えない範囲であれば問題はないが、越える場合ピッ
チ減少ダミー領域段数相当分だけ転送周波数を変更して
高くしなければならないなど駆動方法が複雑になる問題
が生じる。
When the pitch reduction amount of the pitch reduction dummy area is large, if the number of stages is small, the stage pitch of the charge coupled device at the end becomes extremely large, and there is a risk of defective transfer. For this reason, it is necessary to increase the number of steps of the pitch-reducing dummy area according to the pitch reduction amount. Under the condition that the signal output period and the vertical blanking period are defined, the ratio of the number of stages of the pitch reduction dummy region to the number of vertical stages of the image region does not exceed the ratio of the vertical blanking period and the signal output period. There is no problem if it exceeds, but if it exceeds the pitch reduction dummy area, the transfer frequency must be changed and raised by the number of stages corresponding to the number of dummy areas.

【0010】第2の発明の固体撮像素子では、ピッチ減
少ダミー領域の段数がイメージ領域の段数とイメージ領
域に付随するダミーの段数とを合わせた数以上になって
いるので、転送周波数を変更することなくイメージ領域
とピッチ減少ダミー領域とをまったく同一の駆動信号で
駆動させるだけで、1フィールド期間の遅延は発生する
が、垂直ブランキング期間と信号出力期間との割合を満
足する出力信号を得ることができる。
In the solid-state imaging device of the second invention, the transfer frequency is changed because the number of steps in the pitch-reduced dummy area is equal to or more than the number of steps in the image area and the number of dummy steps accompanying the image area. Only by driving the image region and the pitch reduction dummy region with exactly the same drive signal, a delay of one field period occurs, but an output signal satisfying the ratio of the vertical blanking period and the signal output period is obtained. be able to.

【0011】上述の構造では、ピッチ減少ダミー領域の
ピッチ減少量を大きく取ると素子寸法が大きくなるとい
う問題がある。駆動系統が多少複雑になるが素子寸法縮
小を可能にするのが第3の発明の固体撮像素子である。
第3の発明の固体撮像素子では、イメージ領域とピッチ
減少ダミー領域とが別の駆動系統になっており、イメー
ジ領域とピッチ減少ダミー領域との間に第1の読出し制
御ゲートを有し、ピッチ減少ダミー領域と水平電荷結合
素子との間に蓄積部および第2の読出し制御ゲートを有
する。
The above-mentioned structure has a problem that the element size becomes large when the pitch reduction amount of the pitch reduction dummy region is large. The solid-state imaging device according to the third aspect of the present invention makes it possible to reduce the size of the device, although the drive system is somewhat complicated.
In the solid-state imaging device according to the third aspect of the invention, the image region and the pitch-reducing dummy region have different drive systems, and the first read control gate is provided between the image region and the pitch-reducing dummy region. The storage portion and the second read control gate are provided between the reduced dummy region and the horizontal charge coupled device.

【0012】この構造で、第1の読出し制御ゲートの操
作によりイメージ領域の1段分の電荷がピッチ減少ダミ
ー領域に移される毎に、ピッチ減少ダミー領域は高速で
数回の転送動作をさせ、蓄積部に電荷を運び込む。高速
といっても水平電荷結合素子が全段転送しあげる期間に
1段分の電荷を蓄積部に送り込めばよいので、水平電荷
結合素子に比べれば充分低速である。蓄積部に運んだ電
荷は第2読出し制御ゲートの操作により水平電荷結合素
子に移される。ピッチ減少ダミー領域は転送効率が多少
悪かろうと転送動作を繰り返すことにより転送漏れ電荷
をすべて蓄積部へ運び込むことができる。このため、ピ
ッチ減少ダミー領域のピッチ減少量が大きくとも、段数
を少なくすることができ、素子寸法を小さくすることが
できる。
With this structure, each time the charge for one stage in the image area is transferred to the pitch reduction dummy area by the operation of the first read control gate, the pitch reduction dummy area is made to perform several transfer operations at high speed, Carry charge to the storage. Even if it is said to be high speed, it is sufficient to send the charge for one stage to the accumulating portion during the period when the horizontal charge coupled device transfers all the stages, so it is sufficiently slow compared with the horizontal charge coupled device. The charge carried to the storage is transferred to the horizontal charge coupled device by operating the second read control gate. Even if the transfer efficiency of the pitch-reduced dummy area is somewhat poor, the transfer operation can be repeated to transfer all the transfer leakage charges to the storage section. Therefore, even if the pitch reduction amount of the pitch reduction dummy region is large, the number of steps can be reduced and the element size can be reduced.

【0013】[0013]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。
Embodiments of the present invention will now be described with reference to the drawings.

【0014】図1は、第1の発明の固体撮像素子の一実
施例を示す平面構成図である。図1において、イメージ
領域3内には、光検出素子1が2次元に配列され、垂直
電荷結合素子2が光検出素子列間に設けられており、そ
の下部には、電荷結合素子列間ピッチが下方に行くに従
って減少するピッチ減少ダミー領域4が設けられてい
る。ピッチ減少ダミー領域4内の電荷結合素子は、イメ
ージ領域3の垂直電荷結合素子2と連続でつながってい
る。ピッチ減少ダミー領域4の下部に水平電荷結合素子
5が設けられている。図1に紛らわしさを避けるために
描かれていないが、ピッチ減少ダミー領域4と水平電荷
結合素子5との間に読出し制御ゲートを設けるのが普通
である。水平電荷結合素子5の終端には出力部6が接続
されている。
FIG. 1 is a plan view showing an embodiment of the solid-state image pickup device of the first invention. In FIG. 1, photo-detecting elements 1 are two-dimensionally arranged in an image region 3, vertical charge-coupled elements 2 are provided between the photo-detecting element rows, and a pitch between the charge-coupled element rows is provided under the photo-detecting element rows. Is provided with a pitch-reducing dummy region 4 that decreases as the position goes downward. The charge coupled device in the pitch reducing dummy region 4 is continuously connected to the vertical charge coupled device 2 in the image region 3. A horizontal charge coupled device 5 is provided below the pitch reduction dummy region 4. Although not shown in FIG. 1 to avoid ambiguity, it is common to provide a read control gate between the pitch-reducing dummy region 4 and the horizontal charge coupled device 5. An output unit 6 is connected to the end of the horizontal charge coupled device 5.

【0015】次に、本実施例の動作について説明する。
本実施例の動作は従来のものと同様である。光検出素子
1において光電変換により発生した信号電荷をそれ自身
が一定期間蓄積した後、光検出素子群から垂直電荷結合
素子列に信号電荷が移される。信号電荷を移した後、光
検出素子1は再び光電変換および電荷蓄積動作状態とな
る。一水平期間のうちに、垂直電荷結合素子列およびピ
ッチ減少ダミー領域4の電荷結合素子群が一段下方への
電荷転送動作によって一水平ライン分を水平電荷結合素
子5に転送し、水平電荷結合素子5から出力部6を経て
順次外部に読出す動作をする。この一水平ライン分の読
出しを一水平期間毎に繰り返し、ダミーも含めた全画素
の読出しを光検出素子1の蓄積期間に行う。従って、垂
直電荷結合素子列に読出された信号電荷は、ピッチ減少
ダミー領域4の段数に対応する水平期間の後に外部に順
次読出される。
Next, the operation of this embodiment will be described.
The operation of this embodiment is similar to the conventional one. After the signal charge generated by photoelectric conversion in the photodetector 1 is accumulated for a certain period of time, the signal charge is transferred from the photodetector group to the vertical charge coupled device array. After transferring the signal charges, the photodetector element 1 is again in the photoelectric conversion and charge storage operation state. In one horizontal period, the vertical charge-coupled device row and the charge-coupled device group in the pitch reduction dummy region 4 transfer one horizontal line portion to the horizontal charge-coupled device 5 by the charge transfer operation downward by one stage, and the horizontal charge-coupled device 5 is transferred. The operation of sequentially reading out from 5 through the output unit 6 is performed. This reading of one horizontal line is repeated every horizontal period, and all pixels including the dummy are read during the accumulation period of the photodetector 1. Therefore, the signal charges read to the vertical charge coupled device column are sequentially read out to the outside after the horizontal period corresponding to the number of stages of the pitch reduction dummy region 4.

【0016】図1に示すように、本発明の固体撮像素子
では、水平電荷結合素子の段ピッチをイメージ領域の画
素ピッチより細かくでき、かつ、全長をイメージ領域の
水平長より短縮できるので、転送効率を高くすることが
できる。
As shown in FIG. 1, in the solid-state image pickup device of the present invention, the step pitch of the horizontal charge-coupled device can be made finer than the pixel pitch of the image area and the total length can be made shorter than the horizontal length of the image area. The efficiency can be increased.

【0017】なお、実施例にはないがピッチ減少ダミー
領域の他に、イメージ領域に付随するダミーを持ってい
てもかまわない。
Although not included in the embodiment, a dummy attached to the image area may be provided in addition to the pitch reduction dummy area.

【0018】図2は、第2の発明の固体撮像素子の一実
施例を示す平面構成図である。m段イメージ領域8内に
は、第1の発明の実施例のイメージ領域3同様、光検出
素子が2次元に配列され、光検出素子列間に垂直電荷結
合素子が設けられている。また、(l+m+n)段ピッ
チ減少ダミー領域10内にも、第1の発明の実施例のピ
ッチ減少ダミー領域4同様、下方に行くに従ってピッチ
が減少する電荷結合素子群が設けられている。これらは
簡単のため図2で省略されている。m段イメージ領域8
の上方にl段イメージ領域上ダミー7が設けてあり、m
段イメージ領域8と(l+m+n)段ピッチ減少ダミー
領域10との間にn段イメージ領域下ダミー9が設けら
れている。これらl段イメージ領域上ダミー7とn段イ
メージ領域下ダミー9とがイメージ領域に付随するダミ
ーである。従って、ピッチ減少ダミー領域の段数は、イ
メージ領域上ダミーとイメージ領域とイメージ領域下ダ
ミーの段数の和である(l+m+n)段以上設ける必要
があり、本実施例では(l+m+n)段としている。
FIG. 2 is a plan view showing an embodiment of the solid-state image pickup device of the second invention. Similar to the image area 3 of the first embodiment of the present invention, photodetector elements are two-dimensionally arranged in the m-stage image area 8, and vertical charge-coupled elements are provided between the photodetector element rows. Further, in the (l + m + n) -step pitch reduction dummy region 10, as in the pitch reduction dummy region 4 of the embodiment of the first invention, a charge-coupled device group whose pitch decreases as it goes downward is provided. These are omitted in FIG. 2 for simplicity. m stage image area 8
A dummy 7 on the 1st stage image area is provided above
An n-step image area lower dummy 9 is provided between the step image area 8 and the (l + m + n) step pitch reduction dummy area 10. The l-th stage image area upper dummy 7 and the n-th stage image area lower dummy 9 are the dummy attached to the image area. Therefore, it is necessary to provide (l + m + n) stages or more, which is the sum of the number of stages of the dummy on the image region, the dummy on the image region, and the dummy on the lower region of the image region.

【0019】次に、本実施例の動作について説明する。
m段イメージ領域8内の光検出素子において光電変換に
より発生した信号電荷をそれ自身が一定期間蓄積した
後、光検出素子群から垂直電荷結合素子列に信号電荷が
移される。信号電荷を移した後、光検出素子は再び光電
変換および電荷蓄積動作状態となる。一水平期間のうち
に、l段イメージ領域上ダミー7、m段イメージ領域8
内の垂直電荷結合素子列、n段イメージ領域下ダミー9
および(l+m+n)段ピッチ減少ダミー領域10内の
電荷結合素子群が一段分下方への電荷転送動作によって
一水平ライン分を水平電荷結合素子5に転送し、水平電
荷結合素子5から出力部6を経て順次外部に読出す動作
をする。
Next, the operation of this embodiment will be described.
After the signal charge generated by photoelectric conversion in the photodetector in the m-stage image area 8 accumulates for a certain period of time, the signal charge is transferred from the photodetector group to the vertical charge coupled device column. After transferring the signal charge, the photodetector element is again in the photoelectric conversion and charge storage operation state. During the one horizontal period, the dummy 7 on the l-th stage image area and the image area 8 on the m-th stage image area
Vertical charge-coupled device array in the n-stage image area lower dummy 9
And the charge coupled device group in the (l + m + n) stage pitch reduction dummy region 10 transfers one horizontal line portion to the horizontal charge coupled device 5 by the charge transfer operation downward by one stage, and the horizontal charge coupled device 5 outputs the output portion 6 from the horizontal charge coupled device 5. Then, the reading operation is sequentially performed to the outside.

【0020】この一水平ライン分の読出しを一水平期間
毎に繰り返すのであるが、l段イメージ領域上ダミー
7、m段イメージ領域8およびn段イメージ領域下ダミ
ー9の電荷がすべて(l+m+n)段ピッチ減少ダミー
領域10に移った時点で、再びm段イメージ領域8内に
おいて光検出素子群から垂直電荷結合素子列に信号電荷
が移される。従って、外部には、l段イメージ領域上ダ
ミー7とn段イメージ領域下ダミー9の段数の和に相当
する垂直ブランキング期間を持った信号が、1フィール
ド期間の遅延が掛かった状態で出力される。要求される
垂直ブランキング期間対信号出力期間の割合に(l+
n)段対m段の割合を合わせておけば、出力信号は要求
を満足するものとなる。
This reading of one horizontal line is repeated every horizontal period, but all the charges in the l-stage image area upper dummy 7, the m-stage image area 8 and the n-stage image area lower dummy 9 are (l + m + n) steps. At the time of moving to the pitch-reducing dummy area 10, the signal charges are transferred from the photodetecting element group to the vertical charge-coupled device row in the m-stage image area 8 again. Therefore, a signal having a vertical blanking period corresponding to the sum of the number of stages of the l-stage image area upper dummy 7 and the n-stage image area lower dummy 9 is output to the outside with a delay of one field period. It The ratio of the required vertical blanking period to the signal output period is (l +
If the ratios of n) stages to m stages are matched, the output signal satisfies the requirement.

【0021】なお、ピッチ減少ダミー領域の段数がイメ
ージ領域の段数とイメージ領域に付随するダミーの段数
とを合わせた数より多い場合は、イメージ領域とイメー
ジ領域に付随するダミーの電荷がすべてピッチ減少ダミ
ー領域に移動した後、ピッチ減少ダミー領域の過剰段数
分空転送し、それからイメージ領域内において光検出素
子群から垂直電荷結合素子列に信号電荷を移す。
If the number of stages of the pitch-reduced dummy area is larger than the total number of steps of the image area and the number of dummy steps associated with the image area, all the charges of the image area and the dummy charges associated with the image area are reduced in pitch. After moving to the dummy area, dummy transfer is performed by the number of excess stages of the pitch-reducing dummy area, and then the signal charges are transferred from the photo-detecting element group to the vertical charge coupled element column in the image area.

【0022】以上のように本実施例では、ピッチ減少ダ
ミー領域のピッチ減少量が大きいために段数を多くする
必要がある場合にも、1フィールド期間の遅延は掛かる
が、従来と大差のない駆動で垂直ブランキング期間と信
号出力期間との割合を満足する出力信号を得ることがで
きる。
As described above, in the present embodiment, even if it is necessary to increase the number of stages because the pitch reduction amount of the pitch reduction dummy area is large, a delay of one field period is required, but the driving is not much different from the conventional driving. Thus, it is possible to obtain an output signal that satisfies the ratio of the vertical blanking period and the signal output period.

【0023】図3は、第3の発明の固体撮像素子の一実
施例を示す平面構成図である。イメージ領域3内には、
第1の発明の実施例同様、光検出素子が2次元に配列さ
れ、光検出素子列間に垂直電荷結合素子が設けられてい
る。また、ピッチ減少ダミー領域4内にも、第1の発明
の実施例同様、下方に行くに従ってピッチが減少する電
荷結合素子群が設けられている。これらは簡単のため図
3で省略されている。イメージ領域3とピッチ減少ダミ
ー領域4との間に、第1読出し制御ゲートおよびその電
極11が設けられ、ピッチ減少ダミー領域4と水平電荷
結合素子5との間に、蓄積部およびその制御電極12
と、第2読出し制御ゲートおよびその電極13とが連続
して設けられている。
FIG. 3 is a plan view showing an embodiment of the solid-state image pickup device of the third invention. In the image area 3,
Similar to the first embodiment of the invention, the photo-detecting elements are arranged two-dimensionally, and the vertical charge coupled elements are provided between the photo-detecting element rows. Also in the pitch reduction dummy region 4, as in the first embodiment of the present invention, a charge-coupled device group whose pitch decreases as it goes downward is provided. These are omitted in FIG. 3 for simplicity. A first read control gate and its electrode 11 are provided between the image area 3 and the pitch reduction dummy area 4, and a storage portion and its control electrode 12 are provided between the pitch reduction dummy area 4 and the horizontal charge coupled device 5.
And the second read control gate and its electrode 13 are continuously provided.

【0024】本実施例では、イメージ領域3とピッチ減
少ダミー領域4は、どちらも4相の場合を示しており、
イメージ領域垂直電荷結合素子駆動信号14(φV1〜
φV4)とピッチ減少ダミー領域電荷結合素子駆動信号
16(φD1〜φD4)で駆動される。また、水平電荷
結合素子5は、2相の場合を示しており、水平電荷結合
素子駆動信号19(φH1,φH4)で駆動される。こ
れらの電荷結合素子の形式および駆動信号は別の相でも
かまわない。
In this embodiment, both the image area 3 and the pitch reduction dummy area 4 have four phases.
Image region vertical charge coupled device drive signal 14 (φV1
φV4) and pitch reduction dummy area charge coupled device drive signal 16 (φD1 to φD4). Further, the horizontal charge-coupled device 5 shows a case of two phases, and is driven by the horizontal charge-coupled device drive signal 19 (φH1, φH4). The type and drive signal of these charge-coupled devices may be in different phases.

【0025】次に、本実施例の動作について説明する。
イメージ領域3内の光検出素子において光電変換により
発生した信号電荷をそれ自身が一定期間蓄積した後、光
検出素子群から垂直電荷結合素子列に信号電荷が移され
る。信号電荷を移した後、光検出素子は再び光電変換お
よび電荷蓄積動作状態となる。一水平期間のうちに、垂
直電荷結合素子列が一段分下方への電荷転送動作によっ
て一水平ライン分をピッチ減少ダミー領域4へ第1読出
し制御ゲートを介して転送し、第1読出し制御ゲートを
閉状態とした後、ピッチ減少ダミー領域4が高速転送動
作を数回繰り返して一水平ライン分を蓄積部に送り込
み、第2読出し制御ゲートを開状態として蓄積部から水
平電荷結合素子5に一水平ライン分を転送し、水平電荷
結合素子5から出力部6を経て、順次外部に読出す動作
をする。この一水平ライン分の読出しを一水平期間毎に
繰り返し、ダミーも含めた全画素の読出しを光検出素子
の蓄積期間に行う。
Next, the operation of this embodiment will be described.
After the signal charges generated by photoelectric conversion in the photodetection elements in the image area 3 are accumulated for a certain period of time, the signal charges are transferred from the photodetection element group to the vertical charge coupled device column. After transferring the signal charge, the photodetector element is again in the photoelectric conversion and charge storage operation state. In one horizontal period, the vertical charge coupled device column transfers one horizontal line to the pitch reduction dummy region 4 through the first read control gate by the charge transfer operation downward by one stage, and the first read control gate After the closed state, the pitch-reducing dummy region 4 repeats the high-speed transfer operation several times to send one horizontal line portion to the storage unit, and the second read control gate is opened to set one horizontal line from the storage unit to the horizontal charge coupled device 5. The line portion is transferred, and the horizontal charge coupled device 5 and the output unit 6 are sequentially read out to the outside. This reading of one horizontal line is repeated every horizontal period, and all pixels including the dummy are read during the accumulation period of the photodetector.

【0026】本実施例では、ピッチ減少ダミー領域の転
送効率が多少悪かろうと一水平ライン分について転送動
作を数回繰り返すので転送漏れ電荷をすべて蓄積部へ運
び込むことができる。このため、図3に示すように、ピ
ッチ減少ダミー領域の占める割合を小さくでき、素子寸
法を小さくすることができる。
In the present embodiment, the transfer operation is repeated several times for one horizontal line even if the transfer efficiency of the pitch-reduced dummy area is somewhat poor, so that all transfer leakage charges can be carried to the storage section. Therefore, as shown in FIG. 3, the proportion of the pitch-reducing dummy region can be reduced, and the element size can be reduced.

【0027】なお、本実施例にはないが、ピッチ減少ダ
ミー領域の他にイメージ領域に付随するダミーを持って
いてもかまわない。
Although not provided in this embodiment, a dummy attached to the image area may be provided in addition to the pitch reduction dummy area.

【0028】[0028]

【発明の効果】以上説明したように第1の発明の固体撮
像素子は、水平電荷結合素子の段ピッチをイメージ領域
の画素ピッチより細かくでき、かつ、全長をイメージ領
域の水平長より短縮できるので、転送効率を高くするこ
とができるという効果を有する。
As described above, in the solid-state imaging device of the first invention, the step pitch of the horizontal charge coupled device can be made finer than the pixel pitch of the image area, and the total length can be made shorter than the horizontal length of the image area. The effect is that the transfer efficiency can be increased.

【0029】また、第2の発明の固体撮像素子は、ピッ
チ減少ダミー領域の段数がイメージ領域の段数とイメー
ジ領域に付随するダミーの段数とを合わせた以上になっ
ているので、良好な転送を行うことができるという効果
を有する。
Further, in the solid-state image pickup device of the second invention, the number of stages of the pitch-reduced dummy region is equal to or more than the number of stages of the image region and the number of dummy stages associated with the image region, so that good transfer can be performed. It has the effect that it can be performed.

【0030】さらに、第3の発明の固体撮像素子は、一
水平ライン分について転送動作を数回繰り返すので転送
漏れ電荷をすべて蓄積部へ運ぶことができるためにピッ
チ減少ダミー領域を小さくでき、素子寸法を小さくする
ことができるという効果を有する。
Further, in the solid-state image pickup device of the third invention, since the transfer operation is repeated several times for one horizontal line, all the transfer leakage charges can be carried to the storage portion, so that the pitch reduction dummy region can be made small, and the device can be made small. This has the effect of reducing the size.

【図面の簡単な説明】[Brief description of drawings]

【図1】第1の発明の固体撮像素子の一実施例を示す平
面構成図である。
FIG. 1 is a plan configuration diagram showing an embodiment of a solid-state imaging device of the first invention.

【図2】第2の発明の固体撮像素子の一実施例を示す平
面構成図である。
FIG. 2 is a plan configuration diagram showing an embodiment of a solid-state imaging device of the second invention.

【図3】第3の発明の固体撮像素子の一実施例を示す平
面構成図である。
FIG. 3 is a plan configuration diagram showing an embodiment of a solid-state imaging device of the third invention.

【符号の説明】[Explanation of symbols]

1 光検出素子 2 垂直電荷結合素子 3 イメージ領域 4 ピッチ減少ダミー領域 5 水平電荷結合素子 6 出力部 7 l段イメージ領域上ダミー 8 m段イメージ領域 9 n段イメージ領域下ダミー 10 (l+m+n)段ピッチ減少ダミー領域 11 第1読出し制御ゲートおよびその電極 12 蓄積部およびその制御電極 13 第2読出し制御ゲートおよびその電極 14 イメージ領域垂直電荷結合素子駆動信号 15 第1読出し制御信号 16 ピッチ減少ダミー領域電荷結合素子駆動信号 17 蓄積部制御信号 18 第2読出し制御信号 19 水平電荷結合素子駆動信号 1 Photodetector 2 Vertical charge-coupled device 3 Image area 4 Pitch reduction dummy area 5 Horizontal charge-coupled device 6 Output part 7 l stage image area upper dummy 8 m stage image area 9 n stage image area lower dummy 10 (l + m + n) stage pitch Reduced dummy region 11 First read control gate and its electrode 12 Storage part and its control electrode 13 Second read control gate and its electrode 14 Image region Vertical charge coupled device drive signal 15 First read control signal 16 Pitch reduced dummy region Charge coupled Device drive signal 17 Storage unit control signal 18 Second readout control signal 19 Horizontal charge coupled device drive signal

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】光検出素子が2次元に配列され、光検出素
子から垂直電荷結合素子および水平電荷結合素子の組み
合わせにより光信号電荷を転送し、出力部から時系列電
気信号として出力する固体撮像素子において、 光検出素子が2次元に配列されたイメージ領域と水平電
荷結合素子との間に、イメージ領域の垂直電荷結合素子
列からつながる電荷結合素子列の間のピッチが水平電荷
結合素子へ近づくに従って減少するピッチ減少ダミー領
域を備えることを特徴とする固体撮像素子。
1. A solid-state imaging device in which photo-detecting elements are two-dimensionally arranged, photo-signal charges are transferred from the photo-detecting elements by a combination of vertical charge-coupled elements and horizontal charge-coupled elements, and output as time-series electrical signals from an output section. In the device, the pitch between the charge-coupled device rows connected from the vertical charge-coupled device row in the image area approaches the horizontal charge-coupled element between the image area in which the photodetection elements are two-dimensionally arranged and the horizontal charge-coupled element. A solid-state image sensor, comprising: a pitch-reducing dummy region that decreases in accordance with the above.
【請求項2】請求項1記載の固体撮像素子において、ピ
ッチ減少ダミー領域の段数がイメージ領域の段数とイメ
ージ領域に付随するダミーの段数とを合わせた数以上で
あることを特徴とする固体撮像素子。
2. The solid-state imaging device according to claim 1, wherein the number of stages of the pitch-reduced dummy region is equal to or more than the number of stages of the image region and the number of dummy stages accompanying the image region. element.
【請求項3】請求項1記載の固体撮像素子において、イ
メージ領域とピッチ減少ダミー領域との間に第1の読出
し制御ゲートを備え、ピッチ減少ダミー領域と水平電荷
結合素子との間に蓄積部および第2の読出し制御ゲート
を備え、イメージ領域とピッチ減少ダミー領域とが別の
駆動系統になっていることを特徴とする固体撮像素子。
3. The solid-state imaging device according to claim 1, further comprising a first read control gate provided between the image region and the pitch reduction dummy region, and a storage unit provided between the pitch reduction dummy region and the horizontal charge coupled device. And a second read control gate, wherein the image area and the pitch-reducing dummy area are separate drive systems.
JP4195730A 1992-07-23 1992-07-23 Solid-state imaging device Expired - Lifetime JP2884929B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4195730A JP2884929B2 (en) 1992-07-23 1992-07-23 Solid-state imaging device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4195730A JP2884929B2 (en) 1992-07-23 1992-07-23 Solid-state imaging device

Publications (2)

Publication Number Publication Date
JPH0645576A true JPH0645576A (en) 1994-02-18
JP2884929B2 JP2884929B2 (en) 1999-04-19

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Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0866502A2 (en) * 1997-03-21 1998-09-23 Dalsa Inc. Architecture for a CCD-imager with multiple readout registers
EP1102326A2 (en) * 1999-11-22 2001-05-23 Matsushita Electric Industrial Co., Ltd. Solid-state imaging device and imaging system using the same
US6392260B1 (en) 1999-04-29 2002-05-21 Dalsa, Inc. Architecture for a tapped CCD array
JP2002334988A (en) * 2001-05-09 2002-11-22 Sony Corp Solid-state imaging element
WO2003012477A1 (en) * 2001-08-01 2003-02-13 Hamamatsu Photonics K.K. X-ray imager
US7148464B2 (en) 2002-08-09 2006-12-12 Hamamatsu Photonics K.K. Photodiode array with a plurality of depressions

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0866502A2 (en) * 1997-03-21 1998-09-23 Dalsa Inc. Architecture for a CCD-imager with multiple readout registers
EP0866502A3 (en) * 1997-03-21 1999-01-13 Dalsa Inc. Architecture for a CCD-imager with multiple readout registers
US6392260B1 (en) 1999-04-29 2002-05-21 Dalsa, Inc. Architecture for a tapped CCD array
EP1102326A2 (en) * 1999-11-22 2001-05-23 Matsushita Electric Industrial Co., Ltd. Solid-state imaging device and imaging system using the same
EP1102326A3 (en) * 1999-11-22 2004-04-07 Matsushita Electric Industrial Co., Ltd. Solid-state imaging device and imaging system using the same
US6985182B1 (en) 1999-11-22 2006-01-10 Matsushita Electric Industrial Co., Ltd. Imaging device with vertical charge transfer paths having appropriate lengths and/or vent portions
JP2002334988A (en) * 2001-05-09 2002-11-22 Sony Corp Solid-state imaging element
WO2003012477A1 (en) * 2001-08-01 2003-02-13 Hamamatsu Photonics K.K. X-ray imager
JP2003046862A (en) * 2001-08-01 2003-02-14 Hamamatsu Photonics Kk X-ray image pickup device
US7138637B2 (en) 2001-08-01 2006-11-21 Hamamatsu Photonics K.K. X-ray imager
US7148464B2 (en) 2002-08-09 2006-12-12 Hamamatsu Photonics K.K. Photodiode array with a plurality of depressions

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