JPH0645448A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0645448A
JPH0645448A JP21579592A JP21579592A JPH0645448A JP H0645448 A JPH0645448 A JP H0645448A JP 21579592 A JP21579592 A JP 21579592A JP 21579592 A JP21579592 A JP 21579592A JP H0645448 A JPH0645448 A JP H0645448A
Authority
JP
Japan
Prior art keywords
fuse
wiring
fuses
semiconductor device
metal film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21579592A
Other languages
Japanese (ja)
Other versions
JP2830636B2 (en
Inventor
Yasuo Oyama
泰男 大山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21579592A priority Critical patent/JP2830636B2/en
Publication of JPH0645448A publication Critical patent/JPH0645448A/en
Application granted granted Critical
Publication of JP2830636B2 publication Critical patent/JP2830636B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To provide a semiconductor device in which fuses for redundant circuits can be blown by a low-energy laser beam and they are laminated on interconnections to realize large scale integration. CONSTITUTION:Thin, patterned metal films 3 and 4, including interconnection patterns, are formed on an insulating layer 6. A plated interconnection 1 is formed on part of the metal film, and the remaining part of the metal film forms fuses 2. Since the fuses are made of thin metal, they can be formed on the uppermost layer and thus blown by lower energy. In addition, this structure is suitable for high scale integration because the fuses can be laminated on interconnections.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
レーザ光により溶断するヒューズを有する半導体装置に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a fuse that is blown by a laser beam.

【0002】[0002]

【従来の技術】半導体装置におけるメモリ部分は、同一
の回路を複数有し、かつ素子密度も非常に高く、他の回
路部分に比較して良品が得にくい。このため、従来から
冗長回路を予め配置した状態で半導体装置を製造し、そ
の後の電気的試験においてメモリ部分の状況を判断して
不良部分を切り離し、その代わりに冗長回路を接続する
ことにより、電気的に良品として使用するようにした構
成がとられている。この不良部分と冗長回路の切り離
し,接続を行うためにヒューズが用いられており、ヒュ
ーズをレーザ光により溶断することで回路の切断を行っ
ている。このレーザ光によるヒューズの溶断に際して
は、配線の熱伝導が高過ぎて非常に高エネルギのレーザ
光が必要となるため、ヒューズは配線層下にポリシリコ
ンを用いて形成し、レーザ光によりヒューズを溶断させ
ている。
2. Description of the Related Art A memory portion of a semiconductor device has a plurality of identical circuits and has a very high element density, so that it is difficult to obtain a good product as compared with other circuit portions. Therefore, conventionally, a semiconductor device is manufactured in a state where a redundant circuit is arranged in advance, the condition of a memory portion is judged in an electric test thereafter, a defective portion is cut off, and a redundant circuit is connected instead. It is designed to be used as a non-defective product. A fuse is used to disconnect and connect the defective portion and the redundant circuit, and the fuse is blown by a laser beam to disconnect the circuit. When the fuse is blown by the laser beam, the heat conduction of the wiring is too high and a laser beam of very high energy is required. Therefore, the fuse is formed by using polysilicon under the wiring layer, and the fuse is cut by the laser beam. It is blown out.

【0003】[0003]

【発明が解決しようとする課題】このような従来のヒュ
ーズでは、ヒューズ上に被着膜が多くなると、レーザ光
がヒューズに到達されるまでに減衰されてしまうため、
ヒューズの形成後にヒューズ上の被着部を選択的に除去
するエッチングが行われている。しかしながら、近年の
半導体装置では、配線層の数が増加する傾向にあり、配
線層間の絶縁膜の数も増大し、厚さも増加している。更
に、配線の段差を低減させるために有機系の塗布材料が
多用され、製造途中でヒューズ上の絶縁膜をエッチング
除去しておいても、その後に有機材料を塗布したときに
有機材料がその凹みに溜り、結果的には表面が平坦とな
り、絶縁膜の膜厚を薄くすることができないという問題
がある。
In such a conventional fuse, if the adhered film on the fuse is large, the laser light is attenuated by the time it reaches the fuse.
After the fuse is formed, etching is performed to selectively remove the adhered portion on the fuse. However, in recent semiconductor devices, the number of wiring layers tends to increase, the number of insulating films between wiring layers also increases, and the thickness also increases. In addition, an organic coating material is often used to reduce the step difference of the wiring, and even if the insulating film on the fuse is removed by etching during the manufacturing process, the organic material will not be dented when the organic material is applied later. However, there is a problem that the surface becomes flat and the thickness of the insulating film cannot be reduced.

【0004】この対策として、全絶縁膜を成長させた後
にヒューズ上のエッチングを行うことが考えられるが、
エッチングにより形成される凹みは深くなるため、その
後の取扱いによって汚れ等が溜り易く、信頼性が悪くな
るという問題がある。また、ヒューズ上の絶縁膜をエッ
チングしてしまうことから、ヒューズ上には配線を配置
することができず、半導体装置の高集積化が難しくなる
という問題がある。本発明の目的は、低エネルギのレー
ザ光でのヒューズ溶断を可能とし、かつヒューズと配線
とを積層可能にして高集積化を可能にした半導体装置を
提供することにある。
As a countermeasure against this, it is conceivable to perform etching on the fuse after growing the entire insulating film.
Since the dents formed by etching become deeper, dirt and the like are likely to accumulate due to subsequent handling, resulting in a problem of poor reliability. Further, since the insulating film on the fuse is etched, the wiring cannot be arranged on the fuse, which makes it difficult to achieve high integration of the semiconductor device. An object of the present invention is to provide a semiconductor device capable of fusing a fuse with a low-energy laser beam and stacking a fuse and a wiring to achieve high integration.

【0005】[0005]

【課題を解決するための手段】本発明は、下地絶縁膜上
に配線パターンを含む所要のパターンで形成された薄い
金属膜と、この薄い金属膜の一部を残した領域にめっき
法により形成された配線とを備え、前記配線が形成され
ない薄い金属膜をヒューズとして構成する。
According to the present invention, a thin metal film formed in a desired pattern including a wiring pattern on a base insulating film, and a thin metal film formed in a region where a part of the thin metal film remains by plating. And a thin metal film on which the wiring is not formed is configured as a fuse.

【0006】[0006]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の第1実施例を示しており、同図
(a)は平面レイアウト図、(b)はそのA−A線断面
図である。下地絶縁膜6上にチタンタングステン3が形
成され、この上にスパッタ法により形成されたスパッタ
金4が形成されている。更に、この上に電解めっき或い
は無電解めっきで形成された配線1が形成されている。
そして、この配線1は一部箇所で切断され、この切断部
は前記チタンタングステン3とスパッタ金4のみで構成
され、これでヒューズ2を形成している。そして、この
ヒューズ2及び配線1上にパッシベーション膜として窒
化膜5が被着されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1A and 1B show a first embodiment of the present invention. FIG. 1A is a plan layout diagram and FIG. 1B is a sectional view taken along the line AA. Titanium-tungsten 3 is formed on the base insulating film 6, and sputtered gold 4 formed by the sputtering method is formed on the titanium-tungsten 3. Furthermore, the wiring 1 formed by electrolytic plating or electroless plating is formed on this.
Then, the wiring 1 is cut at a part thereof, and the cut portion is composed of only the titanium tungsten 3 and the sputtered gold 4 to form the fuse 2. Then, a nitride film 5 is deposited as a passivation film on the fuse 2 and the wiring 1.

【0007】この製造方法を図2を用いて説明する。先
ず、図2(a)のように、下地絶縁膜6上にチタンタン
グステン3を1000Åスパッタし、めっきの成長核となる
金4を 500Åスパッタする。その後、図2(b)のよう
に、フォトレジスト7により配線部以外を覆うようにパ
ターニングし、電解めっき又は無電解めっきを 1.2μm
の厚さでめっきする。次いで、図2(c)のように、フ
ォトレジスト7をエッチングしてヒューズを形成する箇
所にのみフォトレジスト7を残しスパッタ金4とチタン
タングステン3をエッチングする。このとき、フォトレ
ジスト7で覆われていない配線1の表面は2000Å程度エ
ッチングされるため、ヒューズ両端の配線上は2000Å程
度の突起が形成される。その後、フォトレジスト7を除
去し、その上にパッシベーション膜として窒化膜を1μ
m形成する。
This manufacturing method will be described with reference to FIG. First, as shown in FIG. 2A, titanium-tungsten 3 is sputtered on the base insulating film 6 by 1000 Å, and gold 4 serving as a growth nucleus of plating is sputtered by 500 Å. After that, as shown in FIG. 2B, the photoresist 7 is patterned so as to cover portions other than the wiring portion, and electrolytic plating or electroless plating is performed to 1.2 μm.
Plating with the thickness of. Next, as shown in FIG. 2C, the sputtered gold 4 and the titanium tungsten 3 are etched while leaving the photoresist 7 only at the locations where the photoresist 7 is etched to form the fuse. At this time, the surface of the wiring 1 not covered with the photoresist 7 is etched by about 2000 Å, so that a protrusion of about 2000 Å is formed on the wiring at both ends of the fuse. Then, the photoresist 7 is removed, and a nitride film 1 μm is formed as a passivation film on the photoresist 7.
m.

【0008】この構成によれば、チタンタングステン3
とスパッタ金4とからなる非常に薄い金属パターンでヒ
ューズ2を構成することができ、このように形成された
ヒューズは通常の配線より熱伝導が低く、従来と同じエ
ネルギのレーザ光で溶断することができるため、冗長回
路用のヒューズとして充分利用することができる。
According to this structure, the titanium tungsten 3
The fuse 2 can be composed of a very thin metal pattern composed of the sputtered gold 4 and the sputtered gold 4. The fuse formed in this way has lower thermal conductivity than ordinary wiring, and can be blown by a laser beam of the same energy as the conventional one. Therefore, it can be sufficiently used as a fuse for a redundant circuit.

【0009】図3は本発明の第2実施例の断面図であ
る。ここではヒューズ部のスパッタ金を無くしている。
この構成は、例えば図2(b)の工程後にフォトレジス
ト7を除去し、露呈されたスパッタ金4を 500Åエッチ
ングして除去しておき、その後に第1実施例と同様にチ
タンタングステン3をエッチングして形成する。このよ
うにすると、第1実施例よりも更にヒューズ部の金属厚
さが薄くでき、熱伝導を更に低くすることができる。
FIG. 3 is a sectional view of a second embodiment of the present invention. Here, the sputtered gold in the fuse portion is eliminated.
In this structure, for example, after the step of FIG. 2B, the photoresist 7 is removed, the exposed sputtered gold 4 is removed by 500Å etching, and then the titanium tungsten 3 is etched as in the first embodiment. To form. By doing so, the metal thickness of the fuse portion can be made thinner than in the first embodiment, and the heat conduction can be further lowered.

【0010】ここで、図2(a)の工程後に、スパッタ
金4とチタンタングステン3を配線部とヒューズ部分に
のみ残るようにエッチングした後、フォトレジスト7を
除去し、再度フォトレジストでパターニングした上で配
線部の金めっきを無電解金めっきによって形成してもよ
い。このようにすると、第1,第2実施例では配線1を
形成してからヒューズ部のみにフォトレジストをパター
ニングしているために、 1.2μmの配線段差に対し、跨
がるようにフォトレジストをパターニングしなければな
らず、パターニング精度を上げ難いが、この実施例では
平坦な表面にパターニングすればよく、パターニング精
度が向上する。
After the step of FIG. 2A, the sputtered gold 4 and the titanium tungsten 3 were etched so as to remain only in the wiring portion and the fuse portion, the photoresist 7 was removed, and the photoresist was patterned again. The gold plating of the wiring part may be formed by electroless gold plating. In this case, in the first and second embodiments, since the photoresist is patterned only on the fuse portion after the wiring 1 is formed, the photoresist is spread over the 1.2 μm wiring step. Although it is difficult to increase the patterning accuracy because patterning is required, patterning accuracy can be improved by patterning on a flat surface in this embodiment.

【0011】[0011]

【発明の効果】以上説明したように本発明は、配線層を
含むパターン領域に設けた薄い金属膜でヒューズを形成
しているので、例えば多層配線を用いた半導体装置にお
いては、最上層の配線層にヒューズを形成することが可
能となり、絶縁膜をエッチングする必要はなくなり、ヒ
ューズ溶断を低エネルギで行うことが可能になるととも
に、ヒューズに重ねて配線を形成することができ、半導
体装置の高集積化を可能とする。
As described above, according to the present invention, since the fuse is formed by the thin metal film provided in the pattern region including the wiring layer, in the semiconductor device using the multilayer wiring, for example, the wiring of the uppermost layer is formed. A fuse can be formed in a layer, an insulating film does not need to be etched, the fuse can be blown with low energy, and wiring can be formed so as to overlap with the fuse. Enables integration.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施例の平面図及びそのA−A線
断面図である。
FIG. 1 is a plan view of a first embodiment of the present invention and a sectional view taken along line AA thereof.

【図2】図1の製造方法を工程順に示す断面図である。FIG. 2 is a cross-sectional view showing the manufacturing method of FIG. 1 in process order.

【図3】本発明の第2実施例の断面図である。FIG. 3 is a sectional view of a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 配線 2 ヒューズ 3 チタンタングステン 4 スパッタ金 5 窒化膜 6 下地絶縁膜 1 Wiring 2 Fuse 3 Titanium Tungsten 4 Sputtered Gold 5 Nitride Film 6 Base Insulation Film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 下地絶縁膜上に配線パターンを含む所要
のパターンで形成された薄い金属膜と、この薄い金属膜
の一部を残した領域にめっき法により形成された配線と
を備え、前記配線が形成されない薄い金属膜をヒューズ
として構成したことを特徴とする半導体装置。
1. A thin metal film formed in a desired pattern including a wiring pattern on a base insulating film, and a wiring formed by a plating method in a region where a part of the thin metal film is left, A semiconductor device comprising a thin metal film having no wiring formed as a fuse.
JP21579592A 1992-07-22 1992-07-22 Method for manufacturing semiconductor device Expired - Fee Related JP2830636B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21579592A JP2830636B2 (en) 1992-07-22 1992-07-22 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21579592A JP2830636B2 (en) 1992-07-22 1992-07-22 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0645448A true JPH0645448A (en) 1994-02-18
JP2830636B2 JP2830636B2 (en) 1998-12-02

Family

ID=16678374

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21579592A Expired - Fee Related JP2830636B2 (en) 1992-07-22 1992-07-22 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2830636B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004004009A1 (en) * 2002-06-28 2004-01-08 Kabushiki Kaisha Toyota Jidoshokki Semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004004009A1 (en) * 2002-06-28 2004-01-08 Kabushiki Kaisha Toyota Jidoshokki Semiconductor integrated circuit

Also Published As

Publication number Publication date
JP2830636B2 (en) 1998-12-02

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