JPH0645440A - Layout method of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a macro-buried-type cell array method with which the widths of main power buses and loop power buses are properly selected and basic cells are not wasted. CONSTITUTION:One or more macro-cells 13-17 and a number of basic cells which are arranged systematically with predetermined intervals are formed in the inner region 12 of a semiconductor chip 10. The inner region 12 is divided into a plurality of regions. A power is supplied to the respective divided regions or to groups of a plurality of the divided regions which are arranged along certain directions through main power buses 19a, 19b,... 24a and 14b having certain widths. Further, a power is supplied to the macro-cells through loop power buses 14a and 14b which are stretched around the main power buses and the cells. A reference power consumption for one basic cell is obtained. Then a power consumption for a unit area of the macro-cell is obtained and, if it exceeds the reference power consumption, the wiring widths of the respective main power buses and loop power buses are increased so as to eliminate the power consumption difference.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit layout method, and more particularly to a semiconductor integrated circuit layout method to which a macro-embedded cell array system is applied. For consumer ASICs, which have a short product lifespan, ASICs with a fully developed gate array (sea
of gate (SOG) was the mainstream. But this SO
G has a drawback in that the degree of integration does not increase when a large-capacity memory or the like is mounted, and the cost increases as compared with the standard cell. On the other hand, the standard cell can mount a hard macro having a high integration density, which is contrary to the SOG, but has drawbacks such as a long development period, a high development cost, and a layout only at a direct management design center. So SO
A cell array that combines the advantages of G and standard cells,
That is, there is a demand for a cell array which has a short development period, is advantageous in cost, and has a high degree of integration.

[0002]

2. Description of the Related Art FIG. 6 shows a conventional semiconductor integrated circuit which satisfies such requirements. This conventional example is, in short, as shown in FIG.
The standard cell shown in FIG. 7A and the S shown in FIG.
It is made by combining with OG, and is a so-called macro-embedded cell array system. That is, hard macros of standard cells accumulated as design assets, for example, macro cells such as ROM, RAM, multipliers, ... Are selected in accordance with the user's request and embedded in the basic cell area of the SOG. The user-only bulk is formed in the basic cell area.

The power bus layout of the internal area in the macro-embedded cell array system basically follows the SOG method. In FIG. 8, a broken line represents a dividing line of an internal area forming a basic cell or a macro cell. The main power bus MPB passes through n × m areas (4 × 3 areas in the figure) divided by dividing lines, and power (V _DD and V _SS ) is supplied to each area via this main power bus. To be done. Although not shown, a power bus (hereinafter referred to as a ring power bus) is provided around the macro cell and power is supplied through the ring power bus.

The power capacities (that is, the wiring widths) of the main power bus and the ring power bus are set to be the same according to the maximum power consumption of the chip.

[0005]

However, in such a conventional semiconductor integrated circuit layout method, the widths of all the main power buses and ring power buses are determined in accordance with the macro cell having the maximum power. The width of the main power bus responsible for areas with low power consumption and the ring power bus width of macro cells other than the maximum power become excessive, and these power buses are laid out by crushing basic cells, forming a user-specific bulk. However, there is a problem that the number of effective basic cells for the operation is reduced. [Object] Therefore, an object of the present invention is to provide a macro-embedded cell array system in which the width of the main power bus or the ring power bus is optimized and the basic cells are not wasted.

[0006]

In order to achieve the above-mentioned object, the present invention provides at least one macro cell and a large number of basic cells regularly arranged at a predetermined grid interval in an internal region of a semiconductor chip. In the semiconductor integrated circuit to be formed, power is supplied to each of the regions obtained by dividing the internal region into a plurality of regions or a plurality of regions arranged in the same direction via a main power bus having a predetermined width, and In the layout method of the semiconductor integrated circuit for supplying power to the macro cell via the main power bus and a ring power bus provided around the macro cell, wiring widths of the main power bus and the ring power bus are set. When setting, calculate the power consumption per basic cell and use this as the reference power consumption,
The area of the macro cell is divided by the area of the basic cell to obtain the unit area of the macro cell, and the total power consumption of the macro cell is divided by the unit area to obtain the power consumption per unit area of the macro cell, When the power consumption per unit area exceeds the reference power consumption, the wiring width of each main power bus and each ring power bus is increased so that the power difference is eliminated. .

[0007]

In the present invention, since the power consumption of the macro cell is converted into the power consumption per basic cell, the macro cell can be treated as a virtual basic cell, and each power can be adjusted according to the power consumption to be borne. The power capacity of the bus can be optimized.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 5 are views showing an embodiment of a layout method of a semiconductor integrated circuit according to the present invention. In FIG.
Reference numeral 10 denotes a semiconductor chip in which a large number of I / O cells 11 are formed on the periphery thereof. A cell (not shown) and various macro cells (first to fifth macro cells 13 to 17 in the figure) selected according to a user request are formed.

Here, 18a and 18b are I / O cells 11
I / O power bus that runs inside (subscript a is V
_{For DD} and b for V _SS ). Also, 19a, 19
b, 20a, 20b, ..., 24a, 24b are main power buses laid out at equal intervals in the internal region 12. Each main power bus passes through three regions (for example, the main power buses 19a and 19b are regions 25, 28, and 31) of the regions 25 to 33 divided by broken lines, and is in charge of power supply to the passage region.

In FIG. 1, two sets of main power buses 20a in the horizontal and vertical directions are provided on the first macro cell 13.
20b, 22a, 22b are laid out, and two sets of main power buses 22 in the lateral direction are arranged on the second macro cell 14.
a, 22b, 23a, and 23b are laid out.
Further, a pair of horizontal main power buses 23a and 23b is laid out on the third macro cell 15, and a pair of vertical main power buses 21a and 21b is laid out on the fourth macro cell 16. There is.

A ring power bus is stretched around each macro cell. For example, taking the second macro cell 14 as a representative, the ring power bus 1 will be described.
4a and 14b are stretched around, and the ring power buses 14 and 14b are two sets of main power buses 22a, 22b, 23a and 23 that pass over the second macro cell 14.
connected to b.

FIG. 2 is a diagram showing one area. If this area is, for example, area 25, the main power bus 19
a, 19b, 22a, 22b pass through, and a basic cell is formed in that region. Alternatively, assuming that the area 27, the main power buses 21a, 21b, 22a, 22b.
In the area, a part of the second macro cell 14 and the basic cell, and the ring power buses 14a, 14
b is formed.

Hereinafter, the area of FIG. 2 will be represented by reference numeral E, and the main power bus passing through the area will be represented by reference numerals MPBa and MPBb. That is, E is 25, 26, ..., 3
2 or 33, and MBP is 19, 20, ...
23 or 24. Next, a method for determining the widths of the main power bus and the ring power bus will be described.

The average capacity per basic cell is C (for example, C = 1), and the power supply voltage is V (for example, V = 5.
0), the operating frequency is F (for example, 10 MHz, 10
4 of 20MHz, 20-30MHz, 30-40MHz
Step), the operating rate of the main power bus is α (for example, α =
0.5), the power consumption IM in the area E is given by the product of these.

IM = C × V × F × α ... If the number of basic cells in the area E is PUBC,
The average power consumption per basic cell (that is, the reference power consumption Im) is calculated by the following equation. Im = IM ÷ PUBC ... where the area of one basic cell is the unit area (for example, 1
000 μm ² ), the power consumption per unit area is Im.

If, for example, a macro cell is formed in the area E, the ring power bus width around this macro cell is determined by the overlap relationship between the macro cell and the main power bus, and the unit area of the macro cell obtained from the following equation. It can be set as follows according to the magnitude relationship between the power consumption amounts Iem and Im. Iem = maximum power consumption of macro cell / unit area (1) The width W of one ring power bus when the macro cell and the main power bus overlap each other and when the condition of “Im ≧ Iem” is satisfied, Set according to.

W = (WMPB × N ÷ 2) / 2 ... WMPB: width of main power bus N: number of main power buses passing over macro cell (number other than 0) However, in the above equation, “Im >> Iem” At this time, the width of the ring power bus becomes too wide, so it is preferable to subdivide the conditions as follows. That is, (a) Iem
Is smaller than Im and larger than Im / 2, the above formula is applied, and (b) In the range where Iem is smaller than Im / 2 and larger than Im / 4, the following formula is applied, (C) In a region where Iem is smaller than Im / 4 and larger than Im / 8 or a region of Im / 8 or less, the following equation is applied.

(WMPB × N ÷ 2) ÷ 4 (WMPB × N ÷ 2) ÷ 8 ...... For example, the third macro cell 15 includes two main power sources.
Or the fourth and third holes 23a and 23b.
The macro cell 16 of the same also has two main power buses 21.
Since there is an overlapping relationship with a and 21b, N = 2 in both cases.
And when WMPB is set to, for example, 50 μm,
Width W of the ring power bus₁, W₂, W ₃Respectively
The results are shown in Table 1 below. However, G is the basic cell green
The dead space (1 G = 1 μm).(2) When the macro cell and main power bus overlap
And when the condition of “Im <Iem” is satisfied,
From the power consumption per unit cell of Wachi Basic Cell
If the power consumption per unit area of the macro cell is large,
The width of the ring power bus, depending on the difference in power
And the main power bus that connects to the ring power bus
Enlarge width and.

For example, the basic width of the ring power bus is W ₁
Then, W ₁ + Wa (enlargement) is obtained. A sub power bus may be provided in parallel with the ring power bus or the main power bus, and the width of the sub power bus may be Wa. The sub-power bus is assigned to each layer of the multi-layer wiring layer for each laying direction. For example, the horizontal direction is assigned to the wiring layer LB, and the vertical direction is assigned to the wiring layer LC. The number of sub-power buses that can be formed in each layer is calculated as follows.

First, the maximum electric power that can be supplied by the ring power bus having the basic width W ₁ and the main power bus, that is, the maximum current Iemax is given by the following equation. Iemax = (area of macro cell × Im) ÷ unit area
... This is the area of the macrocell multiplied by Im and the result divided by the unit area.

Next, the difference between the above-mentioned maximum current Iemax and the maximum current Imax of the macro cell is obtained, and the difference is divided by the maximum current of each layer to determine the number of sub-power buses that can be formed in each layer (for example, the wiring layer LB). LBn) is required for the number of lines. Then, the number is multiplied by the grid width G (for example, 1 μm) of the basic cell to obtain the width W of the sub power bus.
a is required. (3) When the macro cell and the main power bus do not overlap (corresponding to the fifth macro cell 17 in FIG. 1) and the condition of “Im ≧ Iem” is satisfied, the area E is calculated as shown in the following equation. The width W of the ring power bus is determined based on the area of the macro cell included in

W = [{(area of macro cell included in area E) ÷ unit area} ÷ PUBC] × WMPB ÷ β where PUBC: area of area E WMPB: width of main power bus β: main power bus The number of (in case of V _DD and V _SS β =
2) The following formula is used to convert the width W of the ring power bus obtained by the above formula into a grid image.

G _number = W / G, where G: grid width (for example, 1 μm) (4) When the macro cell and the main power bus do not overlap and the condition of “Im <Iem” is satisfied, that is, basic When the power consumption per unit area of the macro cell is larger than the power consumption per unit cell of the cell, the width of the ring power bus and the ring power bus according to the difference in the power are similarly to (2) above. Expand the width and width of the main power bus leading to.

FIG. 3 is a layout diagram of an example of the power bus set according to the above conditions (1) to (4).
Ring power buses 13a, 13b to 17a, 17b are laid around the first to fifth macro cells 13 to 17, respectively, but for macro cells consuming a large amount of power, for example, the second macro cell 14, , Auxiliary power buses for supplementing the power capacity of the main power buses 14a and 14b, that is, sub power buses 14c and 14d are laid. Between the ring power bus and the macro cell, and
A local power bus connects between the ring power bus and the user-only bulk region formed by the basic cells (regions denoted by reference numerals a to le in FIG. 3).

In FIG. 4, 40 is a macro cell, 41,
42 is a ring power bus, 43 to 46 are macrocell power supply wirings, 47 to 54 are local power buses, and 55 is a signal line. The hatching on the lower right is the wiring layer LA at the bottom,
The hatching in the lower left corner is the wiring layer LB thereabove, and the blackened portions are the connection points of both wiring layers. Here, it is desirable that the wiring can be led out from the macro cell from at least two wiring layers (LA, LB) and that the layer change area 56 is provided between the two ring power buses 41 and 42. By doing so, for example, the wiring layer LA
Since the signal line 55 drawn from the macro cell can be switched to the wiring layer LB by the layer change layer 56, the competition between the horizontal signal line and the double ring power bus can be avoided, and the layout can be facilitated.

FIG. 5 shows the I / O cell section 60 and the macro cell 6
It is a wiring layout diagram between 1 and. In this figure, the hatching in the lower right indicates the lowermost wiring layer LA, the hatching in the lower left indicates the intermediate wiring layer LB, the cross hatching indicates the uppermost wiring layer LC, and the black portions indicate the connection points between the layers. There is. The power supply V _SS input in the wiring layer LB is I /
After the layer is changed to the wiring layer LC in the O cell portion 60, it is transmitted to one ring power bus 65 via the main power buses 62, 63 and 64. The power supply V _DD input to the wiring layer LA is layer-changed to the wiring layer LC in the I / O cell section 60, and then the main power buses 66, 67, 6
It is transmitted to the other ring power bus 70 via 8 and 69. In the configuration of FIG. 5, since power is drawn from the I / O cell unit 60 to the uppermost wiring layer LC or the intermediate wiring layer LB, the lowermost wiring layer LA can be allocated for signals. It is possible to avoid layout conflict of the power supply wiring with respect to the wiring. Therefore, the mutual relation with the signal line can be simplified, and the width and interval of the power supply wiring can be optimally set according to the operating frequency and the power consumption.

As described above, in the present embodiment, the power consumption per basic cell (reference power consumption Im; actual current consumption) and the power consumption per unit area (area of one basic cell) of the macro cell of interest. The amount Iem is calculated, the two power consumptions are compared, and the power capacities (wiring widths) of the main power bus and the ring power bus connected to the macro cell of interest are set, so that the power distribution in the semiconductor chip is determined. Each power bus can be optimized and an excessive wiring area is not generated. Therefore, the minimum required basic cells can be allocated to the wiring area.
The number of effective basic cells can be increased, and the user-dedicated bulk can be efficiently formed.

[0028]

According to the present invention, it is possible to provide a macro-embedded cell array type semiconductor integrated circuit in which the widths of the main power bus and the ring power bus can be optimized and the basic cells are not wasted.

[Brief description of drawings]

FIG. 1 is an overall layout diagram of an embodiment.

FIG. 2 is an extraction diagram of one area in FIG.

FIG. 3 is an overall layout diagram including a ring power bus of one embodiment.

FIG. 4 is a layout diagram of a main part including a local power bus according to an embodiment.

FIG. 5 is a power supply wiring layout diagram from an I / O cell portion to a macro cell according to an embodiment.

FIG. 6 is a layout diagram of a conventional macro-embedded cell array system.

FIG. 7 is a layout diagram of a standard cell and an SOG layout diagram of a conventional example.

FIG. 8 is a layout diagram of a conventional main power bus.

[Explanation of symbols]

10: Semiconductor chip 12: Internal area 13-17: 1st-5th macro cell (macro cell) 14a, 14b: Ring power bus 19a, 19b, 20a, 20b, ..., 24a, 24
b: Main power bus

Claims (1)

[Claims] 1. At least one internal region of a semiconductor chip.
A semiconductor integrated circuit forming one macro cell and a large number of basic cells regularly arranged at a predetermined grid interval, wherein a plurality of basic cells are arranged in each of the plurality of divided internal regions or in the same direction. Power is supplied to the region via a main power bus having a predetermined width, and power is supplied to the macro cell via the main power bus and a ring power bus that is provided around the macro cell. In the layout method of a semiconductor integrated circuit, when setting the wiring widths of the main power bus and the ring power bus, the power consumption per basic cell is calculated and used as a reference power consumption, and the area of the macro cell is set to the basic power consumption. Divide by the cell area to obtain the unit area of the macro cell, and calculate the total power consumption of the macro cell. The power consumption per unit area of the macro cell is obtained by dividing by the unit area, and when the power consumption per unit area exceeds the reference power consumption, the power difference is eliminated so that the power difference is eliminated. A layout method of a semiconductor integrated circuit, characterized in that a wiring width of a main power bus and respective ring power buses is increased.