JPH0644907B2 - Ultrasonic wave reception phasing circuit - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to an ultrasonic wave receiving and phasing circuit in an electronic scanning ultrasonic tomography apparatus or the like.

[Background of the Invention]

A conventional wave receiving and phasing circuit is disclosed, for example, in JP-A-58-1411.
As described in Japanese Patent Laid-Open No. 42-42, each received signal is sampled at twice or more the maximum frequency of the signal band, and the signal value is held for a time corresponding to each delay time, and then added to receive the signal. It is compatible. This will be specifically described below.

FIG. 6 is a diagram showing an example of the configuration of a conventional wave receiving and phasing circuit using delay means by sampling. The signals from the respective receiving elements are input to input terminals 1 to n, subjected to phasing delay by delay means D1 to Dn for sampling, then added by an adder S, and noise by a sampling clock is removed by a low pass filter F. After that, the phasing result is output to the output terminal P.

As the sampling delay means D1 to Dn, for example, as shown in FIG. 8 (a), a sample and hold circuit connected in series or a switched capacitor circuit as shown in FIG. 8 (b) can be used. Moreover, it is also possible to use them in combination.

FIG. 8 (a) shows a case in which a sample hold circuit is used in series as the delay means D1 by sampling, and IN is an input terminal and OUT is an output terminal. With respect to the signal sampled by the sampling switch W ₁ , the potential at that time is held in the capacitor E ₁ at the same time when the switch is opened.

The switches W _{2 to} W _m and the capacitors E _{2 to} E _{m of the} second and subsequent stages perform the same operation via the buffer amplifiers P _{1 to} P _m , so that the maximum sampling cycle T = 1 / f per stage. _s delays can be made.

The delay time is determined by arbitrarily setting the hold time of each sample hold circuit.

FIG. 8 (b) shows an example in which a switched capacitor memory is used as the delay means D ₁ by sampling, IN is an input terminal, and OUT is an output terminal. X ₁ ~
X _{m, Y} 1 ~Y _m is a write switch and a read switch of the memory capacity _M 1 ~M _m respectively. Further, X ₀ is a reset switch, and OP is an operational amplifier.

The detailed operation of this circuit is described in JP-A-58-150193. The sampling period as T T = 1 / f _s, by controlling the write and read times,
It can be used as a variable delay unit up to mT for each sampling period T. The delay accuracy of the sampling cycle T or less is determined by the sampling clocks φ _{1 to} φ between the respective elements.
_It can be realized by shifting the phase of _n .

In the delay circuit of FIGS. 8 (a) and 8 (b), the input signal V
_IN , sampling clock φ _CLK , output signal V
_OUT becomes as shown in FIG. However, the output signal V _{OUT in} FIG. 9 is the case where the delay time is zero. As shown in FIG. 9, the output V _OUT has a leak of the sampling clock and noise synchronized with the clock from the sample to the settling value.

The power spectrum of V _OUT is shown in FIG. The power spectrum of the received signal is the shaded portion U ₁ , the highest frequency is f _H , the lowest frequency is f _L , and the center frequency is f ₀ . According to the sampling theorem, the sampling frequency f _S is more than twice the highest frequency f _H , and the noise frequency is f _S.

Therefore, the noise is removed by the filter F having the low-pass characteristic as shown by U ₂ in FIG. 7. Here, f _C is a cutoff frequency, and is set so that f _H <f _C <f _S.

However, in order to obtain a high-resolution image by increasing the ultrasonic frequency, it is necessary to increase the sampling speed as well. Due to the limit of the operating speed of the sampling element, the above-mentioned wave rectifying circuit is used for high-frequency ultrasonic waves. Was difficult.

[Object of the Invention]

An object of the present invention is to solve the above-mentioned problems in the conventional wave receiving and phasing circuit, and to provide a wave receiving and phasing circuit that can be used for high frequency ultrasonic waves.

[Outline of Invention]

The above-mentioned object of the present invention is to provide a plurality of ultrasonic tomography apparatuses for obtaining a tomographic image by deflecting or focusing an ultrasonic beam by controlling the amplitude and phase of the transmitted or received signal of each element of the array transducer. Receiver, delay means for sampling signals from each of the receivers, and means for selecting one of the delay means of the plurality of circuits.
An ultrasonic wave receiving and phasing circuit comprising a means for adding the outputs of the respective delay means selected by the selecting means, and a means for filtering the output of the adding means, or a plurality of ultrasonic wave receiving and phasing circuits. Any one of a receiver, delay means by sampling of a plurality of circuits for signals from each of the receivers, means for adding corresponding outputs of outputs of the delay means of the plurality of circuits, and output of the adding means This is achieved by an ultrasonic wave wave phasing circuit, characterized in that it comprises means for selecting one and means for filtering the output of the selecting means.

Example of Invention

FIG. 1 shows an ultrasonic wave receiving and phasing circuit which is an embodiment of the present invention. In the figure, 1 to n are input terminals, Di
-O and Di-e are delay means for sampling provided so as to be paired with each of the input terminals 1 to n,
φ _i o, φ _i e the sampling control _signal, s i _-o, s
_i- e is a changeover switch, and S is an adding means.

FIG. 2 shows the operation timings of the sampling control signals φ _i o, φ _i e and the changeover switches s _i −o, s _i −e. As is clear from FIG. 2, the sampling frequency per circuit of the delay means is f _S / 2.

Therefore, in this embodiment, the delay means 1 circuit can cope with a sampling frequency twice as high as the conventional one.

In the embodiment shown in FIG. 1, the delay means of each of the two circuits has a parasitic capacitance difference and an amplifier offset difference. Therefore, the signal at the terminal P ′ after phasing addition is shown in FIG. 4 (a). As shown, noise due to the offset difference of the period 2 / f _S is included.

The power spectrum of the signal at terminal P'is shown in FIG. The spectrum of noise due to the above offset difference exists at the frequency f _S / 2, and the spectrums of other signal and clock noises are the same as in FIG. 7.

Therefore, in order to remove the offset difference noise, U in FIG.
₂ and a _'low band filter characteristic as shown in or filter F having a bandpass characteristic as shown in U _{2 ",'.} That is, high cutoff frequency f _C of the filter F 'is f H _{<f C} <F _S / 2 and the low cutoff frequency f _CL should be 0 ≦ f _CL <f _{L. The} signal passed through the filter F ′ is as shown in FIG. , A signal in which noise due to the offset difference is removed.

In the above embodiment, the case where two delay circuits are provided for each received signal and the sampling is performed alternately has been described. However, three delay circuits or more are provided for each delay signal and the sampling delay is performed sequentially. It is clear that the same effect can be obtained in this case as well.

Further, FIG. 5 shows a second embodiment of the present invention. s-o and s-e are switching means for alternately selecting the signals phased and added by the adder S. The other elements are the same as those shown in FIG. It is clear that the configuration shown in the figure can achieve the same effect as that of the previous embodiment.

〔The invention's effect〕

As described above, according to the present invention, for each received signal,
A plurality of sampling delay circuits are provided,
Since the sampling delay is alternately divided, the sampling rate of the reception signal is increased by the number of the plurality of circuits described above, and it is possible to obtain a high-resolution image by increasing the ultrasonic frequency. Is played.

[Brief description of drawings]

FIG. 1 is a diagram showing an ultrasonic wave receiving and phasing circuit which is an embodiment of the present invention, and FIG. 2 is a timing chart of its control signal,
FIG. 3 is the same power spectrum diagram, and FIGS. 4 (a) and 4 (b).
Is a diagram showing an output signal waveform, FIG. 5 is a diagram showing another embodiment of the present invention, FIG. 6 is a diagram showing an example of a conventional wave-reception phasing circuit,
FIG. 7 is a diagram showing its power spectrum, FIGS. 8 (a) and 8 (b) are diagrams showing an example of delay means, and FIG.
It is a figure which shows the input / output signal to the delay means of the figure. 1 to n: phasing circuit input _{terminal, D i -o, D i -e} : sampling by the delay unit, S: adding means, F ': lowpass or bandpass filtering means, P: phasing output terminal, phi _i e :Control signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinichiro Umemura 1-280, Higashi Koigakubo, Kokubunji City, Tokyo Central Research Laboratory, Hitachi, Ltd. (72) Inventor Hiroshi Ikeda 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Hitachi, Ltd. Central Research Laboratory (56) Reference JP-A-60-200184 (JP, A)

Claims (2)

[Claims] 1. An ultrasonic tomography apparatus for deflecting or focusing an ultrasonic beam to obtain a tomographic image by controlling the amplitude and phase of a transmitted or received signal of each element of an array transducer. A delay means by sampling of a plurality of circuits for signals from each of the receivers, a means for selecting one of the delay means of the plurality of circuits, and a delay means of each of the delay means selected by the selecting means. An ultrasonic wave wave receiving and phasing circuit comprising means for adding outputs and means for filtering outputs of the adding means. 2. An ultrasonic tomographic apparatus for deflecting or converging an ultrasonic beam to obtain a tomographic image by controlling the amplitude and phase of a transmitted or received signal of each element of an array transducer. , A delay means by sampling of a plurality of circuits with respect to signals from each of the receivers, a means for adding corresponding outputs of the outputs of the delay means of the plurality of circuits, and an output of the adding means. An ultrasonic wave wave receiving and phasing circuit comprising: a means for selecting and a means for filtering the output of the selecting means.