JPH0644826B2 - Color signal processing circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color signal processing circuit, and more particularly to a color signal hue adjusting circuit in the form of a color difference signal.

(Prior Art) Hue adjustment in a color television receiver, a color VTR, and various other devices is conventionally performed by changing the phase of a carrier wave of a carrier color signal or changing the phase of a color burst signal. I was doing.

(Problems to be Solved by the Invention) However, since the phase shifter for performing the phase shift of the color burst signal or the carrier of the carrier color signal is usually composed of an analog circuit, it has a characteristic with respect to temperature. Since the change is large, it is difficult to easily configure a hue adjusting device capable of performing stable hue adjustment.

Further, conventionally, there was no means for easily adjusting the hue of the color signal in the form of the color difference signal in the state of the color difference signal, so that the hue adjustment could not be easily performed in the device handling the color difference signal.

(Means for Solving the Problem) According to the present invention, two color difference signals obtained when color-demodulating a carrier color signal with two color difference axes orthogonal to each other are used as a color amplitude signal corresponding to the amplitude of the carrier color signal. , A color amplitude / color phase conversion means for converting into a color phase signal corresponding to the phase of the carrier color signal, and phase shift data to the color phase signal output from the color amplitude / color phase conversion means. There is provided a color signal processing circuit comprising an arithmetic means for adding and subtracting and a means for generating a predetermined color difference signal based on the color amplitude signal and the color phase signal output from the subtracting means.

(Operation) A signal form similar to the two input color difference signals Asinθ and Acosθ that should be obtained when the carrier color signal whose amplitude is A and whose phase is θ is subjected to color demodulation with two orthogonal color difference axes Regarding the two color difference signals that have (Asin θ / Acos
The color phase signal corresponding to the phase θ is obtained from tan θ obtained by performing the calculation of θ).

A signal corresponding to sin θ (or con θ) is created from the color phase signal described above, and the input color difference signal Asin θ (or Acos) is generated.
θ) and [A sin θ / sin θ (or A cos θ / cos
θ)] is calculated to obtain a color amplitude signal corresponding to the amplitude A.

Phase-shifted data is added to or subtracted from the color-phase signal generated from the input color-difference signal to generate a phase-shifted color-phase signal.

A color signal having a predetermined signal form is generated using the phase-shifted color phase signal and the color amplitude signal.

(Embodiment) Hereinafter, specific contents of the color signal processing circuit of the present invention will be described in detail with reference to the accompanying drawings.

1 to 3 are block diagrams of different embodiments of the color signal processing circuit of the present invention, and FIG. 4 is a block diagram showing the configuration of a color amplitude signal and color phase signal generation circuit. 5 and 6 are diagrams for explaining the operation of the color amplitude signal and color phase signal generation circuit shown in FIG.

In FIGS. 1 to 3, 1 should be obtained when the carrier color signal is color-demodulated by two color difference axes which are orthogonal to each other.
An input terminal for digital data of one color difference signal (which is described as a red color difference signal RY signal in the following description) of the two color difference signals having the same signal form as the one color difference signal. Further, 2 is the other of the two color difference signals having the same signal form as the two color difference signals to be obtained when the carrier color signal is color-demodulated by the above-mentioned two orthogonal color difference axes. It is an input terminal for digital data of a color difference signal (which is described as a blue color difference signal BY signal in the following example).

1 to 3, 3 is a divider, 11 to 13 are arithmetic circuits, 14 and 15 are multipliers, 16 and 17 are output terminals, and in FIG. 1, 9 is an adder and 10 is an arithmetic circuit. Circuit.

1 and 2, 7 is a divider, 5 is an arithmetic circuit, 8 is a divider, and 6 is an arithmetic circuit in FIGS. 1 and 3.

1 to 3, two color difference signals to be obtained when a carrier color signal whose amplitude is A and whose phase is θ is color-demodulated by two color difference axes which are orthogonal to each other at the input terminal 1. Digital data of one of the color difference signals RY among the digital data of the two color difference signals (RY signal and BY signal) having the same signal form as Asinθ and Acosθ is supplied.

Further, at the input terminal 2, two color difference signals Asinθ that should be obtained when the carrier color signal whose amplitude is A and whose phase is θ are subjected to color demodulation with two color difference axes which are orthogonal to each other.
And the digital data of the other color difference signal BY signal of the digital data of the two color difference signals (RY signal and BY signal) having the same signal form as Acos θ. 1 to 3, the digital data of the RY signal is supplied to the divider 3 as a dividend,
Further, since the digital data of the BY signal is supplied to the divider 3 as a divisor, the divider 3 uses A
The calculation of sin θ / A cos θ = tan θ is performed, the data corresponding to the quotient tan θ obtained as a result of the division is output, and the data is supplied to the arithmetic circuit 4.

The arithmetic circuit 4 outputs color phase θ data from the tan θ data supplied thereto and supplies it to the arithmetic circuit 11. In the embodiment shown in FIGS. 1 and 2, the data of the color phase θ output from the arithmetic circuit 4 is also supplied to the arithmetic circuit 5 which outputs the data of the color phase θ supplied thereto as the data of sin θ. Further, in the embodiment shown in FIGS. 1 and 3, the data of the color phase θ output from the arithmetic circuit 4 is an operation for outputting the data of the color phase θ supplied thereto as the data of cos θ. It is also supplied to the circuit 6.

In the embodiment shown in FIGS. 1 and 2, the data of sin θ output from the arithmetic circuit 5 is supplied to the divider 7 as a divisor, and in the embodiments shown in FIGS. 1 and 3, the arithmetic circuit described above is supplied. The data of cos θ output from 6 is supplied to the divider 8 as a divisor.

In the embodiment shown in FIG. 1 and FIG. 2, since the digital data of RY = A sin θ supplied to the input terminal 1 is given to the divider 7 as a dividend, the divider 7 calculates Asin θ / sin θ. The calculation is performed to output the data of the color amplitude A.

In the first embodiment shown, the data of the color amplitude A output from the divider 7 is supplied to the adder 9, and in the second embodiment shown, the color amplitude A output from the divider 7 is supplied. Is supplied to the multipliers 14 and 15.

Further, in the embodiment shown in FIGS. 1 and 3, since the digital data of BY = Acosθ supplied to the input terminal 1 is given to the divider 8 as a dividend, the divider 8 uses Acosθ / Cos θ is calculated and the data of color amplitude A is output.

In the first embodiment shown, the data of the color amplitude A output from the divider 8 is supplied to the adder 9, and in the third embodiment shown, the color amplitude A output from the divider 8 is supplied. Is supplied to the multipliers 14 and 15. First
In the illustrated embodiment, since the adder 9 outputs the data of 2A, the arithmetic circuit 10 halves the data to obtain the data of the color amplitude A, and the data of the color amplitude A is multiplied. It is supplied to the vessels 14 and 15.

Next, FIG. 4 shows a means for generating data of color amplitude A having a different configuration from the means for generating data of color amplitude A and the means for generating data of color phase θ already described with reference to FIGS. 1 to 3. FIG. 3 is a block diagram showing a means for generating color phase θ data.

In FIG. 4, 1 has the same signal form as two color difference signals to be obtained when the carrier color signal (amplitude A, phase θ) is color demodulated by two color difference axes which are orthogonal to each other. It is an input terminal for digital data of one of the two color difference signals (in the following description, it is assumed that the red color difference signal R−Y signal = A sin θ).

Further, 2 is the other color difference signal of the two color difference signals having the same signal form as the two color difference signals which should be obtained when the carrier color signal is color-demodulated by the above-mentioned two orthogonal color difference axes ( In the following description, the blue color difference signal B-
Y signal = Acos θ) digital data input terminal. In the following description, it is assumed that the digital data supplied to the input terminals 1 and 2 is 2's complement data.

Further, in FIG. 4, 3 to 8 and 55 are arithmetic circuits, and 9 and 4
6 is an adder, 42 and 43 are absolute value circuits, 44 is a polarity inverting circuit, 45, 51-53 and 56 are changeover switches, 47,
Reference numeral 48 is a signal generation circuit, 49 and 50 are logic 0 value detection circuits, and 54 is an OR circuit.

In FIG. 4, the encoded bits of the digital data of the RY signal supplied to the input terminal 1 are supplied to the absolute value circuit 42 and the signal generation circuits 47 and 48, and B- supplied to the input terminal 2. The coded bits of the digital data of the Y signal are supplied to the absolute value circuit 43 and the signal generation circuits 47 and 48.

In the arithmetic circuit 3 to which the output data Asinθ from the absolute value circuit 42 is supplied as the dividend signal, the data of tanθ obtained by performing the arithmetic operation with the output data Acosθ from the absolute value circuit 43 as the divisor signal is used as the arithmetic circuit 4 Give to.

The arithmetic circuit 4 outputs the data corresponding to the color phase θ from the data of tan θ supplied thereto, and supplies the data to the fixed contact L of the changeover switch 47 and the polarity reversing circuit 44. In the polarity reversing circuit 44, the color phase θ data supplied thereto is supplied to the fixed contact H of the changeover switch 45 as −θ data.

The movable contact v of the changeover switch 45 is fixed to the fixed contact L according to the changeover control signal output from the signal generating circuit 47.
And the fixed contact H are switched to each other. The mode of switching is when the control output described in the column of "control output to switch 45" in FIG. 5 is in the low level state L. The movable contact v of the changeover switch 45 is switched to the fixed contact L side.

Further, when the control output described in the column of "Control output to switch 45" in FIG. 5 is in the high level state H, the movable contact v of the changeover switch 45 is switched to the fixed contact H side. It is done.

The signal generating circuit 47 described above has the input terminal 1
From the digital data of the RY signal supplied from the high-level state H and the low-level state L of the sign bit, and B-supplied from the input terminal 2 to it.
Depending on the combination of the high level state H and the low level state L of the sign bit in the digital data of the Y signal, the "control output to the switch 45" shown in FIG.
Select the control output as described in the column
5 as a switching control signal.

The phase angles of 0 ° and 180 ° described in the column of “Output to adder 46” in FIG. 5 are R− supplied to the signal generating circuit 47 from the input terminal 1. A high level state H and a low level state L of the sign bit in the digital data of the Y signal, and a high level state H of the sign bit in the digital data of the BY signal supplied from the input terminal 2 thereto. Depending on the combination with the low level state L, the adder 46, which will be described later,
Shows the phase of the signal to be supplied to.

The data of the color phase θ output from the arithmetic circuit 4 is supplied to the polarity reversing circuit 44, the changeover switch 45, the signal generating circuit 47, the adder 46, the changeover switch 51, and the signal generating circuit 48 which will be described later. The signal output from the tan θ data input to the arithmetic circuit 4 is output after the predetermined signal processing is performed by the signal processing circuit including the logical zero value detection circuits 49 and 50.
Indicates an angle from 0 ° to 180 °, the calculation circuit 4
Is based on the fact that θ can be calculated only for angles from 0 ° to 90 ° in the data of tan θ input to it.

That is, the data of the color phase θ output from the arithmetic circuit 4 is supplied to the polarity reversing circuit 44, the changeover switch 45, the signal generating circuit 47, the adder 46, the changeover switch 51, and the signal generating circuit 48 which will be described later. When the data of tan θ input to the arithmetic circuit 4 is θ from 0 ° to 90 ° by the signal processing circuit configured by the detection circuits 49 and 50 for the logic 0 value, the arithmetic circuit 4 So that the data of the color phase θ output from is output as it is as the data of the color phase, and when the data of tan θ input to the arithmetic circuit 4 is θ from 90 ° to 180 °, The data of the color phase θ output from the arithmetic circuit 4 is further input to the arithmetic circuit 4 so that the data of 180 ° −θ is output as the data of the color phase.
When the data of tan θ is θ from 180 ° to 270 °, the data of the color phase θ output from the arithmetic circuit 4 is regarded as the data of 180 ° + θ and is output as the data of the color phase. Furthermore, when the data of tan θ input to the arithmetic circuit 4 is an angle of 270 ° to 360 °, the data of the color phase θ output from the arithmetic circuit 4 is regarded as −θ data. The data is output as color phase data.

The data of the color phase θ output from the arithmetic circuit 4 is moved by the switching control signal as shown in the column of "Control output to the switch 46" from the signal generating circuit 47 in FIG. It is supplied to the adder 46 as the data of the color phase θ or the data of the color phase −θ via the changeover switch 45 whose contact point v is changed.

Since the adder 46 is supplied with the data of the phase as shown in the column of "output to the adder 46" in FIG. 5 from the signal generating circuit 47, The sum data of the two supplied data is output and given to the fixed contact of the changeover switch 51.

Further, data of phase 0 ° is supplied to the fixed contact of the changeover switch 51, data of phase 90 ° is supplied to the fixed contact, data of phase 180 ° is supplied to the fixed contact, and data of the fixed contact is supplied to the fixed contact. Is supplied with phase 270 ° data.

The logic 0 value detection circuit 49 to which the output data from the absolute value circuit 42 is supplied and the logic 0 value detection circuit 50 to which the output data from the absolute value circuit 43 is supplied are input to it. When the value of the digital data is a logical 0 value, the output in the high level state is supplied to the signal generating circuit 48.

The signal generation circuit 48 is also supplied with the sign bit of the RY signal supplied to the input terminal 1 and the sign bit of the BY signal supplied to the input terminal 2. The generating circuit 48 uses the combination of the above-mentioned four data supplied thereto so that the outputs .about. Shown in the output column in FIG. 6 can be output from the changeover switch 51. Generates a switching control signal for switching.

In FIG. 6, H indicates a high level signal, L indicates a low level signal, and X indicates an arbitrary level signal.

The data output from the movable contact of the changeover switch 51 is output as the color phase θ data.

Since the data of the color phase θ output from the movable contact of the changeover switch 51 is also supplied to the arithmetic circuits 5 and 6, the arithmetic circuit 5 outputs the data of the absolute value sin θ to the arithmetic circuit 7. It is supplied as a divisor signal, and the arithmetic circuit 6 outputs data whose absolute value is cos θ.
As a divisor signal.

Since the arithmetic circuit 7 is supplied with the digital data of the RY signal as the dividend from the absolute value circuit 42 described above, the arithmetic circuit 7 calculates Asinθ / sinθ so that the arithmetic circuit 7 outputs the color amplitude A Is output and given to the fixed contact L of the changeover switch 52.

Further, the arithmetic circuit 8 described above includes the absolute value circuit 4 described above.
Since the digital data of the BY signal from 3 is supplied as the dividend, the data of the color amplitude A is output from the arithmetic circuit 8 by the arithmetic operation of Acosθ / cosθ in the arithmetic circuit 8 and given to the fixed contact L of the changeover switch 53. To be

The fixed contact H of each of the changeover switches 52 and 53 described above
Data corresponding to 0 is supplied. The switching state of the movable contact v of the changeover switch 52 is controlled by the output data of the detection circuit 49 having a logical 0 value, and the movable contact v of the changeover switch 53 is changed to the logical 0.
The switching state is controlled by the output data of the value detection circuit 50.

The output data of the logical zero value detection circuits 49 and 50 are also used for the switching control of the movable contact v of the changeover switch 56, which will be described later, via the OR circuit 54.

After the data of the color amplitude A output from the movable contact v of the changeover switch 53 is added by the adder 9,
While being supplied to the fixed contact L of the changeover switch 56,
It is also supplied to the arithmetic circuit 55, and the above-mentioned arithmetic circuit 5
The data of the color amplitude 2A doubled by 5 is supplied to the fixed contact H of the changeover switch 56 described above.

Then, the data of the color amplitude 2A is output from the movable contact v of the changeover switch 56.

In each of the channel arrangements shown in FIGS. 1 to 3 and 4,
The data of the color phase θ output from the arithmetic circuit 4 in a part of a specific period in the horizontal blanking period of the color difference signal is the phase of the color burst signal existing in the horizontal blanking period of the color difference signal. This is the data of θ '.

In the embodiment of the color signal processing circuit shown in FIGS. 1 to 3 to which the color phase data output from the arithmetic circuit 4 is supplied, the data of the color phase signal output from the arithmetic circuit 4 described above is Since the phase data for phase shift is supplied to the arithmetic circuit 11 being supplied, the phase data of the color phase signal output from the arithmetic circuit 11 is transferred to the arithmetic circuit 11. The phase data of the phase and the phase data of the phase signal output from the arithmetic circuit 4 are calculated by the arithmetic circuit 11, so that the phase data of the phase signal output from the arithmetic circuit 4 becomes different.

Since the phase data of the phase signal output from the arithmetic circuit 11 changes according to the phase data for phase shift supplied to the arithmetic circuit 11, the set value of the phase data for phase shift supplied to the arithmetic circuit 11 is set. The hue adjustment is performed by changing the.

The color phase signal output from the arithmetic circuit 11, that is, the phase signal in the state of being phase-shifted by the phase data for phase shift supplied to the arithmetic circuit 11, is sin θ by the arithmetic circuit 12.
Signal is supplied to the multiplier 14, is multiplied by the color amplitude signal A in the multiplier 14, and the Asinθ = RY signal is output from the multiplier 14 to the output terminal 16.

Further, the color phase signal output from the arithmetic circuit 11, that is, the phase signal in the state of being shifted by the phase data for phase shift supplied to the arithmetic circuit 11 is calculated by the arithmetic circuit 13.
The signal of cos θ is supplied to the multiplier 15, is multiplied by the color amplitude signal A in the multiplier 15, and the A cos θ = BY signal is output from the multiplier 15 to the output terminal 17.

As described above, the RY signal output to the output terminal 16 and the BY signal output to the output terminal 17 have their hues changed by the phase data for phase shift supplied to the arithmetic circuit 11. It is easy to understand that it has become.

(Effects of the Invention) As is clear from the above description, the color signal processing circuit of the present invention outputs two color difference signals obtained when the carrier color signal is color demodulated by two color difference axes orthogonal to each other. A color amplitude and color phase conversion means for converting the color amplitude signal corresponding to the amplitude of the carrier color signal and the color phase signal corresponding to the phase of the carrier color signal; Arithmetic means for adding / subtracting phase shift data to / from the color phase signal output from the converting means; means for generating a predetermined color difference signal based on the color amplitude signal and the color phase signal output from the subtracting means. Since it is a color signal processing circuit composed of
Since the hue adjustment is performed by digital signal processing, the hue adjustment is performed accurately, and the phase shift angle does not fluctuate even when the temperature changes. Furthermore, the hue adjustment circuit is configured by an integrated circuit. In addition to the above, the phase shift circuit of the encoder unit, which has been conventionally required, can be omitted. According to the present invention, color signal processing in which all the problems of the conventional device described above are solved The circuit can be easily provided.

[Brief description of drawings]

1 to 3 are block diagrams of different embodiments of the color signal processing circuit of the present invention, and FIG. 4 is a block diagram showing the configuration of a color amplitude signal and color phase signal generation circuit. 5 and 6 are diagrams for explaining the operation of the color amplitude signal and color phase signal generation circuit shown in FIG. 1 ... Input of digital data of one of the two color difference signals having the same signal form as the two color difference signals to be obtained when the carrier color signal is color-demodulated by the two color difference axes which are orthogonal to each other. Terminal, 2 ... 2 which should be obtained when the carrier color signal is color demodulated with two color difference axes orthogonal to each other
Input terminals of the other color difference signal of the two color difference signals having the same signal form as one color difference signal, 3, 7, 8 ... Dividers, 4 to 6, 10 to 13, 55 ... Operation circuit, 9, 46 …
Adders, 13 to 15 ... Multipliers, 16, 17 ... Output terminals,
42, 43 ... Absolute value circuit, 44 ... Polarity inversion circuit, 45,
51-53, 56 ... Changeover switch, 47, 48 ... Signal generating circuit, 49, 50 ... Logic 0 value detecting circuit, 54 ... OR circuit,

Claims (1)

[Claims] 1. A color amplitude signal corresponding to the amplitude of the above-mentioned carrier color signal and two color difference signals obtained when color demodulation is carried out with two color difference axes orthogonal to the carrier color signal, and the above-mentioned carrier color signal. A color amplitude and color phase converting means for converting into a color phase signal corresponding to the phase of, and an arithmetic means for adding / subtracting phase shift data to / from the color phase signal output from the color amplitude / color phase converting means, A color signal processing circuit including a unit for generating a predetermined color difference signal based on the color amplitude signal and the color phase signal output from the subtraction unit.