JPH0644643B2 - Josephson junction element - Google Patents
Josephson junction elementInfo
- Publication number
- JPH0644643B2 JPH0644643B2 JP57027610A JP2761082A JPH0644643B2 JP H0644643 B2 JPH0644643 B2 JP H0644643B2 JP 57027610 A JP57027610 A JP 57027610A JP 2761082 A JP2761082 A JP 2761082A JP H0644643 B2 JPH0644643 B2 JP H0644643B2
- Authority
- JP
- Japan
- Prior art keywords
- superconductor
- layer
- josephson junction
- insulating layer
- barrier layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000002887 superconductor Substances 0.000 claims description 54
- 230000004888 barrier function Effects 0.000 claims description 35
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000010955 niobium Substances 0.000 description 3
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910000978 Pb alloy Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052758 niobium Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910001257 Nb alloy Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/10—Junction-based devices
- H10N60/12—Josephson-effect devices
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Description
【発明の詳細な説明】 本発明は、論理回路や記憶装置を構成するスイッチング
素子、微小磁界測定子、電圧標準器などに用いられるジ
ョセフソン接合素子に関するものである。The present invention relates to a Josephson junction element used for a switching element, a minute magnetic field measuring element, a voltage standard, etc., which constitutes a logic circuit or a memory device.
従来開発されて来たジョセフソン接合素子は、超伝導体
として鉛合金，ニオブ，ニオフ化合物なとの種々の超伝
導体が用いられており、主にリフトオフ技術により超伝
導体と絶縁体をパターニングして製造されている。通
常、リフトオフ技術によってパターニングを行う場合、
リフトオフを容易にするためにレジストの断面形状は逆
台形状に形成されている。このようにレジストの断面形
状を逆台形状とすると、レジスト上に目的の超伝導体又
は絶縁体層とする薄膜を蒸着技術やスパッタ技術を用い
て成膜する時、成膜している物質が逆台形のレジストの
傘の下に食い込むという問題がある。この食い込み量
は、場合によっては１μｍ程度に達し、パターンの設計
を著しく困難にしていた。特にジョセフソン接合素子の
接合層の形成においては、接合層の面積が直接ジョセフ
ソン接合素子の電気的な特性に影響するため、ジョセフ
ソン接合素子を用いた論理回路や記憶回路の設計を著し
く困難にしていた。Conventionally developed Josephson junction devices use various superconductors such as lead alloys, niobium, and nioff compounds as superconductors. Mainly patterning superconductors and insulators by lift-off technology. Is being manufactured. Usually, when patterning by lift-off technology,
The cross-sectional shape of the resist is formed in an inverted trapezoidal shape to facilitate lift-off. When the cross-sectional shape of the resist is an inverted trapezoidal shape in this way, when a thin film to be a target superconductor or an insulator layer is formed on the resist by vapor deposition technology or sputtering technology, the material being deposited is not There is a problem of digging under the inverted trapezoidal resist umbrella. This bite amount reaches about 1 μm in some cases, making the pattern design extremely difficult. In particular, when forming the junction layer of a Josephson junction element, the area of the junction layer directly affects the electrical characteristics of the Josephson junction element, making it extremely difficult to design a logic circuit or memory circuit using the Josephson junction element. I was doing.
本発明の目的は、前記従来の欠点を除去せしめたジョセ
フソン接合素子を提供することにある。It is an object of the present invention to provide a Josephson junction device that eliminates the above-mentioned conventional drawbacks.
本発明によれば、第１の超伝導体層上に設けられた該第
１の超伝導体層表面に貫通する開口部を備えた絶縁層と
該絶縁層上および前記開口部に設けられた第３の超伝導
体層と、該第３の超伝導体層上に設けられた接合バリア
層と、該接合バリア層上に設けられた第２の超伝導体層
からなり、前記絶縁層上の前記第３の超伝導体と前記開
口部に設けられた第３の超伝導体とが、前記開口部の側
壁を形成する前記絶縁層の主段差によって電気的に絶縁
され、開口部に形成された接合バリア層によってジョセ
フソン接合素子の特性が定まることを特徴とするジョセ
フソン接合素子が得られる。According to the present invention, an insulating layer provided on the first superconductor layer and having an opening penetrating the surface of the first superconductor layer, and an insulating layer provided on the insulating layer and on the opening A third superconductor layer, a bonding barrier layer provided on the third superconductor layer, and a second superconductor layer provided on the bonding barrier layer, the insulating layer being on the insulating layer. Of the third superconductor and the third superconductor provided in the opening are electrically insulated by the main step of the insulating layer forming the sidewall of the opening, and are formed in the opening. A Josephson junction device is obtained in which the characteristics of the Josephson junction device are determined by the junction barrier layer thus formed.
以下図面により本発明のさらに詳細な説明を行なう。The present invention will be described in more detail below with reference to the drawings.
第１図は、絶縁層が逆台形のレジストの傘の下に食い込
むことを説明するための図で、接合層を形成する孔をリ
フトオフで作る時のレジストと絶縁層との断面を、接合
層を形成する領域の部分について示したものである。図
は、シリコンウエハー等に表面処理を行った基板１１上
に第１の超伝導体１２を形成し、レジストワークで接合
層を形成する開口部を形成するための逆台形の形状レジ
スト１３をパターニングし、絶縁層１４，１５を蒸着技
術などで成膜した状態を示している。絶縁層１４，１５
を成膜している間に、逆台形のレジスト１３の傘の下に
絶縁層１４が図に示すように薄い薄層１６となって食い
込んでくる。この逆台形レジスト１３を形成する時、逆
台形レジスト１３の屋根寸法１７は、マスクの形状寸法
とほぼ同一寸法に設定てきるが、底寸法１８は、逆台形
レジスト１３の加工方法に依存して大きく変動するの
で、底寸法１８を正確に設定することは非常に困難であ
った。このような状態で作られる従来のジョセフソン接
合素子は第２図に示すようになる。FIG. 1 is a diagram for explaining that the insulating layer bites under an umbrella of an inverted trapezoidal resist, and shows a cross section of the resist and the insulating layer when a hole for forming the bonding layer is formed by lift-off. It shows the portion of the region forming the. In the figure, a first superconductor 12 is formed on a substrate 11 which is surface-treated on a silicon wafer or the like, and an inverted trapezoidal shaped resist 13 for forming an opening for forming a bonding layer is patterned by a resist work. The insulating layers 14 and 15 are formed by a vapor deposition technique or the like. Insulating layers 14, 15
While the film is being formed, the insulating layer 14 digs into the thin thin layer 16 under the umbrella of the inverted trapezoidal resist 13 as shown in the figure. When the inverted trapezoidal resist 13 is formed, the roof dimension 17 of the inverted trapezoidal resist 13 is set to be substantially the same as the shape dimension of the mask, but the bottom dimension 18 depends on the processing method of the inverted trapezoidal resist 13. It was very difficult to set the bottom dimension 18 accurately because of the large variation. A conventional Josephson junction device manufactured in such a state is as shown in FIG.
第２図は、第１図に引き続いて逆台形のレジスト１３を
除去し、接合バリア層と第２の超伝導体を形成して作っ
た従来のジョセフソン接合素子の基本構造を示したもの
である。接合バリア層２１の形成には、通常プラズマ酸
化技術が用いられる。接合バリア層２１は、第１図に示
したレジスト１３の底寸法１８で規定される絶縁層の薄
層１６の開口部に形成される。よって、接合バリア層２
１の寸法は、レジスト１３の底寸法１８に等しく、設計
によって規定できる屋根寸法１７との間に大きな誤差を
生じる。一方、ジョセフソン接合素子の電気的特性は、
接合バリア層２１の面積に依存して変わるため、接合バ
リア層２１の寸法ずれは、ジョセフソン接合素子の電気
的な特性を大きく変える。従って、従来のジョセフソン
接合素子を用いて論理回路や記憶装置を構成する場合、
回路の設計を非常に難かしくし、装置全体の動作マージ
を著しく低下させていた。FIG. 2 shows the basic structure of a conventional Josephson junction device formed by removing the inverted trapezoidal resist 13 following FIG. 1 and forming a junction barrier layer and a second superconductor. is there. A plasma oxidation technique is generally used to form the junction barrier layer 21. The junction barrier layer 21 is formed in the opening of the thin layer 16 of the insulating layer defined by the bottom dimension 18 of the resist 13 shown in FIG. Therefore, the junction barrier layer 2
The dimension of 1 is equal to the bottom dimension 18 of the resist 13 and causes a large error from the roof dimension 17 which can be defined by the design. On the other hand, the electrical characteristics of the Josephson junction element are
Since it changes depending on the area of the junction barrier layer 21, the dimensional deviation of the junction barrier layer 21 greatly changes the electrical characteristics of the Josephson junction element. Therefore, when configuring a logic circuit or memory device using the conventional Josephson junction element,
It made the circuit design very difficult and significantly reduced the operation merge of the entire device.
第３図は、本発明によるジョセフソン接合素子の基本構
造を示したものである。図は、ジョセフソン接合素子の
接合層部分の構造のみに注目して基本となる構造のみを
示してあり、ジョセフソン接合素子を用いた回路で通常
用いられるアース面、制御線などの部分は省略してあ
る。以下、本発明によるジョセフソン接合素子の基本的
な構造と簡単な製造方法の説明を行なう。第１の超伝導
体１２と絶縁層１４とは従来と同様にして形成される。
続いて、第１の超伝導体１２と絶縁層の薄層１６に接し
て第３の超伝導体３１を形成する。この時、接合バリア
層を形成する予定の開口部以外の領域にも第３の超伝導
体３２が形成される。この際、絶縁層１４上の第３の超
伝導体３２と絶縁層の薄層１６上の超伝導体３１は、開
口部の側壁を形成する絶縁層の主段差における段切れ効
果によって分離される。次にプラズマ酸化技術などによ
って第３の超伝導体３１，３２の酸化もしくはシリコン
の酸化物などの薄い絶縁体からなる接合バリア層３３を
形成する。この時も前述と同様、接合バリア層を形成す
る予定の開口部以外の領域にも接合バリア層３３と同一
物質のバリア層３４が形成される。接合バリア層３３と
バリア層３４とは、開口部の側壁を形成する絶縁層１４
の主段差における段切れ効果によって分離される。最後
に、接合バリア層３３とバリア層３４の上に第２の超伝
導体２２を形成してジョセフソン接合素子を製造する。FIG. 3 shows the basic structure of the Josephson junction element according to the present invention. The figure shows only the basic structure focusing only on the structure of the junction layer part of the Josephson junction element, omitting parts such as the ground plane and control line that are usually used in the circuit using the Josephson junction element. I am doing it. The basic structure and simple manufacturing method of the Josephson junction device according to the present invention will be described below. The first superconductor 12 and the insulating layer 14 are formed in a conventional manner.
Subsequently, the third superconductor 31 is formed in contact with the first superconductor 12 and the thin layer 16 of the insulating layer. At this time, the third superconductor 32 is also formed in a region other than the opening where the junction barrier layer is to be formed. At this time, the third superconductor 32 on the insulating layer 14 and the superconductor 31 on the thin insulating layer 16 are separated by the step breaking effect in the main step of the insulating layer forming the sidewall of the opening. . Next, a junction barrier layer 33 made of a thin insulator such as an oxide of the third superconductors 31 and 32 or a silicon oxide is formed by a plasma oxidation technique or the like. At this time as well, similar to the above, the barrier layer 34 of the same material as the bonding barrier layer 33 is formed in the region other than the opening where the bonding barrier layer is to be formed. The junction barrier layer 33 and the barrier layer 34 form the insulating layer 14 that forms the sidewall of the opening.
Are separated by the step break effect in the main step. Finally, the second superconductor 22 is formed on the junction barrier layer 33 and the barrier layer 34 to manufacture a Josephson junction device.
このように本発明によるジョセフソン接合素子は、第１
の超伝導体１２と第３の超伝導体３１とで第１の電極が
構成され、第２の電極は第２の超伝導体２２で構成され
る。接合バリア層３３を形成した絶縁層１４の開口部以
外の部分に形成された第３の超伝導体３２とバリア層３
４とは、開口部の側壁を形成する絶縁層１４の主段差に
おける段切れ効果によって、第１の電極を構成する第１
の超伝導体１２と第３の超伝導体３１とから完全に絶縁
され、第２の電極の一部として第２の超伝導体２２電気
的に接続されている。従って、第３の超伝導体３２とバ
リア層３４とは第２の超伝導体２２で完全に短絡されて
いるので、ジョセフソン接合素子の電気的な特性には、
ほとんど影響しない。Thus, the Josephson junction device according to the present invention is
The first electrode is constituted by the superconductor 12 and the third superconductor 31 and the second electrode is constituted by the second superconductor 22. The third superconductor 32 and the barrier layer 3 formed in a portion other than the opening of the insulating layer 14 in which the junction barrier layer 33 is formed
4 means the first electrode forming the first electrode due to the step breaking effect in the main step of the insulating layer 14 forming the side wall of the opening.
Is completely insulated from the superconductor 12 and the third superconductor 31 and is electrically connected to the second superconductor 22 as a part of the second electrode. Therefore, since the third superconductor 32 and the barrier layer 34 are completely short-circuited by the second superconductor 22, the electrical characteristics of the Josephson junction element are as follows.
Has almost no effect.
以上の説明で明らかように、本発明によるジョセフソン
接合素子の電気的な特性は、絶縁層１４に形成された開
口部寸法３５で規定される接合バリア層３３の寸法に依
存して決まる。開口部寸法３５は、第１図で説明したよ
うにレジスト１３の屋根寸法１７に対応し、設計で規定
できるマスクパターンの寸法で直接設定でき、高い精度
で規定することができる。従って、本発明によるジョセ
フソン接合素子の電気的な特性は、マスクパリーンの設
計により容易に定めることができ、本発明によるジョセ
フソン接合素子を用いた論理回路や記憶装置の設計が容
易になる。As is clear from the above description, the electrical characteristics of the Josephson junction device according to the present invention are determined depending on the size of the junction barrier layer 33 defined by the opening size 35 formed in the insulating layer 14. The opening size 35 corresponds to the roof size 17 of the resist 13 as described with reference to FIG. 1, can be directly set by the size of the mask pattern that can be specified by design, and can be specified with high accuracy. Therefore, the electrical characteristics of the Josephson junction element according to the present invention can be easily determined by the design of the mask pareen, which facilitates the design of the logic circuit and the memory device using the Josephson junction element according to the present invention.
以上の説明において、実際のジョセフソン接合素子を用
いて回路を構成する場合必須であるアース面や、ジョセ
フソン接合素子をスイッチさせるための制御線や負荷抵
抗などについて説明を加えなかったが、これらの機能素
子や機能部は、従来のジョセフソン接合素子と全く同様
の手続きにより本発明のジョセフソン接合素子に適用で
きる。In the above description, the ground plane, which is indispensable when the circuit is constructed by using the Josephson junction element, the control line for switching the Josephson junction element, the load resistance, etc. are not described. The functional element and the functional part can be applied to the Josephson junction element of the present invention by the same procedure as that of the conventional Josephson junction element.
尚、第３図において図示してないが第１の超伝導体層が
形成される基板にはアース面およびアース絶縁層が設け
られていることは云うまでもない。Although not shown in FIG. 3, it goes without saying that the substrate on which the first superconductor layer is formed is provided with a ground plane and a ground insulating layer.
第４図に本発明のジョセフソン接合素子の具体的実施例
として、電流制御ゲート回路の構造を示す。図で第３図
と同一構成要素は、同一番号で示し第１の実施例と同じ
構造を取るのでここでは説明を省略する。表面を酸化処
理したシリコン基板４１の上にアース面４２をニオブな
どの超伝導体で形成し、アース面の陽極酸化とシリコン
酸化物などでアース絶縁層４３を形成し、その上に第３
図に示した第１の実施例のジョセフソン接合素子を形成
する。第２の超伝導体２２を絶縁する第２の絶縁層４４
を必要部に形成し、その上にジョセフソン接合素子のス
イッチを制御する超伝導体からなる制御線４５，４６を
形成する。第１の超伝導体１２，第２の超伝導体２２，
制御線４５，４６は、必要に応じて他の回路へそれぞれ
配線され、所望の回路が実現される。FIG. 4 shows the structure of a current control gate circuit as a specific embodiment of the Josephson junction device of the present invention. In the figure, the same components as those in FIG. 3 are designated by the same reference numerals and have the same structure as in the first embodiment, and therefore the description thereof is omitted here. A ground surface 42 is formed of a superconductor such as niobium on a silicon substrate 41 whose surface is oxidized, and a ground insulating layer 43 is formed by anodic oxidation of the ground surface and silicon oxide.
The Josephson junction element of the first embodiment shown in the figure is formed. A second insulating layer 44 for insulating the second superconductor 22
Is formed in a necessary portion, and control lines 45 and 46 made of a superconductor for controlling the switch of the Josephson junction element are formed thereon. The first superconductor 12, the second superconductor 22,
The control lines 45 and 46 are respectively wired to other circuits as needed to realize a desired circuit.
以上で説明したように、本発明によるジョセフソン接合
素子は、接合バリア層を形成する領域へ食い込んだ絶縁
体の薄層１６により生ずる接合バリア層の形状の変化を
防ぐために、絶縁層の薄層１６と第１の超伝導体１２に
接する第３の超伝導体３１を形成し、第３の超伝導体３
１に接して接合層３３を設け、第３の超伝導体３１と第
２の超伝導体２２との間で超伝導トンネル効果を生じさ
せることを特徴とするもので、第１の実施例に示した基
本的な構成を発展させて、実施例で示した以外の種々の
ジョセフソン接合素子が実現される。As described above, in the Josephson junction device according to the present invention, in order to prevent the change in the shape of the junction barrier layer caused by the thin layer 16 of the insulating material that digs into the region forming the junction barrier layer, the thin layer of the insulating layer is formed. 16 to form a third superconductor 31 in contact with the first superconductor 12,
1 is provided with a bonding layer 33 so as to cause a superconducting tunnel effect between the third superconductor 31 and the second superconductor 22. In the first embodiment, By developing the basic configuration shown, various Josephson junction devices other than those shown in the embodiments are realized.
前記第３図，第４図を用いて説明した本発明の基本構造
と実施例において用いた超伝導体としては、今日用いら
れているニオブ，鉛合金等の超伝導体が用いられ、絶縁
層及び接合バリア層としては、シリコンの酸化物，超伝
導体等の金属の酸化物などが用いられる。As the superconductor used in the basic structure and embodiment of the present invention described with reference to FIGS. 3 and 4, superconductors such as niobium and lead alloys used today are used, and the insulating layer As the bonding barrier layer, silicon oxide, metal oxide such as superconductor, or the like is used.
このように前記本発明によれば、設計値からの寸法ずれ
を最小とした接合バリア層を形成できるジョセフソン接
合素子が実現され、素子の電気的な特性の設計値からの
ずれが最小となり、論理回路や記憶装置の設計を容易に
することができる。As described above, according to the present invention, a Josephson junction device capable of forming a junction barrier layer having a minimum dimensional deviation from the design value is realized, and the deviation of the electrical characteristics of the element from the design value is minimized, It is possible to easily design the logic circuit and the storage device.
第１図は絶縁層が逆台形のレジストの傘下に食込むこと
を説明するためのレジストと絶縁層の断面図、第２図は
従来のジョセフソン接合素子の基本構造を示す図、第３
図は本発明のジョセフソン接合素子の基本構造を示す
図、第４図は本発明のジョセフソン接合素子の実施例の
構造を示す図である。 図において、 １１…基板、１２…第１の超伝導体、１３…逆台形の形
状のレジスト、１４，１５…絶縁層、１６…接合バリア
層の開口部の領域へ食い込んだ絶縁層の薄層、１７…レ
ジストの屋根寸法、１８…レジスト底寸法、２１，３３
…接合バリア層、２２…第２の超伝導体、３１…第３の
超伝導体、３２…接合バリアを形成する開口部以外の領
域の第３の超伝導体、３４…接合バリア層と同一物質の
バリア層、３５…接合バリア層を形成する開口部寸法、
４１…シリコン基板、４２…アース面、４３…アース絶
縁層、４４…第２の絶縁層、４５，４６…制御線。FIG. 1 is a cross-sectional view of a resist and an insulating layer for explaining that the insulating layer bites under an inverted trapezoidal resist, and FIG. 2 is a diagram showing a basic structure of a conventional Josephson junction device.
FIG. 4 is a diagram showing a basic structure of a Josephson junction element of the present invention, and FIG. 4 is a diagram showing a structure of an embodiment of the Josephson junction element of the present invention. In the figure, 11 ... Substrate, 12 ... First superconductor, 13 ... Inverted trapezoidal resist, 14, 15 ... Insulating layer, 16 ... Thin layer of insulating layer that digs into the opening region of the junction barrier layer , 17 ... resist roof size, 18 ... resist bottom size, 21, 33
... junction barrier layer, 22 ... second superconductor, 31 ... third superconductor, 32 ... third superconductor in region other than opening forming junction barrier, 34 ... same as junction barrier layer Barrier layer of material, 35 ... Dimension of opening forming junction barrier layer,
41 ... Silicon substrate, 42 ... Ground plane, 43 ... Ground insulating layer, 44 ... Second insulating layer, 45, 46 ... Control line.
Claims (1)
超伝導体層表面に貫通する開口部を備えた絶縁層と、こ
の絶縁層上および前記開口部に設けられた第３の超伝導
体層と、この第３の超伝導体層上に設けられた接合バリ
ア層と、この接合バリア層上に設けられた第２の超伝導
体層とからなり、前記絶縁層上の前記第３の超伝導体と
前記開口部に設けられた第３の超伝導体とが、前記開口
部の側壁を形成する前記絶縁層の主段差によって電気的
に絶縁され、開口部に形成された接合バリア層によって
ジョセフソン接合素子の特性が定まることを特徴とする
ジョセフソン接合素子1. An insulating layer provided on a first superconductor layer and having an opening penetrating the surface of the first superconductor layer, and a first insulating layer provided on the insulating layer and on the opening. 3 superconductor layer, a junction barrier layer provided on the third superconductor layer, and a second superconductor layer provided on the junction barrier layer. Of the third superconductor and the third superconductor provided in the opening are electrically insulated by the main step of the insulating layer forming the sidewall of the opening, and are formed in the opening. Josephson junction device characterized in that the characteristics of the Josephson junction device are determined by the formed junction barrier layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57027610A JPH0644643B2 (en) | 1982-02-23 | 1982-02-23 | Josephson junction element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57027610A JPH0644643B2 (en) | 1982-02-23 | 1982-02-23 | Josephson junction element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58145172A JPS58145172A (en) | 1983-08-29 |
| JPH0644643B2 true JPH0644643B2 (en) | 1994-06-08 |
Family
ID=12225693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57027610A Expired - Lifetime JPH0644643B2 (en) | 1982-02-23 | 1982-02-23 | Josephson junction element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0644643B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6135579A (en) * | 1984-07-27 | 1986-02-20 | Agency Of Ind Science & Technol | Josephson junction element |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5282090A (en) * | 1975-12-27 | 1977-07-08 | Fujitsu Ltd | Apparatus and manufacture for superconductor |
-
1982
- 1982-02-23 JP JP57027610A patent/JPH0644643B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58145172A (en) | 1983-08-29 |
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