JPH064437A - First-in first-out buffer with error display function and control method for read-out device using same - Google Patents

Abstract

PURPOSE:To detect a data error in the FIFO which is used to give and receive data between devices which are operating a synchronously to each other and constructed so that the device of a read-out side can access and arbitrary register of the inside. CONSTITUTION:A valid data counter means 110 is counted up at every write operation of transfer data 103 to a register means 104, and counted down at every read-out operation. A flag value 105 held by a flag holding means 106 is set to a first value, when the transfer data 103 is written in the register means 104 corresponding thereto, and on the contrary, set to a second value, when the data is read out. A reading-out device 102 discriminates generation of an error by a count value 114 or a flag value 105. Also, an illegal data output means 117 outputs illegal data 116 to the reading-out device 102 at the time of illegal access.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a first-in first-out buffer (FIFO) used for exchanging data between devices operating asynchronously with each other, and a control method of a reading device using the same. .

[0002]

2. Description of the Related Art A first-in first-out buffer (FIFO) is basically a buffer having a structure in which the first input data is taken out first and operates asynchronously with each other. When data is transferred from one device to another device, the difference in data input / output timing can be effectively absorbed.

When such a FIFO is used, if the device on the write side writes data to the FIFO one after another at a timing when the device on the read side does not read data from the FIFO, the data overflows in the FIFO. Occurs and transfer data is lost. On the other hand, the device on the reading side performs the FIFO operation at the timing when the device on the writing side does not write data to the FIFO.
If data is read from O one after another, meaningless data that has not been written is actually read from the writing side device.

Therefore, a normal FIFO has a function of displaying that no more data can be written or that there is no more data to be read. These functions can be realized by monitoring the positional relationship between the write pointer that indicates the data write position and the read pointer that indicates the data read position, which is designated for the ring register that constitutes the FIFO.

That is, the state in which the position of the write pointer is about to overtake the position of the read pointer indicates that the data cannot be written any more, and the position of the read pointer is equal to the position of the write pointer. The overtaking condition indicates that there is no more data to be read.

Here, there is a FIFO having a structure in which the device on the writing side sequentially writes data to the FIFO, and the device on the reading side can access any register in the FIFO by addressing.

[0007]

However, in a FIFO having such a structure, the position of the write pointer and the position of the read pointer do not always have a correlation, and therefore the positions of these pointers are simply related. There is a problem that it is not possible to detect the overflow or depletion of data in the FIFO only by monitoring the relationship.

An object of the present invention is to enable a device on the reading side to detect a data error in a FIFO having a structure capable of accessing an arbitrary register in the FIFO.

[0009]

FIG. 1 is a block diagram of the present invention. The present invention is based on the first-in first-out buffer 118 that temporarily holds the transfer data 103 transferred from the writing device 101 to the reading device 102.

First, it has a plurality of register means 104 of # 1, ..., #X, ..., #n for temporarily holding a plurality of sets (n sets) of transfer data 103. Flag holding means 106 for holding a plurality of flag values 105 of # 1, ..., #X, ..., #n corresponding to the plurality of register means 104,
Next, transfer data write instruction 1 from the writing device 101
The write counter means 108 performs a count operation sequentially and continuously based on 07.

Further, the count-up operation is sequentially performed based on the transfer data write instruction 107, and the count-down operation is sequentially performed based on the transfer data read instruction 109 from the reading device 102. It has a valid data counter means 110 capable of counting up to a value of n or more.

Further, based on the transfer data write instruction 107, the writing device 10 is added to the register means 104 corresponding to the count value 111 output from the write counter means 108.
It has write control means 112 for writing the transfer data 103 from 1 and setting the flag value 105 in the flag holding means 106 corresponding to the register means 104 to a first value, for example "1".

Then, based on the read instruction 109 and the address 113 designated by the reading device 102, the contents of the arbitrary register means 104, the count value 114 of the valid data counter means 110, or the flag holding means 106.
Outputs the arbitrary flag value 105 held by the reading device 102 and outputs the flag value 105 in the flag holding means 106 corresponding to the register means 104 to the second value when the content of the arbitrary register means 104 is output. For example, it has a read control means 115 for setting it to "0".

According to the present invention, in addition to the above configuration, the reading device 102 attempts to read the contents of the register means 104 when the count value 114 of the valid data counter means 110 exceeds the number n of the register means 104. When the reading device 102 attempts to read the contents of the register means 104 corresponding to the flag value 105 having the second value held in the flag holding means 106, the writing device 101 transfers the transfer data 103. It may be configured to further include an illegal data output unit 117 that outputs the illegal data 116 that is not output as to the reading device 102.

Although not shown in particular, the illegal data setting means for setting the illegal data 116 output by the illegal data output means 117 can be further provided in the reading device 102, for example.

With respect to the first-in first-out buffer 118 according to the present invention having the above-mentioned configuration, the reading device 102 is configured to perform the following control.
First, the reading device 102 accesses any register means 104 in the first-in first-out buffer 118.

Next, the reading device 102 determines whether or not the output value output from the first-in first-out buffer 118 as a result is the illegal data 116.

Subsequently, if the output value is not the illegal data 116, the reading device 102 receives the output value as the transfer data 103 from the writing device 101. On the other hand, in the reading device 102, the output value is incorrect data 1
If it is 16, the count value 114 of the valid data counter means 110 or the flag value 105 corresponding to the access operation held by the flag holding means 106 is read from the first-in first-out buffer 118, and based on these read values. Perform error handling.

Alternatively, the reading device 102 can be configured to perform the following control on the first-in first-out buffer 118 according to the present invention having the above-mentioned configuration.

First, the reading device 102 reads the arbitrary flag value 105 held in the flag holding means 106 from the first-in first-out buffer 118.

When the flag value 105 has the first value, the contents of the register means 104 corresponding to the flag value 105 having the first value are read from the first-in first-out buffer 118, and the writing device 1 is read.
01 as the transfer data 103.

[0022]

In FIG. 1, the first-in first-out buffer 118 always accepts the write operation of the transfer data 103 from the writing device 101, and the write control means 112 has the count value 1 from the write counter means 108.
Sequential transfer data 1 to register means 104 corresponding to 11
Write 03.

Further, the valid data counter means 110 is incremented each time the above-mentioned write operation is performed. The valid data counter means 110 counts down every read operation of the reading device 102. Therefore, when the counter value 114 is larger than the number n of the register means 104, the writing device 101 overwrites the transfer data 103 in the register means 104 before the content of the register means 104 is read by the reading device 102. It will be.

Therefore, the reading device 102 reads the count value 114 of the valid data counter means 110, and thereby the first-in first-out buffer 11 is read.
It is possible to know that the data overflow has occurred in 8.

On the other hand, the flag value 1 of #X corresponding to the register unit 104 of #X held by the flag holding unit 106, for example.
05 is set to the first value when the writing device 101 writes the transfer data 103 to the #X register means 104, and the reading device 102 sets the #X register means 104.
It is set to the second value when the transfer data 103 from is read. Therefore, the flag value 1 having the second value
It is indicated that new transfer data 103 from the writing device 101 has not yet been written in the register means 104 corresponding to 05.

Therefore, the reading device 102 reads each flag value 105 of the flag holding means 106,
It is possible to know whether or not the valid transfer data 103 in the first-in first-out buffer 118 is accessed.

Further, when the illegal access as described above is made, the illegal data output means 117 causes the illegal data 11
By being configured to output 6, the reading device 102 has a first-in first-out buffer 1.
By determining whether the access result output from 18 is the unauthorized data 116, it is possible to easily determine the unauthorized access.

As a first access method performed by the reading device 102 for the first-in first-out buffer 118, first, whether the output value output as a result of accessing the register means 104 is the illegal data 116 or not. If there is no illegal data 116, the next access is made. As a result, the writing device 101
When the frequency of writing the transfer data 103 from the
Since there is a high possibility that there is data that can be read when the reading device 101 accesses the register means 104, the first-in first-out buffer 118 is accessed about once per data. Therefore, this access form is particularly effective when it takes time to access the first-in first-out buffer 118 from the reading device 101.

In the above access method, when the output value from the first-in first-out buffer 118 is the illegal data 116, the reading device 102
Whether the overflow has occurred or whether valid data has been accessed by reading the count value 114 of the valid data counter means 110 or the flag value 105 corresponding to the access operation held by the flag holding means 106 You can know whether or not.

On the other hand, when the writing device 101 does not write much data and the register means 104 is accessed by the above-mentioned first access method, the register means 1
No data exists in 04, and the flag value 105 in the flag holding means 106 corresponding to the register means 104 is the second value.
If the frequency of
Reads out the flag value 105 first, and when it has the first value, the register means 10 corresponding thereto
By making access to No. 4, useless access can be eliminated.

[0031]

Embodiments of the present invention will now be described in detail with reference to the drawings. In the following embodiment, the CPU bus 30 is provided in the message communication device 103 of FIG. 3 described later.
2 and the network command / result bus 303 through C
The configuration of the I / O controller 315 for relaying a transmission command, a transmission result notification, or a reception result notification exchanged between the PU 313 and the network control circuit 310 is most relevant to the present invention. <Overall Configuration of Embodiment of the Present Invention> FIG. 2 is a configuration diagram of a network to which the embodiment of the present invention is applied.

A network 201 having an optical fiber ring 206 as a core includes a plurality of nodes 202 (see FIG. 2).
Are indicated by numbers such as # 000, # ***, # %%%, etc.)
Are connected.

At node 202, processor bus 2
A plurality of processors 204 are connected to 05, and the processor bus 205 is accommodated in the message communication device 203. The message communication device 203 includes the processor bus 20.
5, the processor 204 processes the message data transmitted or received, and also processes the frame in which the message data input to or output from the optical fiber ring 206 is stored.

Next, FIG. 3 is a block diagram of the message communication device 203 in the node 202 of FIG. 2 in the embodiment of the present invention. The real memory 307 functions as a communication buffer that temporarily holds message data.

The control memory 308, for each virtual page address in the virtual storage space used for message communication, if the virtual page address is assigned to the real page address in the real memory 307, the real page. The address and data indicating the page state (communication state) of the virtual page address are stored.

The processor bus interface 312 is
2 is connected to the external bus 301 and accommodates the message data and the like input from the processor 204 of FIG. 2 via the processor bus 205 via the external bus 301 and the virtual memory controller 309. 307 and vice versa, the message data and the like input from the real memory 307 via the virtual memory controller 309 and the external bus 301 are output to the processor 204 via the processor bus 205.

Further, the processor bus interface 31
2 exchanges communication control data with the CPU 313 via the external bus 301, the bus coupling unit 311, and the CPU bus 302.

Although not explicitly shown in FIG. 2, in FIG. 3, two processor buses 205 are provided for each node. Therefore, the processor bus interface 312 also
Two # 0 and # 1 are provided corresponding to each processor bus 205. Then, the # 0 processor bus interface 312 uses the control line 319 to perform contention control when the # 0 and # 1 processor bus interfaces 312 access the external bus 301. Further, the # 0 processor bus interface 312 is connected to the control lines 321 and 322.
Via a CPU bus arbiter 314 and I /
While exchanging control data regarding bus use with the O controller 315, competition control of the external bus 301 is performed, and opening / closing control of the bus coupling unit 311 is performed via the control line 320 when necessary.

The network control circuit 310 sends the frame from the CPU 313 to the CPU bus 302, I when transmitting a frame.
A control memory 308 via a control memory access bus 306 based on a transmission command input via the I / O controller 315 and the network command / result bus 303.
While accessing, read message data to be transmitted from the real memory 307 via the virtual memory controller 309 and the network data transmission bus 305, construct a transmission frame including the message data, and send it to the optical fiber ring 206. The transmission result is sent to the network command / result bus 303 and the I / O controller 31.
5 and the CPU 313 via the CPU bus 302.

Further, the network control circuit 310 receives the frame from the optical fiber ring 206 and, via the control memory access bus 306, the control memory 308.
Access the received frame to another node 2
Relay to 02. Alternatively, the message data in the received frame is extracted and the network data reception bus 30
4 to the real memory 307 via the virtual memory controller 309, and the reception result is notified to the CPU 313 via the network command / result bus 303, the I / O controller 315, and the CPU bus 302.

The CPU 313 is connected to the CPU bus 302, and is connected to the CPU bus 302 at the start of operation.
It operates according to a control program written from the PROM 316 to the program RAM 317 connected to the CPU bus 302.

The CPU 313 has a CPU bus 302,
Communication control data is exchanged with the processor bus interface 312 via the bus coupling unit 311 and the external bus 301.

Further, the CPU 313, when transmitting a frame, uses the CPU bus 302, the I / O controller 315,
And output a send command to the network control circuit 310 via the network command / result bus 303, and thereafter
From the network control circuit 310, a network command /
Result bus 303, I / O controller 315, and CP
The transmission result notification is received via the U bus 302. Conversely, the CPU 313 receives from the network control circuit 310 the network command / result bus 303, the I / O controller 315, and the CPU bus 3 when receiving a frame.
A reception result notification is received via 02.

Further, the CPU 313 has a CPU bus 302.
The page state data (data indicating the communication state) of each virtual page address in the control memory 308 is accessed via the CPU memory 302 and the virtual page address of each virtual page address in the control memory 308 is accessed via the CPU bus 302 and the virtual memory controller 309. The page address data and the real memory 307 are accessed.

The I / O controller 315 is connected to the CPU bus 302 and accommodates a peripheral device bus 318 to which external peripheral devices are connected. In addition, I / O controller 3
As described above, the relay unit 15 relays the transmission command, the transmission result notification, or the reception result notification exchanged between the CPU 313 and the network control circuit 310 via the CPU bus 302 and the network command / result bus 303. In this case, the structure of the FIFO in the I / O controller 315 that temporarily holds the transmission result notification or the reception result notification transferred from the network control circuit 310 to the CPU 313 is most relevant to the present invention. This will be described later.

Further, the I / O controller 315 is a CP
The address that U313 uses to access the external bus 301 is C
When specified for the PU bus 302, the control line 322
To the processor bus interface 312 of # 0 via
Outputs an external bus access request.

The CPU bus arbiter 314 is a C bus from the processor bus interface 312 via the control line 321.
When the PU bus access request (bus grant request) is received, the bus use request (bus grant request) is output to the CPU 313 via the control line 323, and the CPU 3
13 receives a bus use permission (bus grant acknowledge) from the control line 323 through the control line 323, and based on that, the CPU
Bus access permission (bus grant acknowledge) is sent via the control line 321 to the # 0 processor bus interface 3
Return to 12.

The virtual memory controller 309 is
Processor bus interface 312 and real memory 307
Data exchanged with the external bus 301 via the external bus 301, C
Data transmitted and received between the PU 313 and the real memory 307 or the control memory 308 via the CPU bus 302, and between the network control circuit 310 and the real memory 307 via the network data reception bus 304 or the network data transmission bus 305. The switching control and the contention control of the exchanged data are performed.

The operation of the embodiment of the present invention having the above configuration will be described. <Overall operation of inter-processor communication> Now, in FIG. 2 and FIG. 3, for example, message data is sent from one processor 204 in the node 202 of # 000 to another processor 204 in the node 202 of # ***. The overall operation when transmitting will be described.

In this case, the message data transmitted from one processor 204 in the node # 000 is the message communication device 203 in the node (hereinafter, the message communication device 203 in # 000) via the processor bus 205. Call)) to the real memory 307,
It is sent to the real memory 307 of the message communication device 203 in the node 202 of # *** (hereinafter referred to as the message communication device 203 of # ***), and then the destination from the real memory 307 via the processor bus 205. The processor 204
Transferred to. That is, the real memory 307 of each message communication device 203 functions as a communication buffer. Communication Method Between Message Communication Devices 203 Here, a special method called a network virtual storage method is applied to communication of message data between the message communication devices 203.

First, in the entire network 201 of FIG.
A virtual memory space is defined. This virtual storage space is divided into a plurality of virtual pages, and message data is communicated via these virtual pages. For example, the virtual storage space is divided into virtual page addresses of 0000 to FFFF pages (hexadecimal number). One virtual page has a fixed length (for example, 8 kilobyte length) data length that can sufficiently accommodate a packet that is one unit of message data. Unless otherwise specified, the virtual page address and the dictated real page address are represented by hexadecimal numbers.

Next, the message communication device 203 of each node 202 connected to the network 201 is allocated for every predetermined number of pages of this virtual storage space, for example, every 16 pages. For example, the message communication device 203 of the # 000th node 202 is allocated to the 0000 to 000F page, the message communication device 203 of the # 001th node 202 is allocated to the 0010 to 001F page, and so on. ** 0-*** F page and %%% 0-%%% F page (3 digit *
And% are arbitrary numbers in hexadecimal numbers 0 to F), the message communication device 203 of each node 202 of the # *** th and # %%% th is assigned.

Therefore, in the above example, the network 20
1, a maximum of 3096 message communication devices 203 from # 000 to #FFF can be connected. On the other hand, the real memory 307 in each message communication device 203 is divided into a plurality of real pages each having the same data length as the above-mentioned virtual page. The page capacity of the real memory 307 may be much smaller than the page capacity of the virtual storage space, and may be, for example, about 64 to 256 pages.

Next, in the control memory 308 of each message communication device 203, as shown in FIG. 4, control data for all virtual page addresses are stored. As shown in FIG. 4, the control data of each virtual page address indicates the real page address data of the real memory 307 in the own message communication device 203 associated with the virtual page address and the communication state of the virtual page address. And page status data shown.

Then, as an initial state, each node 202
In the control memory 308 of the message communication device 203 in the internal message communication device 203, the virtual page address assigned to the node 202 is set to an arbitrary empty page in the real memory 307 of the message communication device 203 by the network reception control function of the CPU 313. The real page address of the network receiving buffer provided in the above and the receiving buffer allocation state VP as the page state are respectively written in advance. The network reception control function is a CP
This is realized by the U313 executing the control program stored in the program RAM 317.

For example, the # 000 message communication device 203
In the control memory 308 of the own message communication device 2
As shown in FIG. 4, each virtual page address of 0000,0001, ..., 000F pages assigned to the 03 is assigned to each real page of s, q, ..., p in the real memory 307. The address has been written and the page status VP indicating the receive buffer allocation status has been written.

Further, in the control memory 308 of the message communication device 203 of # ***, the own message communication device 20
As shown in FIG. 4, each virtual page address of **** 0, *** 1, ..., *** F page assigned to
The page status indicating the receive buffer allocation status in which each real page address of v, u, ..., T in the real memory 307 is written.
VP is written.

Similarly, # %%% message communication device 203
In the control memory 308 of the own message communication device 2
, %%% 0, %%% 1, ..., %%% F, the virtual page addresses of the pages of the real memory 307 include y, w, and , X are written, and the page state VP indicating the receive buffer allocation state is written.

Now, by the transfer operation described later, for example, # 000
Message data is transferred from one processor 204 in the node # 000 202 to a network transmission buffer (to be described later) whose real page address is r in the real memory 307 of the message communication device 203 of FIG. To do.

The network transmission control function of the CPU 313 analyzes the destination address part in the header of the message data stored in the network transmission buffer in the real memory 307 via the CPU bus 302 and the virtual memory controller 309. By doing so, the virtual page address assigned to the node 202 in which the processor 204 corresponding to the destination address is accommodated is determined as the one whose page state is the buffer unallocated state NA. In the example of FIG. 4, for example, the virtual page address *** 2 is determined. The network transmission control function is realized by the CPU 313 executing the control program stored in the program RAM 317.

Next, the network transmission control function of the CPU 313 writes the real page address of the network transmission buffer in which the above-mentioned message data is stored in the above-determined virtual page address in the control memory 308, and the page Change the status from the buffer unallocated status NA to the transmission status SD. In the example of FIG. 4, the real page address r and the transmission state SD are set to the virtual page address *** 2, for example.

The network transmission control function of the CPU 313 is the transmission F function in the I / O controller 315.
The virtual page address and the transfer length of the message data described above are written to the IFO via the CPU bus 302 together with the transmission command.

When the network control circuit 310 reads the above-mentioned transmission command or the like from the transmission FIFO in the I / O controller 315 via the network command / result bus 303, the virtual page added to the transmission command. An address is designated to the control memory 308 via the control memory access bus 306, the real page address set in the above-mentioned virtual page address is read from the control memory 308, and set in the DMA transfer register in the virtual memory controller 309. To do.

Then, the network control circuit 310
The page data of the real page address in the real memory 307 including the message data to be transmitted to the virtual memory controller 309 is transferred to the network control circuit 310 via the network data transmission bus 305.
To DMA transfer.

The network control circuit 310 extracts message data corresponding to the transfer length of the message data added to the send command from the above-mentioned page data, and the message data and the virtual page address added to the send command. And a transmission frame including the transfer length of the message data and generating the transmission frame.
Send to 6. The token ring network method is adopted as the frame transmission method of the optical fiber ring 206, and the network control circuit 310 can send a transmission frame only when a free token circulating on the optical fiber ring 206 is acquired. .

In the example of FIG. 4, the transmission frame including the virtual page address *** 2 and the message data stored in the real page address r in the real memory 307 from the message communication device 203 of # 000 is It is sent to the optical fiber ring 206.

The above-mentioned transmission frame is transmitted to another node 202 (see FIG. 2) connected to the optical fiber ring 206.
Are sequentially transferred to. When the network control circuit 310 of the message communication device 203 in each node 202 fetches the transmission frame from the optical fiber ring 206, the page state corresponding to the virtual page address stored in the transmission frame is set to the control memory access bus 306. Read from the control memory 308 via the, and whether the page status is the receive buffer allocation status VP, that is, whether the virtual page address is assigned to the message communication device 203 of the own node 202, or the page It is determined whether or not the state is the transmission state SD, that is, whether or not the transmission frame is transmitted by the own network control circuit 310.

When the network control circuit 310 determines that the page state of the virtual page address stored in the transmission frame is the reception buffer allocation state VP,
The message data stored in the transmission frame is taken into the real memory 307 as follows.

That is, the network control circuit 310 first specifies the virtual page address stored in the transmission frame to the control memory 308 via the control memory access bus 306, and the control memory 308 changes the virtual page address to the above virtual page address. The set real page address is read out and set in the DMA transfer register in the virtual memory controller 309. Then, the network control circuit 310 causes the virtual memory controller 309 to
The message data included in the transmission frame is DMA-transferred to the above-mentioned real page address in the real memory 307 via the network data reception bus 304.

After that, the network control circuit 310
The virtual page address stored in the transmission frame is
Control memory 30 via control memory access bus 306
8 is specified, and the page status of the virtual page address is changed from the reception buffer allocation status VP to the reception completion status RD.

Further, the network control circuit 310 is
The virtual page address extracted from the transmission frame and the transfer length of the message data are written into the reception FIFO in the / O controller 315 via the network command / result bus 303 together with the result code indicating the success or failure of the reception.

Finally, the network control circuit 310
After writing the reception success notification in the response area in the above-mentioned transmission frame received from the optical fiber ring 206, the transmission frame is sent to the optical fiber ring 206 again.

For example, in the example of FIG. 4, the network control circuit 310 of the message communication device 203 of # *** is # 000.
The message stored in the transmission frame is determined by determining that the page state on the control memory 308 of the virtual page address *** 2 stored in the transmission frame from the node 202 is the reception buffer allocation state VP. The data is transferred to the real memory 30 having the real page address u set to the virtual page address *** 2 of the control memory 308.
After fetching in the network reception buffer in 7, the page state of the virtual page address *** 2 of the control memory 308 is changed from the reception buffer allocation state VP to the reception completion state RD.

The above-mentioned reception result notification is received by the CPU 313 via the CPU bus 302. That is, CP
The U313 network reception control function uses the reception F in the I / O controller 315 via the CPU bus 302.
When the above reception result notification is received from the IFO and if the result code is successful in reception, the virtual page address which is a part of the reception result notification is designated to the control memory 308 via the CPU bus 302, and the page state Read the real page address.

If the above-mentioned page state is the reception completion state RD, the network reception control function of the CPU 313 first controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to make the above-mentioned real state. Separates the real page specified by the page address from the network receive buffer and connects it to the processor send-wait buffer queue.

After that, the network reception control function of the CPU 313 controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to connect an arbitrary empty page to the network reception buffer, and further Control memory 3 via CPU bus 302 with a virtual page address that is part of the reception result notification
08 is accessed, and the real page address of the above-mentioned empty page and the reception buffer allocation state VP as the page state are written to the virtual page address.

Thereafter, the processing for the processor transmission waiting buffer queue in the real memory 307 is performed by the CPU 31.
3 from the network reception control function to the processor transmission control function described later.

On the other hand, the network control circuit 310 reads the page state corresponding to the virtual page address stored in the transmission frame from the control memory 308, and as a result, the page state is neither the reception buffer allocation state VP nor the transmission state SD. If it is determined that the transmission frame is transmitted, the transmission frame is directly transmitted to the optical fiber ring 206.

For example, in the example of FIG. 4, the network control circuit 310 of the # %%% message communication device 203 uses # 000
By determining that the page state on the control memory 308 of the virtual page address *** 2 stored in the transmission frame from the node 202 of the node 202 is neither the reception buffer allocation state VP nor the transmission state SD, the transmission frame is left as it is. It is sent to the optical fiber ring 206.

Optical fiber ring 206 as described above
The transmission frame sequentially transferred above returns to the network control circuit 310 of the message communication device 203 in the node 202 which is the transmission source.

The source network control circuit 310 is
As a result of reading out the page state corresponding to the virtual page address stored in the transmission frame from the control memory 308, by determining that it is the transmission state SD,
It is determined that the transmission frame is the transmission frame transmitted by the own network control circuit 310.

In this case, the network control circuit 310
After confirming that the reception success notification is written in the response area of the received transmission frame, the control memory 308 of the control memory 308 corresponding to the virtual page address stored in the transmission frame is transmitted via the control memory access bus 306. The page state is changed from the transmission state SD to the transmission completion state SC.

Then, the network control circuit 310 is
The virtual page address extracted from the transmission frame is written to the reception FIFO in the I / O controller 315 via the network command / result bus 303 together with the result code indicating the success or failure of the transmission.

The above-mentioned transmission result notification is received by the CPU 313 via the CPU bus 302. That is, CP
The network transmission control function of the U313 is performed by the reception F in the I / O controller 315 via the CPU bus 302.
When the above result notification is received from the IFO, if the result code is successful, the virtual page address that is a part of the result notification is specified in the control memory 308 via the CPU bus 302, and the page status is changed. Read the real page address.

If the above-mentioned page state is the transmission completion state SC, the network transmission control function of the CPU 313 first controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to make the above-mentioned real state. The real page specified by the page address is separated from the network send buffer and used as a free page.

After that, the network transmission control function of the CPU 313 controls the control memory 3 via the CPU bus 302 with the virtual page address which is a part of the above-mentioned transmission result notification.
08 is accessed, and the buffer unallocated state NA is written as the page state of the virtual page address.

As described above, the network 201 (see FIG.
In the above, one virtual storage space is defined, and a virtual page having a fixed data length that constitutes this space is assigned to each message communication device 203. Communication of message data between the message communication devices 203 is performed using this virtual page. As a result, blocking control and sequence control that are performed in normal packet communication are not required.

When the network control circuit 310 of the message communication device 203 in each node 202 on the optical fiber ring 206 receives a transmission frame, the network control circuit 310 in the control memory 308 uses the virtual page address stored in the transmission frame. By accessing the page state, the received transmission frame can be processed at high speed.

In addition, a response area is provided in the transmission frame transferred on the optical fiber ring 206, and the network control circuit 310 of the message communication device 203 in the node 202 on the reception side transmits the reception result of the transmission frame. It writes in the response area of the frame and sends it out again to the optical fiber ring 206. Therefore, by the time this transmission frame is transferred on the optical fiber ring 206 and returned to the transmission source, the message data transmission processing is completed, and the response from the reception side to the transmission source is sent using another frame. No need to notify. As a result, the communication protocol can be simplified and high-speed response processing can be performed.

Further, the communication of the message data between the message communication devices 203 is performed using the real memory 307 while the network control circuit 310 in the message communication device 203 accesses the control memory 308, and the processor 204 and the message communication device 203. The communication of message data between 203 is performed by the message communication device 2 as described later.
The processor bus interface 312 in 03 uses the real memory 307 independently of the operation of the network control circuit 310 described above. Further, the correspondence between the message data stored in the real page address in the real memory 307 and the virtual page address in the virtual storage space is as described below, in which the CPU 313 sends the destination address in the header added to the message data. Based on. Therefore, between the processor 204 and the message communication device 203,
Message communication device 203 and message communication device 203
It is possible to efficiently perform the processing between them at high speed. From the processor 204 at the sender to the message communication device
Operation of Transferring Message Data to Device 203 Next, from one processor 204 in the source node 202 (# 000 node 202 in the example of FIG. 4) to the real memory 307 of the message communication device 203 in that node, The operation when the message data is transferred will be described.

First, the processor reception control function of the CPU 313 accesses the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to connect the processor reception buffer queue to the free buffer queue in the real memory 307. Connect the free buffer that is being used. The processor reception control function is a function realized by the CPU 313 executing the control program stored in the program RAM 317.

The processor reception control function of the CPU 313 activates, for example, the # 0 processor bus interface 312 via the CPU bus 302, the bus coupling unit 311, and the external bus 301. The start address of the above-mentioned processor receive buffer queue is notified.

The processor bus interface 312 is
The message data transferred from the processor 204 via the processor bus 205 is received, and the received message data described above is updated while sequentially updating the buffer address with the start address as the reception start address.
External bus 301 and virtual memory controller 30
9 is sequentially transferred to an empty buffer connected to the processor reception buffer queue in the real memory 307.

The processor bus interface 312 is
When there is no free buffer connected to the processor reception buffer queue, the free buffer is automatically stopped, and the fact is notified to the CPU 313 via the external bus 301, the bus coupling unit 311, and the CPU bus 302.

The processor reception control function of the CPU 313 first controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to separate the above-mentioned received buffer from the processor reception buffer queue and transmit it to the network. Connect to a buffer. Thereafter, the processing for the network transmission buffer in the real memory 307 is transferred from the processor reception control function of the CPU 313 to the network transmission control function described above, and the transmission source of the transmission source is transmitted in accordance with the communication method between the message communication devices 203 described above. From the real memory 307 in the message communication device 203 of the node 202 (# 000 message communication device 203 in the example of FIG. 4), the message communication device 203 of the node 202 (in the example of FIG. 4) in which the destination processor 204 is accommodated # *** message communication device 20
The message data transfer operation to the real memory 307 in 3) is executed. From the message communication device 203 on the receiving side to the process
Transfer Operation of Message Data to Server 204 Next, the real memory 3 of the message communication device 203 in the receiving node 202 (# 202 node 202 in the example of FIG. 4).
07 to one processor 204 in that node 202
The operation when the message data is transferred will be described below.

When the network control circuit 310 succeeds in receiving the transmission frame, as described above, the CPU 313
The network reception control function of (1) connects the received message data to the processor transmission waiting buffer queue in the real memory 307.

On the other hand, the CPU transmission control function of the CPU 313 includes the CPU bus 302 and the bus coupling unit 31.
For example, the # 0 processor bus interface 312 is activated via 1 and the external bus 301, and the interface 312 is notified of the start address of the above-mentioned processor transmission waiting buffer queue.

The processor bus interface 312 is
While sequentially updating the buffer address with the start address as the transmission start address, the real memory 30 is accessed via the external bus 301 and the virtual memory controller 309.
7 sequentially reads the message data stored in the buffer connected to the processor transmission waiting buffer queue, analyzes the destination address part in the header of the message data, and transfers the message data to the processor bus 205. Via the destination processor 204. <Explanation of I / O Controller Part for Processing Transmission / Reception Result Notification> Next, in the configuration of the I / O controller 315 of FIG.
FIF in the I / O controller 315 that temporarily holds the above-mentioned transmission result notification or reception result notification transferred to
O will be explained. The configuration of this part is most relevant to the present invention. The CPU 313 to the network control circuit 3
The present invention can also be applied to the FIFO in the I / O controller 315 for holding the transmission command transferred to 10, but its configuration is omitted.

FIG. 5 is a block diagram of a FIFO formed in the I / O controller 315 that temporarily holds the above-mentioned transmission result notification or reception result notification. In FIG. 5, the network control circuit 310 is connected to the four registers R _{0 to} R _3.
The data of the above-mentioned transmission result notification or reception result notification is written from the above via the data bus of the network command / result bus 203.

On the other hand, the CPU 313 operates the address decoder 50 via the address bus of the CPU bus 302.
By setting the register address in 9, the selectors 510 and 511, the buffer 513 to the CPU bus 30
Any of the contents of the registers R _{0 to} R ₃ can be read out via the second data bus, and this content is passed to the network transmission control function or the network reception control function of the CPU 313 described above.

The timing generation circuit 501 operates from the network control circuit 310 to the network command / result bus 20.
A write signal FIFOW for writing to the registers R _{0 to} R ₃ is generated based on a control signal instructing the writing of the data output to the control bus No. ₃ .

The write 2-bit counter 502 is a counter for determining which of the registers R _{0 to} R ₃ is to be written with data, and its count value increases to 0, 1, 2, 3. After that, it changes to 0 again. Therefore, the writing of data from the network control circuit 310 requires the registers R ₀ , R ₁ , R ₂ , R ₃ and R _3
0 , ..., Sequentially and cyclically.

By asserting the write signal FIFOW, the count value of the write 2-bit counter 502 becomes 1
The output WDEC of the decoder 503 according to the count value X (X is an arbitrary number from 0 to 3 inclusive; hereinafter, X is also used as a subscript) that increases and changes from X to X + 1 and before increasing. _X changes from asserted state to negated state.

At the timing of this change, the data of the above-mentioned transmission result notification or reception result notification is written from the network control circuit 310 to the register R _X. For writing 2
As a result of the value of the bit counter 502 being incremented by 1, the output WDEC of the decoder 503 according to the incremented count value
_{X + 1} is asserted. However, when X = 3, WD
EC ₃ is negated and WDEC ₀ is asserted at the same time.

The decoder 50 immediately before being negated
The write signal FI is input to the D-flip-flop D-FF _X in the #X flag circuit 504 to which the output WDEC _{X of} 3 is input.
A signal of logic "1" is set at the timing when FOW is asserted.

The content of this D-FF _X is specified by the register address from the CPU 313 via the address bus of the CPU bus 302, and the address decoder 509 registers the register R.
_When the decode output RDEC _X designating _X is asserted, it is returned to logic "0".

That is, in the D-FF _X , when the logic of the signal set in the D-FF _X is “1”, the network control circuit 310 writes the register R _X and the CPU 3
13 indicates that there is valid data that has not yet been read, and the logic of the signal set in it is "1".
, It means that there is no valid data in the register R _X.

From the #X flag circuit 504, D-FF _X
Output DFF _X and the value count for count check
_X is output. The value of count _X is determined by the value of the decode output RDEC _X from the address decoder 509 described later and the value of the output DFF _X of D-FF _X. This will be described later.

The 3-bit valid data counter 505 in the count check circuit 506 is a counter for detecting data overflow in the registers R _{0 to} R ₃ .

The count value of the 3-bit valid data counter 505 is incremented by 1 each time the write signal FIFOW is asserted and the data is written to the register R _X , and is registered from the CPU 313 via the address bus of the CPU bus 302. Every time an address is designated and the address decoder 509 outputs the decode output RDEC _X , it is decremented by 1 based on the read signal FIFOR output from the address.

Therefore, when the value of the 3-bit valid data counter 505 exceeds 4, the contents of the register R _X becomes CP.
It means that the network control circuit 310 has overwritten the register R _X before it is read by the U 313.

When the count check circuit 506 detects that the value of the 3-bit valid data counter 505 exceeds 4, it asserts the error detection signal thru. On the other hand, the output DFF of D-FF _{X in} the #X flag circuit 504.
_If the logic of _X is logic "0" indicating that valid data is not written in the register R _X , the CPU 31
When the decode output RDEC _X of the address decoder 509 is asserted by 3 accessing the content of the register R _X to access it, the #X flag circuit 504 asserts the count check output count _X. To the negate state.

As a result, the count check circuit 506
Asserts the error detection signal thru based on the count check output count _X that has changed to the negated state.

When the error detection signal thru is asserted, the selector 511 selects not the output of the selector 510 but the all “1” illegal pattern held in the register 512, and the CPU bus 302 via the buffer 513. Output to the data bus. It is assumed that this all “1” illegal pattern is a data pattern that is not written from the network control circuit 310 to the registers R _{0 to} R ₃ .

The CPU 313 detects the illegal pattern to detect the FI in the I / O controller 315.
It is possible to know that an unauthorized access has occurred in the FO.

The CPU 313 is the I / O controller 31.
When reading the contents of registers R _{0 to} R _{3 in} 5,
For example, the data reception program shown in the operation flowchart of FIG. 6 is executed. This program is stored in the program RAM 317 of FIG.

First, the CPU 313 determines that the CPU bus 302
A register address for accessing, for example, the register R ₀ is set in the address decoder 509 via the address bus of (1), and a read instruction is output to the control bus of the CPU bus 302 (step S601).

When the above-mentioned read instruction from the CPU 313 is generated, the control circuit 507 causes the internal arbiter circuit 50 to operate.
8, the write signal FIFOW is checked to determine whether the read instruction from the CPU 313 and the write instruction from the network control circuit 310 are simultaneously generated, and if access conflict occurs, the arbitration is performed. I do.

When the control circuit 507 receives the read instruction from the CPU 313, the address decoder 509 outputs the decode output RDEC ₀ to the selector 510,
The selector 510 selects the output of the register R ₀ .

As a result, if the above-mentioned access from the CPU 313 is not an illegal access, the output of the register R ₀ is output from the selectors 510 and 511 and the buffer 513 to the CP.
It is output to the data bus of the U bus 302. On the other hand, when the above-mentioned access from the CPU 313 is an unauthorized access, the error detection signal thru is asserted as described above, so that the selector 511 causes the selector 5 to operate.
Instead of the output of 10, the incorrect pattern of all “1” held in the register 512 is selected, and the buffer 513 is selected.
To the data bus of the CPU bus 302 via.

The CPU 313 is the CPU bus 302 described above.
The contents of the register output to the data bus are read (step S602). Subsequently, the CPU 313 determines whether the above-mentioned data is correct data, that is, whether it is an illegal pattern (step S602).

If the data is not an illegal pattern, the register address is incremented by _1, and the register address for accessing the next register R ₁ is set in the address decoder 509 via the address bus of the CPU bus 302, A read instruction is output to the control bus of the CPU bus 302 to access the register (step S
604 → S602). If the previous register address was the address to access the register R ₃ ,
The next register address is, for example, an address for accessing the register R ₀ .

On the other hand, when the read data is an illegal pattern, the CPU 313 designates the address for accessing the count check circuit 506 to the address decoder 509 via the address bus of the CPU bus 302, and thereby the address decoder Based on a decode output (not shown) from the selector 509, selectors 510, 5
11. The count value of the 3-bit valid data counter 505 in the count check circuit 506 is acquired from the buffer 513 via the data bus of the CPU bus 302, and whether or not the count value exceeds 4; It is determined whether it has occurred (step S60).
5).

If it is determined in step S605 that an overflow has occurred, the register R ₀
Before the contents of R ₃ to R ₃ are read by the CPU 313, the network control circuit 310 overwrites any of the registers R _{0 to} R ₃ , so that the CPU 31
3 executes error processing such as a request for resending the data of the transmission result notification or the reception result notification described above to the network control circuit 310 (step S606).

On the other hand, if it is determined in step S605 that the overflow has not occurred, the CP
The U313 can determine that it has tried to read the contents of the register R _X when valid data has not been written in the register R _X , and therefore accesses the register again after taking appropriate timing (step S60
5 → S602).

The CPU 313 is the CPU bus 302.
#X to the address decoder 509 via the address bus of
By designating an address for accessing the D-FF _X in the flag circuit 504, the selectors 510 and 511, the buffer 513 to the CPU bus 30 are operated based on the decode output (not shown) from the address decoder 509.
The value of the output DFF _X of the D-FF _X can be read at any time via the second data bus.

Further, the CPU 313 executes, for example, step S.
In the error processing of 606, by outputting the reset address through the address bus of the CPU bus 302, D in the flag circuits 504 of # 0 to # 3 is output based on an output (not shown) from the address decoder 509. −
The contents of FF _{0 to} D-FF _3, the contents of the write 2-bit counter 502, and the contents of the 3-bit valid data counter 505 in the count check circuit 506 can be reset respectively. WDEC ₀ is asserted at the output of the decoder 503 in this state.

In the above access form of the I / O controller 315 by the CPU 313, as shown in FIG. 6, the CPU 313 first accesses the contents of the registers R _{0 to} R ₃ , and the data is an invalid pattern. If so, it is further checked whether or not an overflow has occurred.

In this access mode, when the frequency of writing the data of the transmission result notification or the reception result notification from the network control circuit 310 is high, there is data that can be read when the CPU 313 accesses the register R _X. Because of the high probability, the FIFO will be accessed about once per data. Therefore, this access form is particularly effective when it takes time to access the FIFO from the CPU 313.

On the other hand, the network control circuit 31
If data is not written so much from 0 and the register R _X is accessed in the above-mentioned access mode, there is no data in the register R _X and the output value of the D-FF _X in the flag circuit 504 of #X corresponding to that register. If the frequency of the DFF _X logic being "0" increases, the D-FF _X
The useless access can be eliminated by reading the contents of the above and accessing the register R _X corresponding thereto when the logic of the output value DFF _X is “1”.

Further, in the embodiment shown in FIG. 5, the illegal pattern of all "1" is held in advance in the register 512, but by configuring the CPU 313 to write an arbitrary illegal pattern in the register 512, ,
Even when the device on the writing side (network control circuit 310) is changed, it is possible to set an illegal pattern so that the device on the writing side does not output.

Further, although the illegal pattern is output via the register 512, the register 512 may be eliminated and the register 510 may be directly configured to select the output of the register 512.

[0133]

According to the present invention, the reading device reads the count value of the valid data counter means,
It becomes possible to know that a data overflow has occurred in the first-in first-out buffer.

Further, the reading device can know whether or not the valid transfer data in the first-in first-out buffer is accessed by reading each flag value of the flag holding means.

Furthermore, since the illegal data output means is configured to output the illegal data when the illegal access as described above is performed, the reading device can access the access data output from the first-in first-out buffer. By determining whether or not the result is unauthorized data, it is possible to easily determine the unauthorized access.

On the other hand, when accessing the first-in first-out buffer, the reading device first determines whether or not the output value output as a result of accessing the register means is illegal data, and the illegal data is detected. Otherwise, by performing the next access, it becomes possible to perform efficient access when the writing frequency of the transfer data from the writing device is high.

When accessing the first-in first-out buffer, the reading device first reads each flag value held by the flag holding means and accesses the register means corresponding to the flag having the first value. This makes it possible to eliminate unnecessary access to the first-in first-out buffer when the transfer device writes the transfer data infrequently.

[Brief description of drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a configuration diagram of a network to which an embodiment of the present invention is applied.

FIG. 3 is a configuration diagram of a message communication device according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of message communication.

[Fig. 5] I / O for processing a transmission result notification or a reception result notification
It is a block diagram of the part of O controller.

FIG. 6 is an operation flowchart when the CPU reads the contents of registers R _{0 to} R ₃ .

[Explanation of symbols]

 101 writing device 102 reading device 103 transfer data 104 register means 105 flag value 106 flag holding means 107 transfer data write instruction 108 write counter means 109 transfer data read instruction 110 valid data counter means 111, 114 count value 112 write control means 113 address 115 Read control means 116 Illegal data 117 Illegal data output means 118 First-in first-out buffer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04L 12/42

Claims (5)

[Claims] 1. A first-in first-out buffer (11) for temporarily holding transfer data (103) transferred from a writing device (101) to a reading device (102).
In 8), a plurality of register means (104) for temporarily holding a plurality of sets of the transfer data (103), and a flag holding means for holding a plurality of flag values (105) corresponding to the plurality of register means (104) (106)
And a write counter means (108) for sequentially and cyclically counting based on a transfer data write instruction (107) from the writing device (101), and sequentially based on the transfer data write instruction (107). The reading device (1
02) valid data counter means (110) capable of sequentially performing a countdown operation based on a transfer data read instruction (109) and counting up to a value (n) or more of the register means (104). And transfer data from the writing device (101) to the register means (104) corresponding to the count value (111) output from the write counter means (108) based on the transfer data write instruction (107). 103) and the flag value (105) in the flag holding means (106) corresponding to the register means (104)
Based on the read instruction (109) and the address (113) specified by the read device (102), and the write control means (112) for setting the value to a first value. The contents, the count value (114) of the valid data counter means (110), or the arbitrary flag value (105) held by the flag holding means (106) is output to the reading device (102) and at the same time, A read control means (115) for setting a flag value (105) in the flag holding means (106) corresponding to the register means (104) to a second value when the content of the register means (104) is output. And an FIF with an error display function characterized by having
O. 2. The valid data counter means (110)
The count value (114) of the register means (104)
The number of reading devices (10)
2) attempts to read the contents of the register means (104), or the reading device (102) has the flag value (2) held in the flag holding means (106). 105), when reading the contents of the register means (104), the writing device (101) outputs incorrect data (116) that is not output as the transfer data (103) by the reading device (102). The FIFO with an error display function according to claim 1, further comprising an illegal data output means (117) for outputting to the. 3. The FIFO with an error display function according to claim 2, further comprising illegal data setting means for setting the illegal data (116) output by the illegal data output means (117). 4. The read-out device (102) comprises the first-in first-out buffer (11).
8) Any register means (104) in 8) is accessed, and as a result, it is determined whether the output value output from the first-in first-out buffer (118) is the illegal data (116). If the output value is not the illegal data (116), the output value is received as the transfer data (103) from the writing device (101), and if the output value is the illegal data (116). If
The first-in first-out buffer (11
8) to the count value (114) of the valid data counter means (110) or the flag holding means (106)
4. The error according to claim 2, wherein the flag value (105) corresponding to the access operation held by is read, and error processing is performed based on the read value. A control method of a reading device using a first-in first-out buffer with a display function. 5. The read-out device (102) comprises the first-in first-out buffer (11).
8) read out the arbitrary flag value (105) held in the flag holding means (106), and when the flag value (105) has the first value,
The first-in first-out buffer (11
8) to the flag value (105) with the first value
4. The contents of the register means (104) corresponding to the above are read and received as the transfer data (103) from the writing device (101). A control method of a reading device using a first-in first-out buffer with an error display function.