JPH0644262B2 - Multiprocessor system - Google Patents

Multiprocessor system

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Publication number
JPH0644262B2
JPH0644262B2 JP14619588A JP14619588A JPH0644262B2 JP H0644262 B2 JPH0644262 B2 JP H0644262B2 JP 14619588 A JP14619588 A JP 14619588A JP 14619588 A JP14619588 A JP 14619588A JP H0644262 B2 JPH0644262 B2 JP H0644262B2
Authority
JP
Japan
Prior art keywords
central processing
processing unit
receiving
transaction
communication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP14619588A
Other languages
Japanese (ja)
Other versions
JPH01312660A (en
Inventor
正和 石原
雅一 塩出
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP14619588A priority Critical patent/JPH0644262B2/en
Publication of JPH01312660A publication Critical patent/JPH01312660A/en
Publication of JPH0644262B2 publication Critical patent/JPH0644262B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はマルチプロセッサシステムに関する。The present invention relates to a multiprocessor system.

〔従来の技術〕[Conventional technology]

従来のマルチプロセッサシステムの負荷制御において、
待合せ形式として各プロセッサ(中央処理装置)内の合
計した受信用信号収容量は全ての中央処理装置内の合計
した送信用信号容量を確保することにより実現されてい
た。
In load control of conventional multiprocessor system,
As a queuing format, the total reception signal capacity in each processor (central processing unit) has been realized by ensuring the total transmission signal capacity in all the central processing units.

第3図を参照すると、送信側中央処理装置1aにおい
て、受信側中央処理装置1bへの通信要求が発生した場
合、中央処理装置1a内の送信用トランザクションを捕
捉し(31)、この送信用トランザクションを使用して
受信側中央処理装置1bに送信する(33)。受信側中
央処理装置1bでは、送信側中央処理装置1aよりの通
信要求を受けると、受信用トランザクションを捕捉し
(34)、通信データを受信した後(35)、内部処理
を実行し(36)、終了報告を送信側中央処理装置1a
に返送し(37)、受信用トランザクションを解放する
(38)。送信側中央処理装置1aでは、受信側中央処
理装置1bに通信後、送信用トランザクションを保留し
た状態で受信側中央処理装置1bよりの終了報告を待ち
(39)、終了報告受信(40)で送信用トランザクシ
ョンを解放する(41)。これにより、送信側トランザ
クションの数以上に他の中央処理装置に通信することが
できないため、負荷制御が可能となる。なお、送信側中
央処理装置1aにおいて、送信用トランザクションを捕
捉したのち、送信用トランザクションの全塞りの場合は
待合せを行う(42)。
Referring to FIG. 3, in the central processing unit 1a on the transmitting side, when a communication request is issued to the central processing unit 1b on the receiving side, a transaction for transmission in the central processing unit 1a is captured (31), and this transaction for transmission is acquired. Is used to transmit to the receiving side central processing unit 1b (33). Upon receipt of the communication request from the transmission side central processing unit 1a, the reception side central processing unit 1b captures a reception transaction (34), receives communication data (35), and then executes internal processing (36). , End report sending central processing unit 1a
(37) and releases the receiving transaction (38). After transmitting to the receiving side central processing unit 1b, the transmitting side central processing unit 1a waits for an end report from the receiving side central processing unit 1b with the transaction for transmission being held (39), and sends it by the end report reception (40). Release 41 the trusted transaction. As a result, it is not possible to communicate with another central processing unit more than the number of transactions on the transmitting side, and thus load control becomes possible. In the sending side central processing unit 1a, after the sending transaction is captured, when the sending transaction is completely blocked, waiting is performed (42).

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

上述した従来のシステムにおいては、送信側トランザク
ションを解放するために必ず受信側中央処置装置より送
信側中央処理装置へ終了報告を返送する必要があり、通
信回数が1回の要求で必ず2回発生し、システムの通信
能力低下を免れない。
In the above-mentioned conventional system, it is necessary to return the end report from the receiving side central processing unit to the transmitting side central processing unit in order to release the transmitting side transaction, and the number of times of communication always occurs twice with one request. However, the communication capability of the system is inevitable.

〔課題を解決するための手段〕[Means for Solving the Problems]

本発明のマルチプロセッサシステムは、互いに通信バス
により接続された複数のプロセッサと前記複数のプロセ
ッサにより共用される共通メモリとを備え、前記複数の
プロセッサのそれぞれが有する複数の受信用トランザク
ションの輻輳状態を表示する手段を前記共通メモリに設
け、前記複数のプロセッサ間の通信に際し送信側プロセ
ッサは受信側プロセッサの前記受信用トランザクション
の輻輳状態を前記共通メモリの前記手段に基づいて識別
し輻輳状態にないとき送信する構成である。
A multiprocessor system of the present invention includes a plurality of processors connected to each other via a communication bus and a common memory shared by the plurality of processors, and sets a congestion state of a plurality of receiving transactions included in each of the plurality of processors. A means for displaying is provided in the common memory, and when communicating between the plurality of processors, the transmitting processor identifies the congestion state of the receiving transaction of the receiving processor based on the means of the common memory and is not in the congestion state. It is a configuration for transmitting.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

一実施例を示す第1図及び第2図を参照すると、このマ
ルチプロセッサシステムは通信バス2により相互接続さ
れた複数の中央処理装置1a,1b,1nを備える。中
央処理装置1a〜1nは個別に共通メモリ3に信号線4
a,4b,4nを介して接続されている。この構成にお
いて、送信側となる中央処理装置1aで通信要求が発生
すると、受信側となる中央処理装置1bの受信用トラン
ザクションの状態を共通メモリ4より読出し(11)、
輻輳状態でない場合(12)、通信バス2を介して送信
し(13)、送信側中央処理装置1aの通信処理を終了
する。一方、受信側中央処理装置1bは受信用トランザ
クションを捕捉する(15)。この後、残りの受信用ト
ランザクションの個数をチェックし(16)、基準値以
下に減っている場合(17)、後続するトランザクショ
ンの通信を止めるために共通メモリ3の該当エリアに輻
輳状態を設定する(18)。次に、通信情報を受信し
(19)、内部処理を実行し(20)、処理終了で受信
用トラザクションを解放する(21)。続いて、他の中
央処理装置からの通信を再開させるため、受信用トラン
ザクションを解放したのち、再度残りの受信用トランザ
クションの空個数をチェックし(22)、基準値より増
加している場合(23)、共通メモリ3の輻輳表示を解
除する(24)。なお、送信側中央処理装置1aにおけ
る識別効果、受信用トランザクションが輻輳状態である
場合、中央処理装置1aが待合せを行う(14)。
Referring to FIGS. 1 and 2 showing an embodiment, the multiprocessor system comprises a plurality of central processing units 1a, 1b, 1n interconnected by a communication bus 2. The central processing units 1a to 1n individually provide the common memory 3 with the signal lines 4
It is connected via a, 4b, and 4n. In this configuration, when a communication request occurs in the central processing unit 1a on the transmitting side, the state of the transaction for reception of the central processing unit 1b on the receiving side is read from the common memory 4 (11),
If it is not in the congestion state (12), it is transmitted via the communication bus 2 (13), and the communication processing of the transmission side central processing unit 1a is ended. On the other hand, the receiving side central processing unit 1b captures the receiving transaction (15). After this, the number of remaining receiving transactions is checked (16), and if the number is below the reference value (17), a congestion state is set in the corresponding area of the common memory 3 in order to stop the communication of the subsequent transactions. (18). Next, the communication information is received (19), the internal process is executed (20), and the reception transaction is released at the end of the process (21). Then, in order to restart communication from another central processing unit, after releasing the receiving transaction, the empty number of the remaining receiving transactions is checked again (22), and if it is larger than the reference value (23 ), The congestion display of the common memory 3 is canceled (24). When the identification effect in the transmitting side central processing unit 1a and the receiving transaction are in a congested state, the central processing unit 1a performs waiting (14).

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明によれば、システムの通信能
力を向上できる。
As described above, according to the present invention, the communication capability of the system can be improved.

【図面の簡単な説明】[Brief description of drawings]

第1図及び第2図は本発明の一実施例を示す図、第3図
は従来の動作を説明する図である。 1a,1b,1n……中央処理装置、2……通信バス、
3……共通メモリ、4a,4b,4n……信号線。
1 and 2 are diagrams showing an embodiment of the present invention, and FIG. 3 is a diagram for explaining a conventional operation. 1a, 1b, 1n ... Central processing unit, 2 ... Communication bus,
3 ... Common memory, 4a, 4b, 4n ... Signal line.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】互いに通信バスにより接続された複数のプ
ロセッサと前記複数のプロセッサにより共用される共通
メモリとを備え、前記複数のプロセッサのそれぞれが有
する複数の受信用トランザクションの輻輳状態を表示す
る手段を前記共通メモリに設け、前記複数のプロセッサ
間の通信に際し送信側プロセッサは受信側プロセッサの
前記受信用トランザクションの輻輳状態を前記共通メモ
リの前記手段に基づいて識別し輻輳状態にないとき送信
することを特徴とするマルチプロセッサシステム。
1. A means for displaying a congestion state of a plurality of receiving transactions included in each of the plurality of processors, comprising a plurality of processors connected to each other via a communication bus and a common memory shared by the plurality of processors. Is provided in the common memory, and in communication between the plurality of processors, the transmitting processor identifies the congestion state of the receiving transaction of the receiving processor based on the means of the common memory, and transmits when it is not in the congestion state. A multiprocessor system characterized by.
JP14619588A 1988-06-13 1988-06-13 Multiprocessor system Expired - Lifetime JPH0644262B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14619588A JPH0644262B2 (en) 1988-06-13 1988-06-13 Multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14619588A JPH0644262B2 (en) 1988-06-13 1988-06-13 Multiprocessor system

Publications (2)

Publication Number Publication Date
JPH01312660A JPH01312660A (en) 1989-12-18
JPH0644262B2 true JPH0644262B2 (en) 1994-06-08

Family

ID=15402280

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14619588A Expired - Lifetime JPH0644262B2 (en) 1988-06-13 1988-06-13 Multiprocessor system

Country Status (1)

Country Link
JP (1) JPH0644262B2 (en)

Also Published As

Publication number Publication date
JPH01312660A (en) 1989-12-18

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