JPH0644134A - Comparator - Google Patents

Abstract

PURPOSE:To provide a comparator which is suitable for a cache memory and a translation look-aside buffer, which are incorporated in a semiconductor integrated circuit, and realizes a high speed operation with small hardware quantity. CONSTITUTION:An XOR circuit 102 and an XNOR circuit 101 where a pair of bit lines 111 and 112, and a pair of comparison input lines 113 and 114 are set to be inputs are composed of path transistor logical circuits. They are arranged between the collectors and bases of the NPN transistors 103 and 104 of bipolar differential sense circuits, and the potential of load resistances 106 and 107 is set to be the output of the comparator. The saturation preventing circuit of a bipolar transistor can be realized with small hardware quantity by simultaneously executing a comparison operation and a read operation with such constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed comparator used in a cache memory or a translation lookaside buffer (TLB) of a microprocessor.

[0002]

2. Description of the Related Art Conventionally, in a microprocessor, a cache memory tag or a TLB is used with a multi-bit comparator. FIG. 6 shows a conventional example of the tag portion of the cache memory, and shows the configuration of a 24-bit comparator. 601 is a tag memory, and when the address PA 610 is decoded by the decoder 602 and the word line WL 611 becomes a high potential (hereinafter abbreviated as “H”), the data of the memory cell array selected by the word line is output to the bit line pair. To be done. Sense enable SEN612
Becomes "H", the sense circuit 603 reads the data from the tag memory as the address B [23: 0]. Address A [2 from central processing unit (CPU)
3: 0] 613 and B [23: 0] are matched / mismatched for each bit by a matching circuit 604 including an exclusive NOR gate (XNOR, logical inversion of exclusive OR), and the AND circuit 605. It is determined whether all bits match or do not match. A hit signal HIT 614 is "H" when all the bits match, and has a low potential (hereinafter abbreviated as "L") when at least one bit does not match. The RAM section of the cache memory uses this hit signal to control the input / output of data. A precharge / equalize circuit 606 precharges and equalizes the bit line pair by controlling the precharge enable PCEN 615 and the equalize enable EQEN 616 when the tag memory is not accessed. N-channel MOSF for faster read and precharge / equalization
ET is used in the precharge circuit. A write circuit 607 for writing the data W [23: 0] 618 is controlled by the write enable WEN617.

The sense circuit 603 has a high transconductance (g) for realizing high-speed reading of the memory circuit.
m) is used for the differential sense circuit. FIG. 7 shows a configuration example of the differential sense circuit. 701 and 702 are bit lines B711 and NB7
An emitter follower circuit having 12 as inputs, 703, 70
4 is an NPN transistor that constitutes a differential sense circuit,
Reference numeral 705 denotes an N-channel MOSFET for current switch, which operates only when the sense enable signal 715 is "H",
Operates as a constant current source. Reference numerals 706 and 707 are load resistances of the differential sense circuit, and 716 is an output data line.

In general, a circuit composed of bipolar transistors has a low input impedance, and when the bipolar transistor is saturated, a large base current flows, so that a circuit connected to the base, that is, a bit line has a large load. Therefore, when the memory is read, the potential of the bit line on the “H” side is considerably lowered, and if a large amount of noise is mixed in the power supply line and the ground line, there is a possibility that incorrect data may be written in the memory cell. As a method for avoiding this, 70 in FIG.
The emitter follower circuit having the features of high input impedance, low output impedance, and high current gain shown by reference numerals 1 and 702 is used to reduce the bit line load. Furthermore, since the potential lower than the bit line potential by the internal potential Vbe between the base and the emitter is input to the base of the NPN transistor of the differential sense circuit, the NPN transistor of the differential sense circuit is less likely to be saturated. is doing.

[0005]

In the above prior art, by the time the hit signal is generated, 1) the reading of the tag section, 2) the address B [23: 0] read from the tag and the address A [23: from the CPU. 0], it is necessary to perform three operations: determination of match / mismatch for each bit, and 3) determination of match / mismatch of all bits. Therefore, there is a problem that it takes time from the reading of the tag portion to the generation of the hit signal. Particularly, in 2) and 3), since the multi-bit information is compressed into a 1-bit signal, there is a problem that the number of gate stages increases and the delay time increases.

Further, since an emitter follower circuit is added,
The number of bipolar transistors increases and the area of the sense circuit increases. A bipolar transistor requiring an element isolation region on the periphery cannot be reduced in area as much as a MOSFET even if miniaturization progresses, and the area matching between the memory cell and the sense circuit cannot be obtained. Therefore, in a tag memory or TLB that requires simultaneous multi-bit reading, there is a problem in that a sense circuit having a large area cannot be provided for each bit.

The present invention is to solve the above problems,
It is an object of the present invention to provide a high-speed and small hardware amount comparator having both a sense function and a comparison function.

[0008]

In order to solve the above problems, the present invention provides a first MOSFET in which one of the first input signal line pair is connected to the gate and one of the second input signal line pair. The first MOSFE connected to the gate and to the drain
A second MOSFET to which the source of T is connected; a third MOSFET to which the other of the first input signal line pair is connected to the gate and a drain of which is connected to the drain of the first MOSFET; The other of the two input signal line pairs is connected to the gate, and the third MOSFE is connected to the drain.
The source of T is connected and the source of said second MOSF
A fourth MOSFET to which the source of ET is connected, a fifth MOSFET to which one of the first input signal line pair is connected to the gate, and the other of the second input signal line pair to the gate A sixth MOSFET having the drain connected to the source of the fifth MOSFET, and a sixth MOSFET having the other of the first input signal line pair connected to the gate and the drain connected to the drain of the fifth MOSFET. 7 MOSFET and one of the second input signal line pair is connected to the gate, the drain is connected to the source of the seventh MOSFET, and the source is the sixth MOSFET.
An eighth MOSFET having a source connected thereto, a first NPN transistor having a collector connected to the drain of the first MOSFET and a base connected to the source of the second MOSFET, and a collector connected to the fifth MOSFET. MO
A second NPN transistor connected to the drain of the SFET, the base of which is connected to the source of the sixth MOSFET, and the emitter of which is connected to the emitter of the first NPN transistor, and the signal line of the activation signal to the gate. A current switch MOSFET having a drain connected to the emitter of the first NPN transistor and a source connected to a ground line, a power supply line and the first N
A first load resistor connected between the collector of the PN transistor, a second load resistor connected between the power supply line and the collector of the second NPN transistor, and a collector of the first NPN transistor, or The second NPN
And a output line connected to the collector of the transistor.

In the second invention, the 1-bit comparator is n
Each of the output lines is connected in a wired-OR connection, and an n-bit comparator for comparing the n-bit bit line pair of the memory circuit with the first n-bit input is configured.

[0010]

According to the first aspect of the present invention, an exclusive OR circuit (XOR circuit, which receives a bit line pair and a comparison input line pair as inputs,
Exclusive OR circuit) and exclusive NOR circuit (XN
An OR circuit, an exclusive OR negation circuit) is generated by a MOSFET pass transistor logic circuit, and a base current is supplied to the NPN transistor of the differential sense circuit by turning it on and off. Whether or not there is a voltage drop across the load resistance is determined according to the match / mismatch, and the output line potential changes. Also, NP
Since the base potential of the N-transistor is clamped below the collector potential by the MOSFET of the pass-transistor logic circuit, saturation of the NPN transistor is prevented and malfunction of the memory due to reduction of the bit line potential is prevented. In this way, the differential type sense circuit and the comparator are integrated and the reading and comparing are executed at the same time, thereby shortening the reading / comparing time.

In the second invention, the 1-bit comparator is n
Since it is equipped with one and each output line is wired or connected,
If even one bit of each input signal does not match, the output line potential drops to "L", but if all match, the output line potential becomes "H". This configuration eliminates the need for a logic circuit that determines the coincidence of multiple inputs, so that the coincidence / high-speed
Mismatch can be detected.

[0012]

【Example】

(Example 1) Hereinafter, a specific example will be described in detail. Figure 1
FIG. 3 is a diagram showing a 1-bit comparator in a comparator of a cache memory which is an embodiment of the first invention. The 1 bit in the address read from the tag memory is compared with the 1 bit in the address from the CPU.

In FIG. 1, 101 is a bit line pair B11.
1, NB112, an address input line A113, and an XNOR circuit composed of a pass transistor logic circuit of an N-channel MOSFET that receives a logical inversion signal NA114 of an address input signal as input, 102 is B111, NB112, A11
3, XOR circuit composed of N-channel MOSFET pass transistor logic circuit with NA114 as input, 10
Reference numerals 3 and 104 denote NPN transistors that form a differential sense circuit, and have collectors and bases of XNOR circuits 101 and X.
It is connected to the drain output line of the OR circuit 102. 1
Reference numeral 05 denotes an N-channel MOSFET for current switch, which is turned on only when the sense enable signal EN115 is "H" and operates as a constant current source of the differential sense circuit. 10
Reference numerals 6 and 107 are load resistances of the differential sense circuit, and 116 is an output line of the output HIT.

The operation of the 1-bit comparator of FIG. 1 will be described with reference to the operation timing chart shown in FIG. In FIG. 2, potential waveforms corresponding to the signal line numbers in FIG. 1 have the same numbers.

1) When they do not match "L" is output to the address input line A113 and "H" is output to the address inversion signal input line NA114. Word line opens, bit line B111 is "H", NB112
"L" is output to. In this case, the XNOR circuit 101 configured by the pass transistor logic circuit is turned off, the XOR circuit 102 is turned on, and the base current is supplied to the NPN transistor 104. Sense enable signal EN115
Becomes "H", the differential sense circuit starts operating and N
The collector current of the PN transistor 104 flows. Since a voltage drop occurs in the load resistor 107, the potential of the output line 116 becomes "L". The output potential depends on the load resistance and MO
Although it becomes a value divided by the resistance component of the SFET and NPN transistor, if an inverter circuit in which the logical threshold value is shifted above ½ of the power supply potential is used, the change in the output line potential at the time of disagreement Can be output to the outside.

2) In case of coincidence "H" is output to the address input line A113 and "L" is output to the address inversion signal input line NA114. Word line opens, bit line B111 is "H", NB112
"L" is output to. In this case, the XNOR circuit 101 configured by the pass transistor logic circuit is turned on and the XOR circuit 102 is turned off. Sense enable signal EN115
The differential sense circuit starts its operation when the voltage goes to "H", and the current due to the discharge of the parasitic capacitance transiently flows, and the output line HIT
The potential of 116 drops slightly. However, the XOR circuit 10
Since 2 is off, the base current is not supplied to the NPN transistor 104, and there is no steady collector current path. When the initial discharge is completed, the potential of the output line HIT116 does not drop further, and the load resistance 107 raises the potential to the power supply potential VDD again.

As shown in the above embodiments, in the present invention, the XOR circuit and the XNOR circuit are realized by the pass transistor logic circuit, and the comparator is constructed by combining with the differential type sense circuit. In this way, the sense circuit and the comparator are combined,
By simultaneously executing the read and the comparison, the read / comparison time can be shortened. Also, MOSF
Since the base current of the NPN transistor is supplied via ET, the input impedance of the differential sense circuit becomes high, the potential of the "H" side bit line does not drop, and there is no risk of malfunction due to noise. Further, the base potentials of the NPN transistors 103 and 104 are clamped below the collector potential by the potential of the series MOSFET of the pass transistor logic circuit, and even if the emitter follower circuit, which requires a large area, is not used, the NP can be formed with a small area MOSFET.
An N-transistor saturation prevention circuit can be realized. As described above, according to the present invention, it is possible to easily realize a high-speed comparator such as a tag portion of a cache memory or a TLB that requires simultaneous multi-bit reading in a small area.

(Embodiment 2) FIG. 3 is a diagram showing a 1-bit comparator in a comparator of a cache memory according to a second embodiment of the first invention. The 1 bit in the address read from the tag memory is compared with the 1 bit in the address from the CPU.

In this embodiment, a P-channel MOSFET is used as the XNOR circuit 301 and XO of the pass transistor logic circuit.
This is an example of configuring the R circuit 302. Also in this case, the bit line pair B111, NB1 is also used as in the 1-bit comparator of FIG.
When the potentials of 12 and the address input line pair A113, NA114 match, the base current is not supplied to the NPN transistor 104, and only when they do not match, the base current is supplied to the NPN transistor 104. Therefore, 1 in FIG.
Operates in the same way as the bit comparator. Also, P channel M
Since the OSFET can be formed in the N-type impurity region of the collector, the NPN transistor and the P-channel MOS are formed.
Since the element isolation region between the FETs is unnecessary, it is effective in reducing the cell area. Even if the contents of the memory cell are output to the bit line pair, the voltage between the bit line pair and the collector is P
As long as the threshold voltage Vt of the channel MOSFET is not exceeded, that is, Vbc = Vgs ≧ Vt (Vb is either potential of the bit line pair, Vc is collector potential, Vgs is P
Unless the gate-source voltage of the channel MOSFET is satisfied, the P-channel MOSFET having the bit line pair as the gate input does not satisfy the operating condition and the comparator does not operate. If the bit line is precharged to VDD, this non-operation time becomes long, but in order to speed up the comparison, the precharge potential may be lowered to VDD-Vt or lower.

As shown in the above embodiments, in the present invention, the XOR circuit and the XNOR circuit are realized by the pass transistor logic circuit, and the comparator is constructed by combining with the differential type sense circuit. In this way, the sense circuit and the comparator are combined,
By simultaneously executing the read and the comparison, the read / comparison time can be shortened. Also, MOSF
Since the base current of the NPN transistor is supplied via ET, the input impedance of the differential type sense circuit is increased, there is no fear of malfunction due to noise, and the saturation prevention circuit of the bipolar transistor can be configured with a small area MOSFET. As described above, according to the present invention, the tag portion and T
A high-speed comparator such as LB can be easily realized in a small area.

(Embodiment 3) FIG. 4 shows a tag portion of a cache memory according to an embodiment of the second invention. The 24 1-bit comparator is provided, and a 24-bit comparator is configured by connecting each output line by wired OR.

In FIG. 4, reference numeral 401 is a tag memory, and when the address PA410 is decoded by the decoder 402 and the word line WL411 becomes "H", the data of the memory cell array selected by the word line is addressed to the bit line pair at the address B. It is output as [23: 0]. When the sense enable SEN412 becomes “H”, B [2
3: 0] and the address A [23: 0] 413 from the CPU
The 1-bit comparator 403 detects the match / mismatch of each bit. This 1-bit comparator 403 is the one shown in the first embodiment or the second embodiment, and has a configuration in which a sense circuit and a match / mismatch detection circuit are integrated. Also, the 24-bit comparator 404 is configured by connecting the output lines of the 1-bit comparators by wired OR. Since each 1-bit comparator detects the voltage drop of the load resistance as the output potential,
Wired or connection of each output line is possible. The potential of the output line HIT414 is lowered to "L" when the comparison result does not match even one bit, but the output line HIT414 remains "H" when all match. A precharge / equalize circuit 405 precharges and equalizes the bit line pair by the precharge enable PCEN 415 and the equalize enable EQEN 416 when the tag memory is not accessed. An NPN transistor is used in the precharge circuit in order to speed up read and bit line precharge / equalization. Again 4
06 is a write circuit for writing the data W [23: 0] 418,
It is controlled by the write enable WEN417.

Unlike the conventional example shown in FIG. 6, the present embodiment does not require a multi-input AND circuit for generating a logical product of match / mismatch determination signals for each bit, so that the amount of hardware can be reduced. is there. Further, by reducing the delay time of the AND circuit, it is possible to detect a match / mismatch at high speed.

(Embodiment 4) FIG. 5 is a second embodiment of the second invention and shows a physical address access type cache memory system. In this embodiment, the physical address read by the tag section and the physical address converted by TLB are compared by the multi-bit comparator shown in the third embodiment.

In FIG. 5, 501 is a tag memory, which is C
A word is selected by a part of bits of the logical address PA511 from PU, and the physical address B [23: 0] is output from the memory cell array to the bit line pair. 5
Reference numeral 02 denotes the associative memory (CAM) unit of the TLB. When the address of the data stored in the CAM unit and a part of bits of the PA 511 match, one of the match signal lines ML512 is "
H ”, and the physical address A [23: 0] is output from the RAM unit 503 of the TLB. Reference numeral 504 denotes the comparator shown in the third embodiment, which has two physical addresses when the sense enable SEN513 is“ H ”. A [23: 0], B [23:
0] are compared. The output line HIT 514 becomes "H" when the two physical addresses match, and "L" when they do not match. In addition, in the CAM and the tag memory, the logical address P
How many bits of A are used depends on the number of cache memory sets and the line size.

In the present embodiment, since the multi-input AND circuit for generating the logical product of the match / mismatch determination signals for each bit is unnecessary, the amount of hardware can be reduced. Furthermore, A
By reducing the delay time of the ND circuit, it is possible to detect a match / mismatch at high speed.

[0027]

As described above, 1) the exclusive OR circuit and the exclusive NOR circuit are formed by the pass transistor logic circuit, and the bipolar differential type sense circuit and the comparator are combined to realize the comparison operation. Speed up,
2) A wired OR circuit is possible to speed up multi-bit comparison operation, and an AND circuit is not required, which reduces the amount of hardware. 3) A hardware with less input impedance conversion of the sense circuit and prevention of bipolar transistor saturation. It can be realized with a wear amount, and 4) It has effects such as stable operation of the memory circuit, and is extremely useful as a comparator used in a semiconductor integrated circuit device.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a 1-bit comparator according to an embodiment of the first invention.

FIG. 2 is a timing diagram of the 1-bit comparator according to the first embodiment of the invention.

FIG. 3 is a configuration diagram of a 1-bit comparator according to an embodiment of the first invention.

FIG. 4 is a block diagram of a cache memory comparator according to an embodiment of the second invention.

FIG. 5 is a configuration diagram of a cache memory system according to an embodiment of the second invention.

FIG. 6 is a block diagram of a conventional cache memory comparator.

FIG. 7 is a configuration diagram of a conventional sense circuit.

[Explanation of symbols]

 101, 301 Exclusive NOR circuit 102, 302 Exclusive OR circuit 103, 104 NPN transistor 105 N-channel MOSFET 106, 107 Load resistance 111, 112 Bit line pair 113, 114 Address input line 115 Sense enable 116 Output line 401 Tag Memory 403 1-bit comparator 404 24-bit comparator 414 output line 501 Tag memory 502 TLB associative memory unit 503 TLB RAM unit 504 Comparator 514 output line

Claims (5)

[Claims] 1. A comparator for comparing the potentials of a first input signal line pair and a second input signal line pair consisting of non-inverted data and inverted data, wherein one of the first input signal line pair Is connected to the gate of the first MOSFET and a second MOSFET having one of the second input signal line pair connected to the gate and the source of the first MOSFET connected to the drain.
SFET, a third MOSFET having the other of the first input signal line pair connected to the gate and a drain of the first MOSFET connected to the drain, and the other of the second input signal line pair having the gate And a source of the third MOSFET is connected to the drain and a source of the second MOSFET is connected to the source of the fourth M
OSFET, a fifth MOSFET in which one of the first input signal line pair is connected to the gate, and the other of the second input signal line pair is connected to the gate and the source of the fifth MOSFET is in the drain. 6th MOSF connected to
ET, a seventh MOSFET in which the other of the first input signal line pair is connected to the gate and the drain of the fifth MOSFET is connected to the drain, and one of the second input signal line pair is the gate An MOS connected to the drain and connected to the source of the seventh MOSFET at the drain and connected to the source of the sixth MOSFET at the source
An FET, a first NPN transistor having a collector connected to the drain of the first MOSFET and a base connected to the source of the second MOSFET, and a collector connected to the drain of the fifth MOSFET and the base Is connected to the source of the sixth MOSFET and the emitter of which is connected to the emitter of the first NPN transistor, and the signal line of the activation signal is connected to the gate and the drain of the first NPN transistor. Current switching MOSFET connected to the emitter of the NPN transistor and the source thereof connected to the ground line, a first load resistor connecting between the power supply line and the collector of the first NPN transistor, and the power supply line. The second NP
A second load resistor connected between the collector of the N-transistor and an output line connected to the collector of the first NPN transistor or the collector of the second NPN transistor. vessel. 2. The first to eighth MOSFEs according to claim 1.
A comparator characterized in that T is an N-channel MOSFET. 3. The first to eighth MOSFEs according to claim 1.
A comparator characterized in that T is a P-channel MOSFET. 4. A comparator, wherein the pair of comparison input line pairs according to claim 2 or claim 3 is a bit line pair of a second memory cell. 5. An n number of arbitrary comparators according to claim 4 are provided,
The m-th bit of the second input signal line pair consisting of the n-bit bit line pair of the memory circuit, the second n-bit input signal, and the inverse logic polarity input of the second n-bit input signal A m-th (0 ≦ m ≦ n−1, m is an integer) bit line pair and a comparison signal line pair, each output line of the n comparators being short-circuited. Comparator to do.