JP3941281B2

JP3941281B2 - Semiconductor integrated circuit

Info

Publication number: JP3941281B2
Application number: JP05652399A
Authority: JP
Inventors: 昌哉炭田
Original assignee: Panasonic Corp; Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Corp; Panasonic Holdings Corp
Priority date: 1999-03-04
Filing date: 1999-03-04
Publication date: 2007-07-04
Anticipated expiration: 2019-03-04
Also published as: JP2000251479A

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体集積回路に関する。
【０００２】
【従来の技術】
マイクロプロセッサなどの計算機システムには、高速動作を行うために中央処理装置と主メモリとの間に主メモリ内のプログラムやデータの一部を格納して、高速バッファメモリとして機能するキャッシュメモリが設けられている。
【０００３】
また、最近の中央処理装置のアドレスは、仮想アドレスが用いられているために、キャッシュメモリや主メモリの実アドレスとの間でアドレスの高速変換が必要となる。このため、トランスレーションルックアサイドバッファ（以下ＴＬＢ）と呼ばれる連想機能を持ったテーブルが階層化されたテーブルと並列に設けられて高速に実アドレスを引き出している。
【０００４】
上記に述べた連想メモリは、多ビットの入力アドレスと多ビットのメモリ内の記憶データとの一致、不一致を調べ、すべてのビットが一致した記憶データが存在するとその存在を示す信号および記憶しているデータを出力する方式である。
【０００５】
このように連想メモリでは、多ビットのデータを一度に比較するので、高速に動作させるには比較回路数が多くなること、これに伴い、回路面積が増加、消費電力の増加となる。検索データと記憶データとの比較を高速に且つ低消費電力且つ回路面積の課題を解決した例が、特開平８−５２８２８５号に示されている。この発明の代表的な半導体集積回路を図９に示す。１０は、仮想アドレス内の１ビットを示している。１１は仮想アドレスデータ線である。１２はインバータで仮想アドレスデータ線１１の相補信号を発生する。１６は、比較回路を内蔵したメモリセルである。１３はワード線で仮想アドレスデータ線１１に送られたデータをメモリセル１６に記憶させる作用をする。ここで、ワード線を選択したり、駆動する回路は省略しているが、これらの回路は広く用いられている回路構成であるので、説明は省略する。１５は一致検出信号線で、Ｎ型ＭＯＳＦＥＴ１４は入力仮想アドレス１１とメモリセル１６内のデータが一致したときにＯＦＦになるように設計されている。信号線１５は入力仮想アドレスビットのすべてに並列に接続されており、仮想アドレスすべての入力データと記憶データとが一致の場合のみ信号線１５は接地端子から遮断される。活性化信号３３は差動回路４１を活性化させるための信号線である。活性化信号３３が活性化された時、Ｐ型ＭＯＳＦＥＴ２１、２９からは、データが不一致のときにＮ型ＭＯＳＦＥＴ１４に流れる電流と等しい電流が供給され、ダイオード接続されたＮ型ＭＯＳＦＥＴ２２、一致検出信号線１５、Ｎ型ＭＯＳＦＥＴ１４を経て貫通電流が流れる。Ｎ型ＭＯＳＦＥＴ２７は遮断されているので信号線１５の電位は上昇する。Ｐ型ＭＯＳＦＥＴ２９より供給された電流はダイオード接続されたＮ型ＭＯＳＦＥＴ２５、Ｎ型ＭＯＳＦＥＴ２６を経て貫通電流が流れる。参照電圧３２にはデータが１個不一致のときＭＯＳＦＥＴ１４に流れる電流と同じように電位を設定しておく。この状態で端子３０、３１の電位の変化を説明する。信号線１５のデータは不一致であると不一致の個数だけ比較回路のＭＯＳＦＥＴ１４が導通するので、最も高い電位に信号線１５がなるのは１個の比較回路のＭＯＳＦＥＴ１４のみが不一致のときである。このときには、端子３０、３１はほぼ同電位となる。このため一致検出回路４２の左右の回路に流れる電流はほぼ等しい。ここで、一致検出回路４２の負荷であるＰ型ＭＯＳＦＥＴ３２、２４の寸法の差を与えて等しい電流が流れたときは一致検出回路４２の出力３４が高電位になるように設計する。すなわち、不一致の場合は、ＨＩＧＨになる。
【０００６】
【発明が解決しようとする課題】
従来の技術で述べた構成では、比較器において、高速化と低消費電力化を両立する為、活性化信号に短パルスを生成させ、貫通電流を少なくしているが、活性化信号が活性化されている間、常に電流が電源からＰチャンネルトランジスタ２１からＮチャンネルトランジスタ１４を経由し接地へ流れるパスと電源からＰチャンネルトランジスタ２９からＮチャンネルトランジスタ２５を経由し接地へ流れるパスがあり、無駄な貫通電流が流れるという第１の課題があった。また、活性化信号は短パルスの為、出力データを活性化信号が不活性になっても更に保持するには、別にラッチ回路を付加させなければならないという第２の課題があった。また、プロセスばらつきによるリファレンス電流を構成するトランジスタ２４、２５、２６、２７の電流量のばらつき変動、特にＭＯＳＦＥＴ２７とＭＯＳＦＥＴ１４の物理的配置が離れていることによるトランジスタを形成する際の注入量や露光時のパターン形成のずれが大きくなりＭＯＳＦＥＴ２７とＭＯＳＦＥＴ１４の電流量が等しくならず半導体集積回路の不良が多くなるという第３の課題があった。また、信号線３０、３１の電位はＭＯＳＦＥＴ２３とＭＯＳＦＥＴ２７のゲートを介してＭＯＳＦＥＴ２４のゲート、ドレインに伝達し増幅するので、どうしても１段ゲートを介さなければならず、これ以上の高速化は望めないという第４の課題があった。
【０００７】
【課題を解決するための手段】
本発明は、多ビットのデータ信号を入力する入力信号線とデータを記憶するメモリセルと入力された多ビットの前記データ信号と記憶された前記データとを比較し、一致の時、導通、不一致の時、非導通となり、比較する入力信号の数に等しい個数の第１のＮ型電界効果型トランジスタのソース同士が接続され、前記第１のＮ型電界効果型トランジスタのソースに所定の電位が供給され、かつ前記第１のＮ型電界効果型トランジスタのドレイン同士が接続され、前記第１のＮ型電界効果型トランジスタのドレイン同士が第２のＮ型電界効果型トランジスタのソースに接続され、前記第２のＮ型電界効果型トランジスタのドレインは、第１のＰ型電界効果型トランジスタのドレインと第２のＰ型電界効果型トランジスタのドレインに接続され、前記第１のＰ型電界効果型トランジスタと前記第２のＰ型電界効果型トランジスタのソース同士が接続されかつ所定の電位に固定され、前記第１のＮ型電界効果型トランジスタの群がすべて導通となった電流量よりも少なく且つ１つのみ不一致となった電流量よりも多い電流源に第３のＮ型電界効果型トランジスタのソースが接続され、前記第３のＮ型電界効果型トランジスタのドレインは、第３のＰ型電界効果型トランジスタのドレインと第４のＰ型電界効果型トランジスタのドレインに接続され、前記第３のＰ型電界効果型トランジスタと前記第４のＰ型電界効果型トランジスタのソース同士が接続されかつ所定の電位に固定され、前記第２のＰ型電界効果型トランジスタのゲートが前記第４のＰ型電界効果型トランジスタのソースに接続され、前記第４のＰ型電界効果型トランジスタのゲートが前記第２のＰ型電界効果型トランジスタのソースに接続され、前記第１のＮ型電界効果型トランジスタと前記第２のＮ型電界効果型トランジスタと前記第１のＰ型電界効果型トランジスタと前記第３のＰ型電界効果型トランジスタのゲートが活性化信号線に接続された構成をとることにより、活性化信号が活性化されると第１から第４までのＰ型電界効果型トランジスタのドレインが所定の固定された電圧からトランジスタの閾値まで下がるまでは、貫通電流が流れず、前記第１のＰ型電界効果型トランジスタと前記第３のＰ型電界効果型トランジスタのドレインの電位の差を増幅することより、前記データ信号と前記データの一致、不一致を検出することができるので第１の課題である無駄な貫通電流が流れず、低消費電力化が可能となる。
【０００８】
また、多ビットのデータ信号を入力する入力信号線とデータを記憶するメモリセルと入力された多ビットの前記データ信号と記憶された前記データとを比較し、一致の時、導通、不一致の時、非導通となり、比較する入力信号の数に等しい個数の第１のＮ型電界効果型トランジスタのソース同士が接続され、前記第１のＮ型電界効果型トランジスタのソースに所定の電位が供給され、かつ前記第１の電界効果型トランジスタのドレイン同士が接続され、前記第１の電界効果型トランジスタのドレイン同士が第２のＮ型電界効果型トランジスタのソースに接続され、前記第２のＮ型電界効果型トランジスタのドレインは、第１のＰ型電界効果型トランジスタのドレインと第２のＰ型電界効果型トランジスタのドレインに接続され、前記第１のＰ型電界効果型トランジスタと前記第２のＰ型電界効果型トランジスタのソース同士が接続されかつ所定の電位に固定され、前記第１のＮ型電界効果型トランジスタの群がすべて導通となった電流量よりも少なく且つ１つのみ不一致となった電流量よりも多い電流源に第３のＮ型電界効果型トランジスタのソースが接続され、前記第３のＮ型電界効果型トランジスタのドレインは、第３のＰ型電界効果型トランジスタのドレインと第４のＰ型電界効果型トランジスタのドレインに接続され、前記第３のＰ型電界効果型トランジスタと前記第４のＰ型電界効果型トランジスタのソース同士が接続されかつ所定の電位に固定され、前記第２のＰ型電界効果型トランジスタのゲートが前記第４のＰ型電界効果型トランジスタのソースに接続され、前記第４のＰ型電界効果型トランジスタのゲートが前記第２のＰ型電界効果型トランジスタのソースに接続され、前記第２のＮ型電界効果型トランジスタと前記第３のＮ型電界効果型トランジスタのゲートが活性化信号に接続され、前記第１のＰ型電界効果型トランジスタと前記第３のＰ型電界効果型トランジスタのゲートが保持信号線に接続された構成をとることにより、前記活性化信号保持信号が活性化された時、前記第１のＰ型電界効果型トランジスタと前記第３のＰ型電界効果型トランジスタのドレインの電位の差を増幅することより、前記データ信号と前記データの一致、不一致を検出し、前記活性化信号のみを不活性にすることで前記検出結果を保持することにより、保持信号を活性化信号よりも活性化期間を長く取る信号にすれば、その期間は貫通電流が流れることなく検出出力データは保持できるので、保持回路をわざわざ次段に設ける必要がなくなり第２の課題であるラッチ回路が不必要となる。
【０００９】
また、多ビットのデータ信号を入力する入力信号線とデータを記憶するメモリセルと入力された多ビットの前記データ信号と記憶された前記データとを比較し、一致の時、導通、不一致の時、非導通となり、比較する入力信号の数に等しい個数の第１のＮ型電界効果型トランジスタのソース同士が接続され、前記第１のＮ型電界効果型トランジスタのソースに所定の電位が供給され、かつ第１のＮ型電界効果型トランジスタのドレイン同士が接続され、前記第１のＮ型電界効果型トランジスタのドレイン同士が第２のＮ型電界効果型トランジスタのソースに接続され、前記第２のＮ型電界効果型トランジスタのドレインは、第１のＰ型電界効果型トランジスタのドレインと第２のＰ型電界効果型トランジスタのドレインに接続され、第１のＰ型電界効果型トランジスタと第２のＰ型電界効果型トランジスタのソース同士が接続されかつ所定の電位に固定され、導通時前記第１のＮ型電界効果型トランジスタと同じ電流量が流れ且つ前記ビット数より１つ少ない数で且つ常に導通している第３のＮ型電界効果型トランジスタのソースと、導通時前記第１のＮ型電界効果型トランジスタより少ない電流量が流れ且つ常に導通している１つの第４の電界効果型トランジスタのソース同士が接続され且つ第１のＮ型電界効果型トランジスタのソースと同電位が供給され、前記第３のＮ型電界効果型トランジスタのドレインと前記第４の電界効果型トランジスタのドレインが接続され、且つ第５のＮ型電界効果型トランジスタのソースが接続され、前記第５のＮ型電界効果型トランジスタのドレインは、第３のＰ型電界効果型トランジスタのドレインと第４のＰ型電界効果型トランジスタのドレインに接続され、前記第３のＰ型電界効果型トランジスタと前記第４のＰ型電界効果型トランジスタのソース同士が接続されかつ所定の電位に固定され、前記第２のＰ型電界効果型トランジスタのゲートが前記第４のＰ型電界効果型トランジスタのソースに接続され、前記第４のＰ型電界効果型トランジスタのゲートが前記第２のＰ型電界効果型トランジスタのソースに接続され、前記第２のＮ型電界効果型トランジスタと前記第５のＮ型電界効果型トランジスタと前記第１のＰ型電界効果型トランジスタと前記第３のＰ型電界効果型トランジスタのゲートが活性化信号線に接続された構成をとることにより、前記活性化信号が活性化された時、前記第１のＰ型電界効果型トランジスタと前記第３のＰ型電界効果型トランジスタのドレインの電位の差を増幅することより、前記データ信号と前記データの一致、不一致を検出でき、比較されるビットの第１のＮ型電界効果型トランジスタと比較する第３のＮ型電界効果型トランジスタ及び第４のＮ型電界効果型トランジスタを隣接配置することにより、第３の課題であるプロセスばらつき変動による電流量の変動を押えることができ、不良を少なくすることが可能となる。
【００１０】
また、多ビットのデータ信号を入力する入力信号線とデータを記憶するメモリセルと入力された多ビットの前記データ信号と記憶された前記データとを比較し、一致の時、導通、不一致の時、非導通となり、比較する入力信号の数に等しい個数の第１のＮ型電界効果型トランジスタのソース同士が接続され、前記第１のＮ型電界効果型トランジスタのソースに所定の電位が供給され、かつ前記第１の電界効果型トランジスタのドレイン同士が接続され、前記第１の電界効果型トランジスタのドレイン同士が第２のＮ型電界効果型トランジスタのソースに接続され、前記第２のＮ型電界効果型トランジスタのドレインは、第１のＰ型電界効果型トランジスタのドレインと第２のＰ型電界効果型トランジスタのドレインと第３のＰ型電界効果型トランジスタのドレインに接続され、前記第１のＰ型電界効果型トランジスタと前記第２のＰ型電界効果型トランジスタと前記第３のＰ型電界効果型トランジスタのソース同士が接続されかつ所定の電位に固定され、前記第１のＮ型電界効果型トランジスタの群がすべて導通となった電流量よりも少なく且つ１つのみ不一致となった電流量よりも多い電流源に第３のＮ型電界効果型トランジスタのソースが接続され、前記第３のＮ型電界効果型トランジスタのドレインは、第４のＰ型電界効果型トランジスタのドレインと第５のＰ型電界効果型トランジスタと第６のＰ型電界効果型トランジスタのドレインに接続され、前記第４のＰ型電界効果型トランジスタと前記第５のＰ型電界効果型トランジスタと前記第６のＰ型電界効果型トランジスタのソース同士が接続されかつ所定の電位に固定され、前記第２のＰ型電界効果型トランジスタのゲートが前記第５のＰ型電界効果型トランジスタのソースに接続され、前記第５のＰ型電界効果型トランジスタのゲートが前記第２のＰ型電界効果型トランジスタのソースに接続され、前記第２のＮ型電界効果型トランジスタと前記第３のＮ型電界効果型トランジスタのゲートが第１の活性化信号に接続され、前記第１のＰ型電界効果型トランジスタと前記第４のＰ型電界効果型トランジスタのゲートが保持信号線に接続され、前記第３のＰ型電界効果型トランジスタと前記第６のＰ型電界効果型トランジスタのゲートが第２の活性化信号線に接続された構成をとることにより、前記第１の活性化信号、前記第２の活性化信号、前記保持信号が活性化された時、前記第１のＰ型電界効果型トランジスタと前記第４のＰ型電界効果型トランジスタのドレインの電位の差を前記第３のＰ型電界効果型トランジスタと第６のＰ型電界効果型トランジスタによって強制的に広げ、前記第２のＰ型電界効果型トランジスタもしくは、前記第４のＰ型電界効果型トランジスタのゲート及びドレインに直接伝達するため前記データ信号と前記データの一致、不一致が第４の課題であるゲート１段を介さずに高速に検出可能となる。
【００１１】
【発明の実施の形態】
（実施形態１）
図１は本発明の請求項２に係る発明の半導体集積回路の一例であり１ウェイのセットアソシアティブ方式（すなわちダイレクトマップ方式）のＴＬＢの構成を示している。１０は、仮想アドレス内の１ビットを示している。１１は仮想アドレスデータ線である。１２はインバータで１１の相補信号を発生する。１６は、比較回路を内蔵したメモリセルである。１３はワード線で１１に送られたデータをメモリセル１６に記憶させる作用をする。ここで、ワード線を選択したり、駆動する回路は省略しているが、これらの回路は広く用いられている回路構成であり、例えば、アドレスの下位ビットをデコードしバッファで駆動するような回路であり、詳細説明は省略する。１５は一致検出信号線で、Ｎ型ＭＯＳＦＥＴ１４は入力仮想アドレスとメモリセル内のデータが一致したときにＯＮになるように設計されている。信号線１５は入力仮想アドレスのすべてに並列に接続されており、仮想アドレスすべての入力データと記憶データとが不一致の場合のみ信号線１５は接地端子から遮断される。活性化信号３５は一致検出回路１を活性化させるための信号線である。５は、仮想アドレスデータが全ビット一致のときに信号線１５に流れる電流よりも小さく、仮想アドレスデータが１ビットのみ不一致のときに信号線１５に流れる電流よりも大きい電流を駆動する電流源である。Ｎ型ＭＯＳＦＥＴ２のソースは、信号線１５に接続されており、Ｎ型ＭＯＳＦＥＴ３のソースは、電流源５に接続されており、Ｎ型ＭＯＳＦＥＴ２のドレインは、比較回路出力相補信号線４に接続されており、Ｎ型ＭＯＳＦＥＴ３のドレインは、比較回路出力信号線３６に接続されており、活性化信号３５が不活性の時、Ｎ型ＭＯＳＦＥＴ２と３はそれぞれのゲートが活性化信号３５に接続されているのでＯＦＦしている。Ｐ型ＭＯＳＦＥＴ６、７、８、９のソースは電源に並列に接続されており、Ｐ型ＭＯＳＦＥＴ６、７のドレインは比較回路出力相補信号線４に接続されている。Ｐ型ＭＯＳＦＥＴ８、９のドレインは比較回路出力信号線３６に接続されている。
【００１２】
Ｐ型ＭＯＳＦＥＴ６、８は活性化信号線３５にゲートが接続されているので、不活性時ＯＮしており、比較回路出力信号線３６と比較回路出力相補信号線４は電源と同電位に固定されている。また、Ｐ型ＭＯＳＦＥＴ７のゲートは、比較回路出力信号線３６に接続され、Ｐ型ＭＯＳＦＥＴ９のゲートは、比較回路出力信号線３６に接続されているので、活性化信号線３５が不活性の時、Ｐ型ＭＯＳＦＥＴ７、９はＯＦＦしている。入力仮想アドレス１１とメモリセル１６内のデータが一致か否か各ビットのＮ型ＭＯＳＦＥＴ１４によって決定され、その後、活性化信号３５が活性化され、一致検出回路１によってすべての仮想アドレス１１とメモリセル１６内のデータが一致したか否かを判定し、比較回路出力信号３６に結果が出力される。
【００１３】
図２は、すべての入力仮想アドレスとメモリセル内のデータが一致した後、活性化信号３５が活性化された場合のタイミングチャートである。横軸は過渡時間であり、縦軸は、電圧であり、各々の信号線の遷移を示す。Ｐ型ＭＯＳＦＥＴ６、７、８、９のドレインが電源電位から閾値分だけ下がるまで、Ｐ型ＭＯＳＦＥＴ７、９はＯＦＦしており、比較回路出力相補信号線４は、各メモリセル１６内のＮ型ＭＯＳＦＥＴを経由して、接地へ電流が流れる。同様に比較回路出力信号線３６は、電流源を経由して接地へ電流が流れる。しかし、各々の電流量は異なり、比較回路出力相補信号線４の電位の方が早く電源電位からＰ型ＭＯＳＦＥＴの閾値分だけ下がる。この時間をＴ１とする。時間Ｔ１から、Ｐ型ＭＯＳＦＥＴ９がＯＮし、比較回路出力信号線３６は電源から電流が流れ、Ｐ型ＭＯＳＦＥＴ９から流れる電流量とＮ型ＭＯＳＦＥＴ３から電流源５を経由して接地へ流れる電流量の差に比例して電位の減少は妨げられる。しばらくして時間Ｔ２で、比較回路出力相補信号線４の電荷は、電源からの供給電流がないのでＮ型ＭＯＳＦＥＴ２からＮ型ＭＯＳＦＥＴ１４を経由し接地へ流れ比較回路出力相補信号線４の電位は、接地電位と等しくなり、またＰ型ＭＯＳＦＥＴ９のゲート電位は電源と接地の電位差となるため、Ｐ型ＭＯＳＦＥＴ９は飽和モードとなり非常に大きな電流が比較回路出力信号線３６に流れ、比較回路出力信号線３６の電位は更に急速に上昇する。上記説明のようにすべて入力アドレスとメモリセル内のデータが一致した場合、比較回路出力信号線３６はＨＩＧＨとなる。また、１ビットでも入力仮想アドレスとメモリセル内のデータが不一致になる場合は、比較回路出力相補信号線４と比較回路出力信号線の振舞いは、逆となり、比較回路出力信号線はＬＯＷとなる。
【００１４】
以上のように、Ｐ型ＭＯＳＦＥＴ６のドレインが電源電位から閾値まで下がるまで貫通電流が流れることなく、Ｐ型ＭＯＳＦＥＴ６のドレインの電位とＰ型ＭＯＳＦＥＴ８のドレインの電位との差がＰ型ＭＯＳＦＥＴ９により増幅され高速に比較検出ができる。
【００１５】
なお、本半導体集積回路は、Ｐ型Ｎ型ＭＯＳＦＥＴ及び電位、出力信号を反対にしてもほぼ同様な動作となることはいうまでもない。更に、仮想アドレスデータ信号がすべて一致の時、信号線１５が非導通の構成をとれば、電流源５は、１ビットのみが一致した場合より小さな電流が流れる電流源で実現できる。この時仮想アドレスデータ信号がすべて一致の時、比較回路出力信号線３６はＬＯＷとなる。仮想アドレスデータ信号がすべて一致の時、一致検出回路１からＨＩＧＨの出力を得たい場合は、比較回路出力相補信号線４を出力とすればよい。
【００１６】
（実施形態２）
図３は本発明の請求項３に係る発明の半導体集積回路の一例でありＴＬＢの構成を示している。図３は、図１とほぼ同様であるが、Ｐ型ＭＯＳＦＥＴ６、７のゲートが保持信号３７に接続されているところが違う。
【００１７】
入力仮想アドレス１１とメモリセル１６内のデータが一致か否か各ビットのＮ型ＭＯＳＦＥＴ１４によって決定され、その後、活性化信号３５と保持信号３７が活性化され、一致検出回路１によってすべての仮想アドレス１１とメモリセル１６内のデータが一致したか否かを判定し、比較回路出力信号３６に結果が出力され、活性化信号３５のみ不活性にすることにより比較回路出力信号３６に結果が保持される。
【００１８】
すべて入力アドレスとメモリセル内のデータが一致し、活性化信号３５と保持信号３７が活性化された場合のタイミングチャートを図４に示す。活性化信号３５と保持信号３７はほぼ同時刻に活性化される。その後、比較回路出力信号３６がＨＩＧＨになるまでは、図１と図２を用いて実施形態１で説明したのと同じ振舞をする。活性化信号３５が不活性になった時間Ｔ３で、Ｎ型ＭＯＳＦＥＴ２、３は、ＯＦＦし、比較回路出力信号３６はＨＩＧＨのままになり、出力データは、ラッチ回路を付加させることなく保持される。
【００１９】
以上のように活性化信号に対して保持信号を長く活性化することにより、出力データが保持される。
【００２０】
（実施形態３）
図５は、本発明の請求項４に係る発明の半導体集積回路の一例である。図５は、図１とほぼ同様であるが、図１の電流源５の代わりに、メモリセル１９内にあるＮ型ＭＯＳＦＥＴ１７のゲートがメモリセル１９内のデータが仮想アドレス１１と一致された時、Ｎ型ＭＯＳＦＥＴ１４のゲート電位１８と同じ電位に固定され、ソースが接地され、ドレインが他のビットの同Ｎ型ＭＯＳＦＥＴ１７のドレインに並列に接続されており、且つＮ型ＭＯＳＦＥＴ３のソースに接続されている。各ビットで構成されるＮ型ＭＯＳＦＥＴ１７の内、１ビットだけは、Ｎ型ＭＯＳＦＥＴ１４の形状よりも電流が少ないように作られた形状であるが、他のビットについては、Ｎ型ＭＯＳＦＥＴ１４と同形状である。電流が少ないように作られたＮ型ＭＯＳＦＥＴ１７とＮ型ＭＯＳＦＥＴ１４の形状を上からみた物理的配置図を図６に示す。図６のようにＮ型ＭＯＳＦＥＴ１４、１７のソースを共通にし、ドレイン形状も同様にしＮ型ＭＯＳＦＥＴ１４のゲート長よりも１７のゲート長を大きくすることによって電流は少なくなる。
【００２１】
以上のように、Ｎ型ＭＯＳＦＥＴ１４、１７を隣接し、ドレイン、ソース、ゲート形状を同形状にすることにより、プロセス製造によるトランジスタ形成時のイオン注入量の場所による局所依存性を改善できほぼ同等性能をもつＮ型ＭＯＳＦＥＴ１４、１７が生成できプロセスばらつきを最小限に押えることが可能となる。
【００２２】
（実施形態４）
図７は本発明の請求項５に係る発明の半導体集積回路の一例でありＴＬＢの構成を示している。図７は、図３とほぼ同様であるが、Ｐ型ＭＯＳＦＥＴ３８のドレインが比較回路出力相補信号４に接続され、Ｐ型ＭＯＳＦＥＴ３８のソースが電源に接続され、Ｐ型ＭＯＳＦＥＴ３９のドレインが比較回路出力信号３６に接続され、Ｐ型ＭＯＳＦＥＴ３９のソースが電源に接続され、Ｐ型ＭＯＳＦＥＴ３８、３９のゲートが第２の活性化信号４０に接続されているところが違う。
【００２３】
入力仮想アドレス１１とメモリセル１６内のデータが一致か否か各ビットのＮ型ＭＯＳＦＥＴ１４によって決定され、その後、活性化信号３５と保持信号３７が活性化され、更に第２の活性化信号４０が活性化され、一致検出回路１によってすべての仮想アドレス１１とメモリセル１６内のデータが一致したか否かを判定し、比較回路出力信号３６に結果が出力され、活性化信号３５、第２の活性化信号４０のみ不活性にすることにより比較回路出力信号３６に結果が保持される。
【００２４】
すべて入力アドレスとメモリセル内のデータが一致し、活性化信号３５と第２の活性化信号４０と保持信号３７が活性化された場合のタイミングチャートを図８に示す。活性化信号３５と保持信号３７はほぼ同時刻に活性化される。Ｐ型ＭＯＳＦＥＴ６、７、８、９のドレインが電源電位から閾値分だけ下がるまで、Ｐ型ＭＯＳＦＥＴ６、７、８、９はＯＦＦしており、比較回路出力相補信号線４は、各メモリセル１６内のＮ型ＭＯＳＦＥＴを経由して、接地へ電流が流れる。同様に比較回路出力信号線３６は、電流源を経由して接地へ電流が流れる。しかし、各々の電流量は異なり、比較回路出力相補信号線４の電位の方が早く電源電位からＰ型ＭＯＳＦＥＴの閾値分だけ下がる。この時間をＴ４とする。このＰ型ＭＯＳＦＥＴの閾値分だけ下がる時刻Ｔ４とほぼ同時刻に第２の活性化信号を不活性化させる。ここでは、第２の活性化信号４０はＰ型ＭＯＳＦＥＴのゲートに接続しているのでＬＯＷ期間が活性化期間である。すると、Ｐ型ＭＯＳＦＥＴ３８、Ｐ型ＭＯＳＦＥＴ３９、Ｐ型ＭＯＳＦＥＴ９がＯＮし、比較回路出力信号線３６は電源から電流が流れ、Ｐ型ＭＯＳＦＥＴ３９とＰ型ＭＯＳＦＥＴ９から流れる電流量の総和とＮ型ＭＯＳＦＥＴ３から電流源５を経由して接地へ流れる電流量の差に比例して比較回路出力信号線３６の電位の減少は妨げられる。また、比較回路出力相補信号線４の電位は、Ｐ型ＭＯＳＦＥＴ３８の供給電流と各メモリセル１６内のＮ型ＭＯＳＦＥＴを経由して、接地へ流れる電流量の差に比例して電位の減少は妨げられる。これら比較回路出力信号線３６の電位と比較回路出力相補信号線４の電位の差は、Ｐ型ＭＯＳＦＥＴ３８、Ｐ型ＭＯＳＦＥＴ３９のゲートとソース間の電圧差が常に一定であるため常に一定の電流が流れる為、すなわち定電流源を追加することにより、比較回路出力信号線３６と比較回路出力相補信号線４に電荷が急速に溜まるので、実施形態１で説明した時間よりも急速に広がり、Ｐ型ＭＯＳＦＥＴ９は実施形態１で説明した時間よりも早く飽和モードに遷移し更に大きな電流が比較回路出力信号線３６に流れ、比較回路出力信号線３６の電位は更に急速に上昇する。活性化信号３５が不活性となり、第２の活性化信号４０が活性になった場合、Ｎ型ＭＯＳＦＥＴ２、３は、ＯＦＦし、比較回路出力信号３６はＨＩＧＨのままになり、出力データは、ラッチ回路を付加させることなく保持される。
【００２５】
第２の活性化信号を活性化させることにより、Ｐ型ＭＯＳＦＥＴ３８、Ｐ型ＭＯＳＦＥＴ３９から電流を強制的に増強させることよりＰ型ＭＯＳＦＥＴ９のゲート及びドレインに直接伝達されＰ型ＭＯＳＦＥＴ６のドレインの電位とＰ型ＭＯＳＦＥＴ８のドレインの電位との差が、高速に比較検出ができ、また、第一の活性化信号に対して保持信号を長く活性化することにより、出力データが保持される。
【００２６】
【発明の効果】
以上のように本発明は、多ビットのデータ信号を入力する入力信号線とデータを記憶するメモリセルと入力された多ビットの前記データ信号と記憶された前記データとを比較し、一致の時、導通、不一致の時、非導通となり、比較する入力信号の数に等しい個数の第１のＮ型電界効果型トランジスタのソース同士が接続され、前記第１のＮ型電界効果型トランジスタのソースに所定の電位が供給され、かつ前記第１のＮ型電界効果型トランジスタのドレイン同士が接続され、前記第１のＮ型電界効果型トランジスタのドレイン同士が第２のＮ型電界効果型トランジスタのソースに接続され、前記第２のＮ型電界効果型トランジスタのドレインは、第１のＰ型電界効果型トランジスタのドレインと第２のＰ型電界効果型トランジスタのドレインに接続され、前記第１のＰ型電界効果型トランジスタと前記第２のＰ型電界効果型トランジスタのソース同士が接続されかつ所定の電位に固定され、前記第１のＮ型電界効果型トランジスタの群がすべて導通となった電流量よりも少なく且つ１つのみ不一致となった電流量よりも多い電流源に第３のＮ型電界効果型トランジスタのソースが接続され、前記第３のＮ型電界効果型トランジスタのドレインは、第３のＰ型電界効果型トランジスタのドレインと第４のＰ型電界効果型トランジスタのドレインに接続され、前記第３のＰ型電界効果型トランジスタと前記第４のＰ型電界効果型トランジスタのソース同士が接続されかつ所定の電位に固定され、前記第２のＰ型電界効果型トランジスタのゲートが前記第４のＰ型電界効果型トランジスタのソースに接続され、前記第４のＰ型電界効果型トランジスタのゲートが前記第２のＰ型電界効果型トランジスタのソースに接続され、前記第１のＮ型電界効果型トランジスタと前記第２のＮ型電界効果型トランジスタと前記第１のＰ型電界効果型トランジスタと前記第３のＰ型電界効果型トランジスタのゲートが活性化信号線に接続された構成をとることにより、活性化信号が活性化されると第１から第４までのＰ型電界効果型トランジスタのドレインが所定の固定された電圧からトランジスタの閾値まで下がるまでは、貫通電流が流れず、前記第１のＰ型電界効果型トランジスタと前記第３のＰ型電界効果型トランジスタのドレインの電位の差を増幅することより、前記データ信号と前記データの一致、不一致を検出することができるので無駄な貫通電流が流れず、低消費電力化ができる。
【００２７】
また、多ビットのデータ信号を入力する入力信号線とデータを記憶するメモリセルと入力された多ビットの前記データ信号と記憶された前記データとを比較し、一致の時、導通、不一致の時、非導通となり、比較する入力信号の数に等しい個数の第１のＮ型電界効果型トランジスタのソース同士が接続され、前記第１のＮ型電界効果型トランジスタのソースに所定の電位が供給され、かつ前記第１の電界効果型トランジスタのドレイン同士が接続され、前記第１の電界効果型トランジスタのドレイン同士が第２のＮ型電界効果型トランジスタのソースに接続され、前記第２のＮ型電界効果型トランジスタのドレインは、第１のＰ型電界効果型トランジスタのドレインと第２のＰ型電界効果型トランジスタのドレインに接続され、前記第１のＰ型電界効果型トランジスタと前記第２のＰ型電界効果型トランジスタのソース同士が接続されかつ所定の電位に固定され、前記第１のＮ型電界効果型トランジスタの群がすべて導通となった電流量よりも少なく且つ１つのみ不一致となった電流量よりも多い電流源に第３のＮ型電界効果型トランジスタのソースが接続され、前記第３のＮ型電界効果型トランジスタのドレインは、第３のＰ型電界効果型トランジスタのドレインと第４のＰ型電界効果型トランジスタのドレインに接続され、前記第３のＰ型電界効果型トランジスタと前記第４のＰ型電界効果型トランジスタのソース同士が接続されかつ所定の電位に固定され、前記第２のＰ型電界効果型トランジスタのゲートが前記第４のＰ型電界効果型トランジスタのソースに接続され、前記第４のＰ型電界効果型トランジスタのゲートが前記第２のＰ型電界効果型トランジスタのソースに接続され、前記第２のＮ型電界効果型トランジスタと前記第３のＮ型電界効果型トランジスタのゲートが活性化信号に接続され、前記第１のＰ型電界効果型トランジスタと前記第３のＰ型電界効果型トランジスタのゲートが保持信号線に接続された構成をとることにより、前記活性化信号保持信号が活性化された時、前記第１のＰ型電界効果型トランジスタと前記第３のＰ型電界効果型トランジスタのドレインの電位の差を増幅することより、前記データ信号と前記データの一致、不一致を検出し、前記活性化信号のみを不活性にすることで前記検出結果を保持することにより、保持信号を活性化信号よりも活性化期間を長く取る信号にすれば、その期間は貫通電流が流れることなく検出出力データは保持できるので、保持回路をわざわざ次段に設ける必要がなくなり、低面積化ができる。
【００２８】
また、多ビットのデータ信号を入力する入力信号線とデータを記憶するメモリセルと入力された多ビットの前記データ信号と記憶された前記データとを比較し、一致の時、導通、不一致の時、非導通となり、比較する入力信号の数に等しい個数の第１のＮ型電界効果型トランジスタのソース同士が接続され、前記第１のＮ型電界効果型トランジスタのソースに所定の電位が供給され、かつ第１のＮ型電界効果型トランジスタのドレイン同士が接続され、前記第１のＮ型電界効果型トランジスタのドレイン同士が第２のＮ型電界効果型トランジスタのソースに接続され、前記第２のＮ型電界効果型トランジスタのドレインは、第１のＰ型電界効果型トランジスタのドレインと第２のＰ型電界効果型トランジスタのドレインに接続され、第１のＰ型電界効果型トランジスタと第２のＰ型電界効果型トランジスタのソース同士が接続されかつ所定の電位に固定され、導通時前記第１のＮ型電界効果型トランジスタと同じ電流量が流れ且つ前記ビット数より１つ少ない数で且つ常に導通している第３のＮ型電界効果型トランジスタのソースと、導通時前記第１のＮ型電界効果型トランジスタより少ない電流量が流れ且つ常に導通している１つの第４の電界効果型トランジスタのソース同士が接続され且つ第１のＮ型電界効果型トランジスタのソースと同電位が供給され、前記第３のＮ型電界効果型トランジスタのドレインと前記第４の電界効果型トランジスタのドレインが接続され、且つ第５のＮ型電界効果型トランジスタのソースが接続され、前記第５のＮ型電界効果型トランジスタのドレインは、第３のＰ型電界効果型トランジスタのドレインと第４のＰ型電界効果型トランジスタのドレインに接続され、前記第３のＰ型電界効果型トランジスタと前記第４のＰ型電界効果型トランジスタのソース同士が接続されかつ所定の電位に固定され、前記第２のＰ型電界効果型トランジスタのゲートが前記第４のＰ型電界効果型トランジスタのソースに接続され、前記第４のＰ型電界効果型トランジスタのゲートが前記第２のＰ型電界効果型トランジスタのソースに接続され、前記第２のＮ型電界効果型トランジスタと前記第５のＮ型電界効果型トランジスタと前記第１のＰ型電界効果型トランジスタと前記第３のＰ型電界効果型トランジスタのゲートが活性化信号線に接続された構成をとることにより、前記活性化信号が活性化された時、前記第１のＰ型電界効果型トランジスタと前記第３のＰ型電界効果型トランジスタのドレインの電位の差を増幅することより、前記データ信号と前記データの一致、不一致を検出でき、比較されるビットの第１のＮ型電界効果型トランジスタと比較する第３のＮ型電界効果型トランジスタ及び第４のＮ型電界効果型トランジスタを隣接配置することにより、プロセスばらつき変動による電流量の変動を押えることができ、不良を少なくすることができる。
【００２９】
また、多ビットのデータ信号を入力する入力信号線とデータを記憶するメモリセルと入力された多ビットの前記データ信号と記憶された前記データとを比較し、一致の時、導通、不一致の時、非導通となり、比較する入力信号の数に等しい個数の第１のＮ型電界効果型トランジスタのソース同士が接続され、前記第１のＮ型電界効果型トランジスタのソースに所定の電位が供給され、かつ前記第１の電界効果型トランジスタのドレイン同士が接続され、前記第１の電界効果型トランジスタのドレイン同士が第２のＮ型電界効果型トランジスタのソースに接続され、前記第２のＮ型電界効果型トランジスタのドレインは、第１のＰ型電界効果型トランジスタのドレインと第２のＰ型電界効果型トランジスタのドレインと第３のＰ型電界効果型トランジスタのドレインに接続され、前記第１のＰ型電界効果型トランジスタと前記第２のＰ型電界効果型トランジスタと前記第３のＰ型電界効果型トランジスタのソース同士が接続されかつ所定の電位に固定され、前記第１のＮ型電界効果型トランジスタの群がすべて導通となった電流量よりも少なく且つ１つのみ不一致となった電流量よりも多い電流源に第３のＮ型電界効果型トランジスタのソースが接続され、前記第３のＮ型電界効果型トランジスタのドレインは、第４のＰ型電界効果型トランジスタのドレインと第５のＰ型電界効果型トランジスタと第６のＰ型電界効果型トランジスタのドレインに接続され、前記第４のＰ型電界効果型トランジスタと前記第５のＰ型電界効果型トランジスタと前記第６のＰ型電界効果型トランジスタのソース同士が接続されかつ所定の電位に固定され、前記第２のＰ型電界効果型トランジスタのゲートが前記第５のＰ型電界効果型トランジスタのソースに接続され、前記第５のＰ型電界効果型トランジスタのゲートが前記第２のＰ型電界効果型トランジスタのソースに接続され、前記第２のＮ型電界効果型トランジスタと前記第３のＮ型電界効果型トランジスタのゲートが第１の活性化信号に接続され、前記第１のＰ型電界効果型トランジスタと前記第４のＰ型電界効果型トランジスタのゲートが保持信号線に接続され、前記第３のＰ型電界効果型トランジスタと前記第６のＰ型電界効果型トランジスタのゲートが第２の活性化信号線に接続された構成をすることにより、前記第１の活性化信号、前記第２の活性化信号、前記保持信号が活性化された時、前記第１のＰ型電界効果型トランジスタと前記第４のＰ型電界効果型トランジスタのドレインの電位の差を前記第３のＰ型電界効果型トランジスタと前記第６のＰ型電界効果型トランジスタによって強制的に広げ、前記第２のＰ型電界効果型トランジスタもしくは前記第４のＰ型電界効果型トランジスタのドレイン及びゲートに直接伝達することより、前記データ信号と前記データの一致、不一致が高速に検出できる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態に係る半導体集積回路の構成図
【図２】本発明の第１の実施形態に係るタイミングチャート
【図３】本発明の第２の実施形態に係る半導体集積回路の構成図
【図４】本発明の第２の実施形態に係るタイミングチャート
【図５】本発明の第３の実施形態に係る半導体集積回路の構成図
【図６】本発明の第３の実施形態に係るメモリセル１９の中のＮ型ＭＯＳＦＥＴ１４とＮ型ＭＯＳＦＥＴ１７の物理的配置図
【図７】本発明の第４の実施形態に係る半導体集積回路の構成図
【図８】本発明の第４の実施形態に係るタイミングチャート
【図９】従来の半導体集積回路の構成図
【符号の説明】
１比較回路
２Ｎ型ＭＯＳＦＥＴ
３Ｎ型ＭＯＳＦＥＴ
４比較回路出力相補信号線
５電流源
６Ｐ型ＭＯＳＦＥＴ
７Ｐ型ＭＯＳＦＥＴ
８Ｐ型ＭＯＳＦＥＴ
９Ｐ型ＭＯＳＦＥＴ
１０仮想アドレス１ビットの構成
１１仮想アドレス信号線
１２インバータ
１３ワード線
１４Ｎ型ＭＯＳＦＥＴ
１５一致検出信号線
１６メモリセル
１７Ｎ型ＭＯＳＦＥＴ[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a semiconductor integrated circuit.
[0002]
[Prior art]
  A computer system such as a microprocessor is provided with a cache memory that functions as a high-speed buffer memory by storing a part of the program and data in the main memory between the central processing unit and the main memory for high-speed operation. It has been.
[0003]
  In addition, since a virtual address is used as the address of the recent central processing unit, it is necessary to perform high-speed address conversion between the cache memory and the real address of the main memory. For this reason, a table having an associative function called a translation lookaside buffer (hereinafter referred to as TLB) is provided in parallel with the hierarchized table, and a real address is extracted at high speed.
[0004]
  The associative memory described above checks the match / mismatch between the multi-bit input address and the stored data in the multi-bit memory. It is a method to output the data.
[0005]
  As described above, in the associative memory, since multi-bit data is compared at a time, the number of comparison circuits is increased in order to operate at high speed, and accordingly, the circuit area is increased and the power consumption is increased. Japanese Patent Application Laid-Open No. 8-528285 discloses an example in which the search data and the stored data are compared with each other at high speed, with low power consumption and the problem of circuit area. A typical semiconductor integrated circuit of the present invention is shown in FIG. Reference numeral 10 denotes one bit in the virtual address. Reference numeral 11 denotes a virtual address data line. An inverter 12 generates a complementary signal of the virtual address data line 11. Reference numeral 16 denotes a memory cell incorporating a comparison circuit. Reference numeral 13 denotes a word line which serves to store data sent to the virtual address data line 11 in the memory cell 16. Here, although a circuit for selecting or driving a word line is omitted, since these circuits have a widely used circuit configuration, description thereof is omitted. Reference numeral 15 denotes a coincidence detection signal line, and the N-type MOSFET 14 is designed to be turned OFF when the input virtual address 11 and the data in the memory cell 16 coincide. The signal line 15 is connected in parallel to all the input virtual address bits, and the signal line 15 is cut off from the ground terminal only when the input data and the storage data of all the virtual addresses match. The activation signal 33 is a signal line for activating the differential circuit 41. When the activation signal 33 is activated, a current equal to the current flowing in the N-type MOSFET 14 when the data does not match is supplied from the P-type MOSFETs 21 and 29, and the diode-connected N-type MOSFET 22 and the coincidence detection signal line are supplied. 15. A through current flows through the N-type MOSFET 14. Since the N-type MOSFET 27 is cut off, the potential of the signal line 15 rises. The current supplied from the P-type MOSFET 29 flows through the diode-connected N-type MOSFET 25 and N-type MOSFET 26. The reference voltage 32 is set with a potential in the same manner as the current flowing in the MOSFET 14 when one piece of data does not match. In this state, changes in the potentials of the terminals 30 and 31 will be described. When the data on the signal line 15 does not match, the MOSFETs 14 in the comparison circuit are turned on by the number of mismatches, so the signal line 15 is at the highest potential when only the MOSFET 14 in one comparison circuit does not match. At this time, the terminals 30 and 31 have substantially the same potential. Therefore, the currents flowing in the left and right circuits of the coincidence detection circuit 42 are substantially equal. Here, it is designed so that the output 34 of the coincidence detection circuit 42 becomes a high potential when an equal current flows by giving a difference in dimensions of the P-type MOSFETs 32 and 24 which are loads of the coincidence detection circuit 42. That is, in the case of mismatch, it becomes HIGH.
[0006]
[Problems to be solved by the invention]
  In the configuration described in the prior art, in the comparator, in order to achieve both high speed and low power consumption, a short pulse is generated in the activation signal to reduce the through current, but the activation signal is activated. During this time, there is always a path in which current flows from the power source to the ground via the P-channel transistor 21 via the N-channel transistor 14 and a path where current flows from the power source to the ground via the N-channel transistor 25 from the P-channel transistor 29. There was a first problem that a through current flows. Further, since the activation signal is a short pulse, there is a second problem that a separate latch circuit must be added to hold the output data even when the activation signal becomes inactive. Also, variations in the current amount of the transistors 24, 25, 26, and 27 constituting the reference current due to process variations, in particular, the implantation amount when forming the transistor due to the physical disposition of the MOSFET 27 and the MOSFET 14, and the exposure time There has been a third problem that the pattern formation shift becomes large, the current amounts of the MOSFET 27 and the MOSFET 14 are not equal, and the number of defects in the semiconductor integrated circuit increases. Further, since the potentials of the signal lines 30 and 31 are transmitted to the gate and drain of the MOSFET 24 through the gates of the MOSFET 23 and the MOSFET 27 and amplified, it is necessary to pass through the single-stage gate, and no further increase in speed can be expected. There was a fourth problem.
[0007]
[Means for Solving the Problems]
  The present invention compares an input signal line for inputting a multi-bit data signal, a memory cell for storing data, and the input multi-bit data signal with the stored data. At that time, the sources of the first N-type field effect transistors equal in number to the number of input signals to be compared are connected to each other, and a predetermined potential is applied to the sources of the first N-type field effect transistors. And the drains of the first N-type field effect transistor are connected to each other, the drains of the first N-type field effect transistor are connected to the source of the second N-type field effect transistor, The drain of the second N-type field effect transistor is connected to the drain of the first P-type field effect transistor and the drain of the second P-type field effect transistor; The sources of the first P-type field effect transistor and the second P-type field effect transistor are connected to each other and fixed at a predetermined potential, and all the groups of the first N-type field effect transistor are conductive. The source of the third N-type field effect transistor is connected to a current source that is less than the current amount and greater than the current amount that is the only mismatch, and the third N-type field effect transistor The drain is connected to the drain of the third P-type field effect transistor and the drain of the fourth P-type field effect transistor, and the third P-type field effect transistor and the fourth P-type field effect transistor are connected. The sources of the transistors are connected and fixed at a predetermined potential, and the gate of the second P-type field effect transistor is in contact with the source of the fourth P-type field effect transistor. And the gate of the fourth P-type field effect transistor is connected to the source of the second P-type field effect transistor, and the first N-type field effect transistor and the second N-type field effect transistor are connected. When the activation signal is activated by adopting a configuration in which the gates of the first transistor, the first P-type field effect transistor, and the third P-type field effect transistor are connected to the activation signal line The through current does not flow until the drains of the first to fourth P-type field effect transistors drop from a predetermined fixed voltage to the threshold value of the transistor, and the first P-type field effect transistor and the first By amplifying the potential difference between the drains of the three P-type field effect transistors, it is possible to detect the coincidence and mismatch of the data signal and the data. Some useless through current does not flow and power consumption can be reduced.
[0008]
  In addition, the input signal line for inputting a multi-bit data signal, the memory cell for storing the data, and the input multi-bit data signal and the stored data are compared. , The sources of the first N-type field effect transistors equal in number to the number of input signals to be compared are connected to each other, and a predetermined potential is supplied to the sources of the first N-type field effect transistors. And the drains of the first field effect transistors are connected to each other, the drains of the first field effect transistors are connected to the source of the second N type field effect transistor, and the second N type The drain of the field effect transistor is connected to the drain of the first P-type field effect transistor and the drain of the second P-type field effect transistor, and the first P From the amount of current that the sources of the field effect transistor and the second P-type field effect transistor are connected to each other and fixed at a predetermined potential, and all the groups of the first N-type field effect transistors are turned on. The source of the third N-type field effect transistor is connected to a current source that is less and greater than the amount of current that is inconsistent, and the drain of the third N-type field effect transistor is connected to the third source The drain of the P-type field effect transistor is connected to the drain of the fourth P-type field effect transistor, and the sources of the third P-type field effect transistor and the fourth P-type field effect transistor are connected to each other. And fixed at a predetermined potential, the gate of the second P-type field effect transistor is connected to the source of the fourth P-type field effect transistor, And the gates of the second N-type field effect transistor and the third N-type field effect transistor are connected to the source of the second P-type field effect transistor. Is connected to the activation signal, and the gate of the first P-type field effect transistor and the third P-type field effect transistor is connected to the holding signal line, thereby holding the activation signal. When the signal is activated, the data signal and the data coincide with each other by amplifying the potential difference between the drains of the first P-type field effect transistor and the third P-type field effect transistor. By detecting a mismatch and holding the detection result by inactivating only the activation signal, if the holding signal is a signal that takes a longer activation period than the activation signal, Since the detection output data can be held without a through current flowing during that period, it is not necessary to provide a holding circuit in the next stage, and the latch circuit which is the second problem is unnecessary.
[0009]
  In addition, the input signal line for inputting a multi-bit data signal, the memory cell for storing the data, and the input multi-bit data signal and the stored data are compared. , The sources of the first N-type field effect transistors equal in number to the number of input signals to be compared are connected to each other, and a predetermined potential is supplied to the sources of the first N-type field effect transistors. And the drains of the first N-type field effect transistor are connected to each other, the drains of the first N-type field effect transistor are connected to the source of the second N-type field effect transistor, and the second The drain of the N-type field effect transistor is connected to the drain of the first P-type field effect transistor and the drain of the second P-type field effect transistor. The sources of the field effect transistor and the second P-type field effect transistor are connected to each other and fixed at a predetermined potential, and when conducting, the same amount of current flows as the first N-type field effect transistor and the number of bits The source of the third N-type field effect transistor that is always smaller than the first N-type field effect transistor, and a current amount that is smaller than that of the first N-type field effect transistor when conducting is 1 The sources of the four fourth field effect transistors are connected to each other and the same potential as the source of the first N type field effect transistor is supplied, and the drain of the third N type field effect transistor is connected to the fourth field effect transistor. The drain of the field effect transistor is connected, and the source of the fifth N type field effect transistor is connected, and the drain of the fifth N type field effect transistor is connected. IN is connected to the drain of the third P-type field effect transistor and the drain of the fourth P-type field effect transistor, and the third P-type field effect transistor and the fourth P-type field effect transistor The sources of the transistors are connected and fixed at a predetermined potential, the gate of the second P-type field effect transistor is connected to the source of the fourth P-type field effect transistor, and the fourth P-type A gate of the field effect transistor is connected to a source of the second P type field effect transistor, and the second N type field effect transistor, the fifth N type field effect transistor, and the first P The activation signal is activated by adopting a configuration in which the gates of the p-type field effect transistor and the third P-type field effect transistor are connected to the activation signal line. At the same time, by amplifying the difference in potential between the drains of the first P-type field effect transistor and the third P-type field effect transistor, it is possible to detect the coincidence / mismatch of the data signal and the data. The third N-type field effect transistor and the fourth N-type field effect transistor to be compared with the first N-type field effect transistor of the bit to be processed are arranged adjacent to each other, thereby causing process variation as a third problem. Variations in the amount of current due to variations can be suppressed, and defects can be reduced.
[0010]
  In addition, the input signal line for inputting a multi-bit data signal, the memory cell for storing the data, and the input multi-bit data signal and the stored data are compared. , The sources of the first N-type field effect transistors equal in number to the number of input signals to be compared are connected to each other, and a predetermined potential is supplied to the sources of the first N-type field effect transistors. And the drains of the first field effect transistors are connected to each other, the drains of the first field effect transistors are connected to the source of the second N type field effect transistor, and the second N type The drain of the field effect transistor includes the drain of the first P-type field effect transistor, the drain of the second P-type field effect transistor, and the third P-type field effect transistor. Connected to the drain of the transistor, the sources of the first P-type field effect transistor, the second P-type field effect transistor, and the third P-type field effect transistor are connected to each other and set to a predetermined potential. The third N-type field effect transistor is connected to a current source which is fixed and less than the current amount in which all the first N-type field effect transistor groups are turned on, and more than the current amount in which only one is inconsistent. The source of the transistor is connected, and the drain of the third N-type field effect transistor is the drain of the fourth P-type field effect transistor, the fifth P-type field effect transistor, and the sixth P-type field effect. The fourth P-type field effect transistor, the fifth P-type field effect transistor, and the sixth P-type field effect transistor connected to the drain of the type transistor The sources are connected and fixed at a predetermined potential, the gate of the second P-type field effect transistor is connected to the source of the fifth P-type field effect transistor, and the fifth P-type field effect is obtained. The gate of the second transistor is connected to the source of the second P-type field effect transistor, and the gates of the second N-type field effect transistor and the third N-type field effect transistor are activated first. Connected to a signal, gates of the first P-type field effect transistor and the fourth P-type field effect transistor are connected to a holding signal line, and the third P-type field effect transistor and the sixth P-type field effect transistor Since the P-type field effect transistor has a gate connected to the second activation signal line, the first activation signal, the second activation signal, and the holding signal are activated. The difference between the drain potentials of the first P-type field effect transistor and the fourth P-type field effect transistor is calculated as the third P-type field effect transistor and the sixth P-type field. Forcibly spread by the effect transistor and directly transmitted to the gate and drain of the second P-type field effect transistor or the fourth P-type field effect transistor, so that the data signal and the data match or do not match However, it becomes possible to detect at high speed without going through one stage of gate, which is the fourth problem.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
  (Embodiment 1)
  FIG. 1 shows an example of a semiconductor integrated circuit according to a second aspect of the present invention, and shows a one-way set associative (ie, direct map) TLB configuration. Reference numeral 10 denotes one bit in the virtual address. Reference numeral 11 denotes a virtual address data line. An inverter 12 generates 11 complementary signals. Reference numeral 16 denotes a memory cell incorporating a comparison circuit. Reference numeral 13 serves to store data sent to the word line 11 in the memory cell 16. Here, the circuits for selecting and driving the word lines are omitted, but these circuits have a widely used circuit configuration, for example, a circuit that decodes the lower bits of the address and drives it with a buffer. Therefore, detailed description is omitted. Reference numeral 15 denotes a coincidence detection signal line, and the N-type MOSFET 14 is designed to be turned on when the input virtual address coincides with the data in the memory cell. The signal line 15 is connected in parallel to all of the input virtual addresses, and the signal line 15 is cut off from the ground terminal only when the input data and the storage data of all the virtual addresses do not match. The activation signal 35 is a signal line for activating the coincidence detection circuit 1. Reference numeral 5 denotes a current source that drives a current that is smaller than the current that flows through the signal line 15 when the virtual address data matches all the bits and that is larger than the current that flows through the signal line 15 when only one bit of the virtual address data does not match. is there. The source of the N-type MOSFET 2 is connected to the signal line 15, the source of the N-type MOSFET 3 is connected to the current source 5, and the drain of the N-type MOSFET 2 is connected to the comparison circuit output complementary signal line 4. The drain of the N-type MOSFET 3 is connected to the comparison circuit output signal line 36. When the activation signal 35 is inactive, the gates of the N-type MOSFETs 2 and 3 are connected to the activation signal 35. So it is OFF. The sources of the P-type MOSFETs 6, 7, 8, 9 are connected in parallel to the power supply, and the drains of the P-type MOSFETs 6, 7 are connected to the comparison circuit output complementary signal line 4. The drains of the P-type MOSFETs 8 and 9 are connected to the comparison circuit output signal line 36.
[0012]
  Since the gates of the P-type MOSFETs 6 and 8 are connected to the activation signal line 35, they are ON when inactive, and the comparison circuit output signal line 36 and the comparison circuit output complementary signal line 4 are fixed at the same potential as the power supply. ing. In addition, since the gate of the P-type MOSFET 7 is connected to the comparison circuit output signal line 36 and the gate of the P-type MOSFET 9 is connected to the comparison circuit output signal line 36, when the activation signal line 35 is inactive, P-type MOSFETs 7 and 9 are OFF. Whether or not the input virtual address 11 and the data in the memory cell 16 match each other is determined by the N-type MOSFET 14 of each bit, and then the activation signal 35 is activated, and all the virtual addresses 11 and the memory cells are activated by the match detection circuit 1. It is determined whether the data in 16 match, and the result is output to the comparison circuit output signal 36.
[0013]
  FIG. 2 is a timing chart when the activation signal 35 is activated after all the input virtual addresses and the data in the memory cell match. The horizontal axis is the transition time, and the vertical axis is the voltage, showing the transition of each signal line. The P-type MOSFETs 7 and 9 are OFF until the drains of the P-type MOSFETs 6, 7, 8 and 9 are lowered from the power supply potential by the threshold value, and the comparison circuit output complementary signal line 4 is the N-type MOSFET in each memory cell 16. Current flows to ground via. Similarly, in the comparison circuit output signal line 36, a current flows to the ground via a current source. However, each current amount is different, and the potential of the complementary circuit output complementary signal line 4 is earlier than the power supply potential by the threshold value of the P-type MOSFET. This time is T1. From time T1, the P-type MOSFET 9 is turned on, and the current from the power source flows through the comparison circuit output signal line 36. The difference between the amount of current flowing from the P-type MOSFET 9 and the amount of current flowing from the N-type MOSFET 3 to the ground via the current source 5 In proportion to the potential decrease is prevented. After a while, at time T2, the charge of the comparison circuit output complementary signal line 4 flows from the N-type MOSFET 2 to the ground via the N-type MOSFET 14 because there is no supply current from the power source, and the potential of the comparison circuit output complementary signal line 4 becomes Since the gate potential of the P-type MOSFET 9 becomes equal to the ground potential and the potential difference between the power supply and the ground, the P-type MOSFET 9 enters a saturation mode, and a very large current flows through the comparison circuit output signal line 36. The potential rises more rapidly. As described above, when the input address and the data in the memory cell all match, the comparison circuit output signal line 36 becomes HIGH. If even one bit does not match the input virtual address and the data in the memory cell, the behavior of the comparison circuit output complementary signal line 4 and the comparison circuit output signal line is reversed, and the comparison circuit output signal line is LOW. .
[0014]
  As described above, the through current does not flow until the drain of the P-type MOSFET 6 falls from the power supply potential to the threshold value, and the difference between the drain potential of the P-type MOSFET 6 and the drain potential of the P-type MOSFET 8 is amplified by the P-type MOSFET 9. Comparison detection is possible at high speed.
[0015]
  Needless to say, the semiconductor integrated circuit operates in the same manner even if the P-type N-type MOSFET, the potential, and the output signal are reversed. Further, when the virtual address data signals all match, if the signal line 15 is non-conductive, the current source 5 can be realized by a current source through which a smaller current flows than when only one bit matches. At this time, when all the virtual address data signals match, the comparison circuit output signal line 36 becomes LOW. When all of the virtual address data signals are coincident, if it is desired to obtain a HIGH output from the coincidence detection circuit 1, the comparison circuit output complementary signal line 4 may be output.
[0016]
  (Embodiment 2)
  FIG. 3 shows an example of a semiconductor integrated circuit according to a third aspect of the present invention and shows the configuration of a TLB. FIG. 3 is almost the same as FIG. 1 except that the gates of the P-type MOSFETs 6 and 7 are connected to the holding signal 37.
[0017]
  Whether or not the input virtual address 11 and the data in the memory cell 16 match each other is determined by the N-type MOSFET 14 of each bit, and then the activation signal 35 and the holding signal 37 are activated. 11 and whether the data in the memory cell 16 match, the result is output to the comparison circuit output signal 36, and the result is held in the comparison circuit output signal 36 by inactivating only the activation signal 35. The
[0018]
  FIG. 4 shows a timing chart in the case where all the input addresses coincide with the data in the memory cell and the activation signal 35 and the holding signal 37 are activated. The activation signal 35 and the holding signal 37 are activated at approximately the same time. Thereafter, until the comparison circuit output signal 36 becomes HIGH, the same behavior as described in the first embodiment with reference to FIGS. 1 and 2 is performed. At time T3 when the activation signal 35 becomes inactive, the N-type MOSFETs 2 and 3 are turned OFF, the comparison circuit output signal 36 remains HIGH, and the output data is held without adding a latch circuit. .
[0019]
  As described above, the output data is held by activating the holding signal for a long time with respect to the activation signal.
[0020]
  (Embodiment 3)
  FIG. 5 shows an example of a semiconductor integrated circuit according to a fourth aspect of the present invention. 5 is substantially the same as FIG. 1 except that the gate of the N-type MOSFET 17 in the memory cell 19 is replaced with the virtual address 11 in place of the current source 5 in FIG. The gate potential of the N-type MOSFET 14 is fixed to the same potential, the source is grounded, the drain is connected in parallel to the drain of the N-type MOSFET 17 of another bit, and the source of the N-type MOSFET 3 is connected. Yes. Of the N-type MOSFET 17 composed of each bit, only one bit has a shape that is less current than the shape of the N-type MOSFET 14, but the other bits have the same shape as the N-type MOSFET 14. is there. FIG. 6 shows a physical layout of the N-type MOSFET 17 and the N-type MOSFET 14 formed so as to have a small current as viewed from above. As shown in FIG. 6, the sources of the N-type MOSFETs 14 and 17 are made common, the drain shape is made the same, and the gate length of 17 is made larger than the gate length of the N-type MOSFET 14, thereby reducing the current.
[0021]
  As described above, the N-type MOSFETs 14 and 17 are adjacent to each other, and the drain, source, and gate shapes are the same, so that the local dependency on the location of the amount of ion implantation at the time of transistor formation by process manufacturing can be improved, and almost the same performance N-type MOSFETs 14 and 17 can be generated, and process variations can be minimized.
[0022]
  (Embodiment 4)
  FIG. 7 shows an example of a semiconductor integrated circuit according to a fifth aspect of the present invention and shows the configuration of a TLB. 7 is substantially the same as FIG. 3, but the drain of the P-type MOSFET 38 is connected to the comparison circuit output complementary signal 4, the source of the P-type MOSFET 38 is connected to the power supply, and the drain of the P-type MOSFET 39 is the comparison circuit output signal. 36, the source of the P-type MOSFET 39 is connected to the power supply, and the gates of the P-type MOSFETs 38 and 39 are connected to the second activation signal 40.
[0023]
  Whether or not the input virtual address 11 and the data in the memory cell 16 coincide with each other is determined by the N-type MOSFET 14 of each bit. Thereafter, the activation signal 35 and the holding signal 37 are activated, and the second activation signal 40 is The coincidence detection circuit 1 determines whether all the virtual addresses 11 and the data in the memory cell 16 coincide with each other, and outputs the result to the comparison circuit output signal 36. The activation signal 35, the second By inactivating only the activation signal 40, the result is held in the comparison circuit output signal 36.
[0024]
  FIG. 8 shows a timing chart in the case where the input address and the data in the memory cell all coincide, and the activation signal 35, the second activation signal 40, and the holding signal 37 are activated. The activation signal 35 and the holding signal 37 are activated at approximately the same time. The P-type MOSFETs 6, 7, 8, and 9 are OFF until the drains of the P-type MOSFETs 6, 7, 8, and 9 are lowered from the power supply potential by the threshold value, and the comparison circuit output complementary signal line 4 is in each memory cell 16. Current flows to the ground via the N-type MOSFET. Similarly, in the comparison circuit output signal line 36, a current flows to the ground via a current source. However, each current amount is different, and the potential of the complementary circuit output complementary signal line 4 is earlier than the power supply potential by the threshold value of the P-type MOSFET. This time is T4. The second activation signal is supplied at approximately the same time as time T4 when the threshold value of the P-type MOSFET falls.BadActivate. Here, since the second activation signal 40 is connected to the gate of the P-type MOSFET, the LOW period is the activation period. Then, the P-type MOSFET 38, the P-type MOSFET 39, and the P-type MOSFET 9 are turned on, the current flows from the power source to the comparison circuit output signal line 36, the total amount of current flowing from the P-type MOSFET 39 and the P-type MOSFET 9, and the current source from the N-type MOSFET 3 The potential of the comparison circuit output signal line 36 is prevented from decreasing in proportion to the difference in the amount of current flowing to the ground via 5. Further, the potential of the complementary circuit output complementary signal line 4 is prevented from decreasing in proportion to the difference between the current supplied to the P-type MOSFET 38 and the amount of current flowing to the ground via the N-type MOSFET in each memory cell 16. It is done. The difference between the potential of the comparison circuit output signal line 36 and the potential of the comparison circuit output complementary signal line 4 is always constant because the voltage difference between the gate and source of the P-type MOSFET 38 and P-type MOSFET 39 is always constant. ForThat is, by adding a constant current source, charges rapidly accumulate in the comparison circuit output signal line 36 and the comparison circuit output complementary signal line 4.The P-type MOSFET 9 transitions to the saturation mode earlier than the time described in the first embodiment, and a larger current flows through the comparison circuit output signal line 36, and the comparison circuit output signal line 36 expands more rapidly than the time described in the first embodiment. The potential at 36 rises more rapidly. Activation signal 35Becomes inactive, The second activation signal 40 isActivityIn this case, the N-type MOSFETs 2 and 3 are turned OFF, the comparison circuit output signal 36 remains HIGH, and the output data is held without adding a latch circuit.
[0025]
By activating the second activation signal, the current is forcibly increased from the P-type MOSFET 38 and the P-type MOSFET 39 to be directly transmitted to the gate and drain of the P-type MOSFET 9 and the potential of the drain of the P-type MOSFET 6 and P The difference from the potential of the drain of the MOSFET 8 can be compared and detected at high speed, and the output data is held by activating the holding signal with respect to the first activation signal.
[0026]
【The invention's effect】
  As described above, the present invention compares the input signal line for inputting a multi-bit data signal, the memory cell for storing the data, the input multi-bit data signal and the stored data, , Non-conducting when conducting and mismatching, the sources of the first N-type field effect transistors equal in number to the number of input signals to be compared are connected to each other, and the sources of the first N-type field-effect transistors are connected to each other A predetermined potential is supplied, the drains of the first N-type field effect transistor are connected to each other, and the drains of the first N-type field effect transistor are connected to the source of the second N-type field effect transistor The drain of the second N-type field effect transistor is connected to the drain of the first P-type field effect transistor and the drain of the second P-type field effect transistor. A group of the first N-type field effect transistors connected to each other, the sources of the first P-type field effect transistor and the second P-type field effect transistor are connected to each other and fixed to a predetermined potential; The third N-type field effect transistor is connected to a current source that is less than the current amount in which all of the transistors are turned on and larger than the current amount in which only one is inconsistent, and the third N-type field effect The drain of the p-type transistor is connected to the drain of the third p-type field effect transistor and the drain of the fourth p-type field effect transistor, and the third p-type field effect transistor and the fourth p-type transistor Sources of field effect transistors are connected to each other and fixed at a predetermined potential, and the gate of the second P type field effect transistor is the fourth P type field effect transistor. Connected to the source, the gate of the fourth P-type field effect transistor is connected to the source of the second P-type field effect transistor, and the first N-type field effect transistor and the second N-type field effect transistor The activation signal is activated by adopting a configuration in which the gates of the p-type field effect transistor, the first p-type field effect transistor, and the third p-type field effect transistor are connected to the activation signal line. Then, the through current does not flow until the drains of the first to fourth P-type field effect transistors drop from a predetermined fixed voltage to the threshold value of the transistor, and the first P-type field effect transistor And the third P-type field effect transistor by amplifying the difference between the drain potentials, it is possible to detect the coincidence and mismatch between the data signal and the data. Useless through current does not flow and power consumption can be reduced.
[0027]
  In addition, the input signal line for inputting a multi-bit data signal, the memory cell for storing the data, and the input multi-bit data signal and the stored data are compared. , The sources of the first N-type field effect transistors equal in number to the number of input signals to be compared are connected to each other, and a predetermined potential is supplied to the sources of the first N-type field effect transistors. And the drains of the first field effect transistors are connected to each other, the drains of the first field effect transistors are connected to the source of the second N type field effect transistor, and the second N type The drain of the field effect transistor is connected to the drain of the first P-type field effect transistor and the drain of the second P-type field effect transistor, and the first P From the amount of current that the sources of the field effect transistor and the second P-type field effect transistor are connected to each other and fixed at a predetermined potential, and all the groups of the first N-type field effect transistors are turned on. The source of the third N-type field effect transistor is connected to a current source that is less and greater than the amount of current that is inconsistent, and the drain of the third N-type field effect transistor is connected to the third source The drain of the P-type field effect transistor is connected to the drain of the fourth P-type field effect transistor, and the sources of the third P-type field effect transistor and the fourth P-type field effect transistor are connected to each other. And fixed at a predetermined potential, the gate of the second P-type field effect transistor is connected to the source of the fourth P-type field effect transistor, And the gates of the second N-type field effect transistor and the third N-type field effect transistor are connected to the source of the second P-type field effect transistor. Is connected to the activation signal, and the gate of the first P-type field effect transistor and the third P-type field effect transistor is connected to the holding signal line, thereby holding the activation signal. When the signal is activated, the data signal and the data coincide with each other by amplifying the potential difference between the drains of the first P-type field effect transistor and the third P-type field effect transistor. By detecting a mismatch and holding the detection result by inactivating only the activation signal, if the holding signal is a signal that takes a longer activation period than the activation signal, Since the detection output data can be held without a through current flowing during that period, it is not necessary to provide a holding circuit in the next stage, and the area can be reduced.
[0028]
  In addition, the input signal line for inputting a multi-bit data signal, the memory cell for storing the data, and the input multi-bit data signal and the stored data are compared. , The sources of the first N-type field effect transistors equal in number to the number of input signals to be compared are connected to each other, and a predetermined potential is supplied to the sources of the first N-type field effect transistors. And the drains of the first N-type field effect transistor are connected to each other, the drains of the first N-type field effect transistor are connected to the source of the second N-type field effect transistor, and the second The drain of the N-type field effect transistor is connected to the drain of the first P-type field effect transistor and the drain of the second P-type field effect transistor. The sources of the field effect transistor and the second P-type field effect transistor are connected to each other and fixed at a predetermined potential, and when conducting, the same amount of current flows as the first N-type field effect transistor and the number of bits The source of the third N-type field effect transistor that is always smaller than the first N-type field effect transistor, and a current amount that is smaller than that of the first N-type field effect transistor when conducting is 1 The sources of the four fourth field effect transistors are connected to each other and the same potential as the source of the first N type field effect transistor is supplied, and the drain of the third N type field effect transistor is connected to the fourth field effect transistor. The drain of the field effect transistor is connected, and the source of the fifth N type field effect transistor is connected, and the drain of the fifth N type field effect transistor is connected. IN is connected to the drain of the third P-type field effect transistor and the drain of the fourth P-type field effect transistor, and the third P-type field effect transistor and the fourth P-type field effect transistor The sources of the transistors are connected and fixed at a predetermined potential, the gate of the second P-type field effect transistor is connected to the source of the fourth P-type field effect transistor, and the fourth P-type A gate of the field effect transistor is connected to a source of the second P type field effect transistor, and the second N type field effect transistor, the fifth N type field effect transistor, and the first P The activation signal is activated by adopting a configuration in which the gates of the p-type field effect transistor and the third P-type field effect transistor are connected to the activation signal line. At the same time, by amplifying the difference in potential between the drains of the first P-type field effect transistor and the third P-type field effect transistor, it is possible to detect the coincidence / mismatch of the data signal and the data. The third N-type field effect transistor and the fourth N-type field effect transistor to be compared with the first N-type field effect transistor of the bit to be used are arranged adjacent to each other, thereby changing the current amount due to process variation fluctuations. Can be suppressed and defects can be reduced.
[0029]
  In addition, the input signal line for inputting a multi-bit data signal, the memory cell for storing the data, and the input multi-bit data signal and the stored data are compared. , The sources of the first N-type field effect transistors equal in number to the number of input signals to be compared are connected to each other, and a predetermined potential is supplied to the sources of the first N-type field effect transistors. And the drains of the first field effect transistors are connected to each other, the drains of the first field effect transistors are connected to the source of the second N type field effect transistor, and the second N type The drain of the field effect transistor includes the drain of the first P-type field effect transistor, the drain of the second P-type field effect transistor, and the third P-type field effect transistor. Connected to the drain of the transistor, the sources of the first P-type field effect transistor, the second P-type field effect transistor, and the third P-type field effect transistor are connected to each other and set to a predetermined potential. The third N-type field effect transistor is connected to a current source which is fixed and less than the current amount in which all the first N-type field effect transistor groups are turned on, and more than the current amount in which only one is inconsistent. The source of the transistor is connected, and the drain of the third N-type field effect transistor is the drain of the fourth P-type field effect transistor, the fifth P-type field effect transistor, and the sixth P-type field effect. The fourth P-type field effect transistor, the fifth P-type field effect transistor, and the sixth P-type field effect transistor connected to the drain of the type transistor The sources are connected and fixed at a predetermined potential, the gate of the second P-type field effect transistor is connected to the source of the fifth P-type field effect transistor, and the fifth P-type field effect is obtained. The gate of the second transistor is connected to the source of the second P-type field effect transistor, and the gates of the second N-type field effect transistor and the third N-type field effect transistor are activated first. Connected to a signal, gates of the first P-type field effect transistor and the fourth P-type field effect transistor are connected to a holding signal line, and the third P-type field effect transistor and the sixth P-type field effect transistor Since the gate of the P-type field effect transistor is connected to the second activation signal line, the first activation signal, the second activation signal, and the holding signal are activated. The difference between the drain potentials of the first P-type field effect transistor and the fourth P-type field effect transistor is set to the third P-type field effect transistor and the sixth P-type. The data signal coincides with the data by being forcibly spread by a field effect transistor and directly transmitted to the drain and gate of the second P-type field effect transistor or the fourth P-type field effect transistor. , Mismatch can be detected at high speed.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.
FIG. 2 is a timing chart according to the first embodiment of the present invention.
FIG. 3 is a configuration diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.
FIG. 4 is a timing chart according to the second embodiment of the present invention.
FIG. 5 is a configuration diagram of a semiconductor integrated circuit according to a third embodiment of the present invention.
FIG. 6 is a physical layout diagram of an N-type MOSFET 14 and an N-type MOSFET 17 in a memory cell 19 according to a third embodiment of the present invention.
FIG. 7 is a configuration diagram of a semiconductor integrated circuit according to a fourth embodiment of the present invention.
FIG. 8 is a timing chart according to the fourth embodiment of the present invention.
FIG. 9 is a configuration diagram of a conventional semiconductor integrated circuit.
[Explanation of symbols]
  1 Comparison circuit
  2 N-type MOSFET
  3 N-type MOSFET
  4 Complementary circuit output complementary signal line
  5 Current source
  6 P-type MOSFET
  7 P-type MOSFET
  8 P-type MOSFET
  9 P-type MOSFET
  10 Configuration of 1-bit virtual address
  11 Virtual address signal line
  12 Inverter
  13 word lines
  14 N-type MOSFET
  15 Match detection signal line
  16 memory cells
  17 N-type MOSFET

Claims

An input signal line for inputting a multi-bit data signal, a memory cell for storing data, and the input multi-bit data signal and the stored data are compared. The sources of the first N-type field effect transistors equal in number to the number of input signals to be compared are connected to each other, a predetermined potential is supplied to the sources of the first N-type field effect transistors, and The drains of the first field effect transistors are connected to each other, the drains of the first field effect transistors are connected to the source of a second N type field effect transistor, and the second N type field effect is connected. The drain of the p-type transistor is connected to the drain of the first p-type field effect transistor and the drain of the second p-type field effect transistor, and the first p-type electric field The source of the fruit transistor and the second P-type field effect transistor are connected to each other and fixed at a predetermined potential, and the drain of the third N-type field effect transistor is the third P-type field effect transistor. Are connected to the drain of the fourth P-type field effect transistor, the sources of the third P-type field effect transistor and the fourth P-type field effect transistor are connected to each other, and have a predetermined potential. The gate of the second P-type field effect transistor is connected to the drain of the fourth P-type field effect transistor, and the gate of the fourth P-type field effect transistor is connected to the second P Integrated circuit characterized by being connected to the drain of a p- type field effect transistor.

An input signal line for inputting a multi-bit data signal, a memory cell for storing data, and the input multi-bit data signal and the stored data are compared. The sources of the first N-type field effect transistors equal in number to the number of input signals to be compared are connected to each other, a predetermined potential is supplied to the sources of the first N-type field effect transistors, and The drains of the first N-type field effect transistor are connected to each other, the drains of the first N-type field effect transistor are connected to the source of the second N-type field effect transistor, and the second The drain of the N-type field effect transistor is connected to the drain of the first P-type field effect transistor and the drain of the second P-type field effect transistor. Current amount in which the sources of the N-type field effect transistor and the second P-type field effect transistor are connected to each other and fixed at a predetermined potential, and all the groups of the first N-type field effect transistor are turned on. The source of the third N-type field effect transistor is connected to a current source that is less than and greater than the amount of current that is the only mismatch, and the drain of the third N-type field effect transistor is connected to the third current source. Connected to the drain of the P-type field effect transistor and the drain of the fourth P-type field effect transistor, and the sources of the third P-type field effect transistor and the fourth P-type field effect transistor are connected to each other. fixed connected to and a predetermined potential, the gate of the second P-type field effect transistor is connected to the drain of said fourth P-type field effect transistor, Serial gate of the fourth P-type field effect transistor is connected to the drain of the second P-type field effect transistor, the first N-type field effect transistor and the second N-type field effect transistor And the first P-type field effect transistor and the gate of the third P-type field effect transistor are connected to an activation signal line, and when the activation signal is activated, A semiconductor integrated circuit characterized by detecting the coincidence / mismatch of the data signal and the data by amplifying a difference in potential between the drains of the P-type field effect transistor and the third P-type field effect transistor. circuit.

An input signal line for inputting a multi-bit data signal, a memory cell for storing data, and the input multi-bit data signal and the stored data are compared. The sources of the first N-type field effect transistors equal in number to the number of input signals to be compared are connected to each other, a predetermined potential is supplied to the sources of the first N-type field effect transistors, and The drains of the first field effect transistors are connected to each other, the drains of the first field effect transistors are connected to the source of a second N type field effect transistor, and the second N type field effect is connected. The drain of the p-type transistor is connected to the drain of the first p-type field effect transistor and the drain of the second p-type field effect transistor, and the first p-type electric field More than the amount of current in which the sources of the fruit type transistor and the second P-type field effect transistor are connected to each other and fixed at a predetermined potential, and all the groups of the first N-type field effect transistors are turned on. The source of the third N-type field effect transistor is connected to a current source that is less and greater than the amount of current that is mismatched, and the drain of the third N-type field effect transistor is connected to the third P Connected to the drain of the p-type field effect transistor and the drain of the fourth p-type field effect transistor, and the sources of the third p-type field effect transistor and the fourth p-type field effect transistor are connected to each other. and is fixed to a predetermined potential, the gate of the second P-type field effect transistor is connected to the drain of said fourth P-type field effect transistor, the fourth The gate of the P-type field effect transistor is connected to the drain of the second P-type field effect transistor, said second N-type field effect transistor and the third N-type field effect gate transistors activity The activation signal and the holding signal are activated in a configuration in which the gates of the first P-type field effect transistor and the third P-type field effect transistor are connected to the holding signal line. And amplifying a difference in potential between the drains of the first P-type field effect transistor and the third P-type field effect transistor to detect coincidence or mismatch between the data signal and the data, A semiconductor integrated circuit, wherein only the activation signal is inactivated and the detection result is held.

An input signal line for inputting a multi-bit data signal, a memory cell for storing data, and the input multi-bit data signal and the stored data are compared. The sources of the first N-type field effect transistors equal in number to the number of input signals to be compared are connected to each other, a predetermined potential is supplied to the sources of the first N-type field effect transistors, and The drains of the first N-type field effect transistor are connected to each other, the drains of the first N-type field effect transistor are connected to the source of the second N-type field effect transistor, and the second N-type field effect transistor is connected. The drain of the p-type field effect transistor is connected to the drain of the first p-type field effect transistor and the drain of the second p-type field effect transistor. The source of the fruit transistor and the second P-type field effect transistor are connected to each other and fixed at a predetermined potential, and when conducting, the same amount of current flows as that of the first N-type field effect transistor and from the number of bits. The source of the third N-type field effect transistor which is always smaller and smaller than the first N-type field effect transistor, and one current which is smaller than the first N-type field effect transistor and is always conductive when conducting. The sources of the fourth field effect transistor are connected to each other and the same potential as the source of the first N type field effect transistor is supplied, and the drain of the third N type field effect transistor and the fourth electric field are supplied. The drain of the effect transistor is connected, and the source of the fifth N-type field effect transistor is connected, and the drain of the fifth N-type field effect transistor is connected. , Connected to the drain of the third P-type field effect transistor and the drain of the fourth P-type field effect transistor, of the third P-type field effect transistor and the fourth P-type field effect transistor. The sources are connected and fixed at a predetermined potential, the gate of the second P-type field effect transistor is connected to the drain of the fourth P-type field effect transistor, and the fourth P-type field effect is obtained. A gate of the n-type transistor is connected to a drain of the second p-type field effect transistor, the second n-type field effect transistor, the fifth n-type field effect transistor, and the first p-type field In the configuration in which the gates of the effect transistor and the third P-type field effect transistor are connected to the activation signal line, when the activation signal is activated, the first P A semiconductor integrated circuit, wherein the data signal and the data are detected to coincide with each other by amplifying a potential difference between a drain of the p-type field effect transistor and the third P-type field effect transistor.

An input signal line for inputting a multi-bit data signal, a memory cell for storing data, and the input multi-bit data signal and the stored data are compared. The sources of the first N-type field effect transistors equal in number to the number of input signals to be compared are connected to each other, a predetermined potential is supplied to the sources of the first N-type field effect transistors, and The drains of the first field effect transistors are connected to each other, the drains of the first field effect transistors are connected to the source of a second N type field effect transistor, and the second N type field effect is connected. The drains of the p-type transistors are the drain of the first p-type field effect transistor, the drain of the second p-type field effect transistor, and the third p-type field effect transistor. The first P-type field effect transistor, the second P-type field effect transistor, and the third P-type field effect transistor are connected to each other and at a predetermined potential. The third N-type field effect transistor is connected to a current source which is fixed and less than the current amount in which all the first N-type field effect transistor groups are turned on, and more than the current amount in which only one is inconsistent. The source of the transistor is connected, and the drain of the third N-type field effect transistor is the drain of the fourth P-type field effect transistor, the fifth P-type field effect transistor, and the sixth P-type field effect. Connected to the drain of the type transistor, the source of the fourth P-type field effect transistor, the fifth P-type field effect transistor, and the sixth P-type field effect transistor Each other are fixed to the connected and a predetermined potential, the gate of the second P-type field effect transistor is connected to the drain of the fifth P-type field effect transistor, said fifth P-type field-effect The gate of the transistor is connected to the drain of the second P-type field effect transistor, and the gates of the second N-type field effect transistor and the third N-type field effect transistor are the first activation signal. And the gates of the first P-type field effect transistor and the fourth P-type field effect transistor are connected to a holding signal line, and the third P-type field effect transistor and the sixth P-type field effect transistor In the configuration in which the gate of the P-type field effect transistor is connected to the second activation signal line, when the first activation signal, the second activation signal, and the holding signal are activated, 1 The first activation signal is detected by detecting a coincidence or mismatch between the data signal and the data by amplifying a potential difference between the drains of the P-type field effect transistor and the fourth P-type field effect transistor. And a second activation signal being deactivated to hold the detection result.