JPH0643961A - Data processor - Google Patents

Abstract

PURPOSE:To perform data processing, program by program, without any waste by selecting the optimum clock for the delay time between registers as a clock of each register with a software instruction. CONSTITUTION:The data processor consists of plural clock oscillators 10 and 11, a clock selection indication register 1 which is set with a software instruction, and selecting circuits 6-9 which select and supply clocks to respective registers 2-5 according to contents indicated by the clock selection indication register 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more particularly to control of a clock signal of a register.

[0002]

2. Description of the Related Art A conventional data processor sets data in a register with a single clock signal, and its frequency is set according to the maximum delay time between registers.

Further, when the reading time of the memory or the like is considerably long, the clock between the registers is made to wait and the data of the memory or the like is kept waiting.

Further, when a plurality of clocks are set and used instead of a single clock, effective use is achieved by setting the data that arrives much earlier than the maximum delay time earlier.

FIG. 2A is a block diagram showing the relationship between registers and clock signals in a conventional data processing device. In the figure, there are logic circuits 25 and 26 between a register 21 and a register 23, a logic circuit 26 between the registers 22 and 23, and a logic circuit 27 between the registers 23 and 24. . Further, the clock of the registers 21 to 24 is a single clock S1.

In this case, the frequency of the clock S1 is 10M.
If the frequency is Hz, the time between clocks is 100 ns and it takes 200 ns to transit from the register 21 or 22 to the register 24.
is necessary. In this case, if the delay time of the logic circuits 25 and 26 and the delay time of the logic circuit 27 are close to 100 ns, they are effectively used. FIG. 2B shows the clock signal S1.
It is a figure which shows the transition state of the registers 21-24.

However, if the delay time of each of the logic circuits 25 to 27 is about 50 ns, the clock of the register 23 can be set at the intermediate clock S1 'of S1 as shown by the broken line in the timing chart of FIG. Further, since the transition from the register 23 to the register 24 can be performed in 50 ns, the operation can be performed by the transition of the broken line like (register 23) (register 24). Therefore, by adopting the clock S1 ′ having an intermediate phase of the clock S1 as the clock input to the register 23, the registers 21 and 22 to the register 24 can be used.
The transition to is completed in 100 ns, which is half the time described above.

In some cases, the path from the register 21 to the register 23 may be lost when a certain program operates. At this time, the delay time of the logic circuit 25 can be ignored, and the logic circuit between the register 22 and the register 23 can be ignored. 26
Since it is only necessary to consider the delay time of, the register 23 can be set earlier and the efficiency can be improved. However, in the conventional data processing device, once the clock is determined, it becomes fixed and cannot be changed, so that it cannot be effectively used even if it passes through a path with a short delay time.

[0009]

As described above, in the conventional clock control system, once the hardware design is completed, it becomes fixed at that point and cannot be changed thereafter. That is, in the case of changing the frequency of the clock, in the conventional technique, only the change of the clock oscillator is necessary, and the change of the hardware is accompanied with respect to the path having a strict delay time. Further, depending on the software, when the data passes through only the path having a short delay time, a fixed clock signal wastes time, which hinders performance improvement.

[0010]

A data processing apparatus according to the present invention includes a register for setting data, an oscillator for outputting a plurality of clocks having different phases for setting data in the register, and the plurality of oscillators. An instruction register for storing instruction content for selecting a desired clock from the clocks, and a selection circuit for selecting a desired clock from the plurality of clocks according to the instruction content stored in the instruction register and giving the selected clock to the register. There is.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The logic circuit 12 is provided between the register 2 and the logic circuit 13, the logic circuit 13 is provided between the register 3 and the register 4, and the logic circuit 14 is provided between the register 4 and the register 5.
Is provided.

The contents instructed to the clock selection instruction register 1 by the software instruction are the registers 2, 3, 4, 5
Instruct the selection of the clock.

First, the contents of the clock selection instruction register 1 instructed by the software instruction are the selection circuits 6, 7,
Sent to 8 and 9. The selection circuits 6, 7, 8 and 9 receive the clocks S1 and S2 sent from the clock oscillators 10 and 11 as input, and select signals 15, 16, 17 and 18 to optimize the delay time between the registers. , 3,
The performance of the device is improved by selecting 4, 5 clocks.

That is, as in the case of FIG. 2, in FIG. 1 as well, when the logic circuits 13 and 14 have a delay time of half the period of the clock S1 or less, the logic circuit 12 does not pass through as described above (that is, from the register 2 to the register). In the case of a program (without transition of 4), the clock selection instruction register 1 is set in advance by a software instruction to select the clock S2 of the intermediate phase of the clock S1 and sent to the register, so that the area between the registers 3 and 5 is conventionally changed. The operation is completed in half the time.

[0016]

As described above, according to the present invention, by selecting an optimum clock from among a plurality of clocks having different phases as a clock of each register, it is possible to make an optimum processing device with no waste for each program. There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

2A and 2B are a block diagram and a time chart, respectively, of a conventional data processing device.

[Explanation of symbols]

 1 Clock selection instruction register 2-5, 21-24 register 6-9 Selection circuit 10, 11 Clock oscillator 12, 13, 14, 25, 26, 27 Logic circuit

Claims (2)

[Claims] 1. A register for setting data,
An oscillator for outputting a plurality of clocks having different phases for setting data in the register, an instruction register for storing instruction content for selecting a desired clock from the plurality of clocks, and an instruction stored in the instruction register A data processing device, comprising: a selection circuit that selects a desired clock from the plurality of clocks according to contents and supplies the selected clock to the register. 2. The data processing apparatus according to claim 1, wherein the instruction content is set in the instruction register by a software instruction.