JPH0642687B2 - Frequency discriminator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a frequency discriminator for extracting frequency error information from a received signal including an uncertain carrier frequency deviation in a terrestrial or satellite microwave communication system or the like.

(Prior Art) In terrestrial and satellite microwave communication systems, a high frequency of several GHz is used as a carrier frequency. Therefore, a large offset variation occurs in the carrier frequency due to the frequency conversion operation in each part on the transmission path and the Doppler caused by the movement of the satellite or the mobile station. In particular, in a low modulation speed system such as mobile communication, the maximum frequency deviation may be equal to or higher than the modulation frequency, and compensation of this frequency deviation becomes a big problem.

Generally, the compensation of the frequency deviation is performed by an automatic frequency control circuit placed in front of the demodulation circuit. The automatic frequency control circuit drives the voltage controlled oscillator by using the frequency error information extracted from the received signal, and operates to sequentially correct the received carrier frequency by loop control. Among them, the frequency discriminator has a role of inputting a received signal including an uncertain frequency deviation and extracting frequency error information.

As a conventional frequency discriminator, a cross product type frequency error detector as shown in FIG. 2 is often used. In addition,
For more information on this, please see IEEE TRANSACTION ON COMMUNICATI
ON Journal August 1984, pages 935-947, "AFC Tracki
ng Algorithms "(written by FD Natali) and will be described below only in brief. In FIG. 2, the delay means 11 in FIG. The second delay means 12 receives the real part of the quadrature signal obtained by the quasi-coherent detection and delays the input signal for a fixed time, and delays the input signal for the fixed time by receiving the imaginary part of the quadrature signal. The first multiplier 13 multiplies the output of the first delay circuit 11 by the imaginary part of the quadrature signal, and the second multiplier 14 multiplies the output of the second delay means 12 by the real part of the quadrature signal. The subtractor 15 subtracts the output of the second multiplier 14 from the output of the first multiplier 13. The output of the subtractor 15 becomes frequency error information. Letting Δf be the frequency deviation of the received signal, The quadrature signal r (t) obtained by quasi-coherent detection of the received signal is r (t) = [p (t) + jq (T)] exp (j2 _Π Δt), where p (t) and q (t) represent the real axis component and the imaginary axis component of the modulated signal, respectively. If the delay time of the delay means 11 and 12 is set to T, the output d (t) of the cross product type frequency detector with r (t) as input is d (t) = [p
(t) p (t−T) + q (t) q (t−T)] sin ( _2ΠΔT ) +
[q (t) p (t-T) -p (t) -T)] cos ( _2ΠΔT ). When T is sufficiently small with respect to the modulation period, the polarity in [] of the first term in the above equation is always positive, and the first
The term has frequency error information represented by sin (2 _Π ΔT). On the other hand, the second term takes a random value according to the modulation patterns p (t) and q (t), and becomes unnecessary pattern jitter. However, as an exception, when r (t) is a two-phase modulation signal, p (t) =
From q (t), the second term becomes zero and the pattern jitter disappears.

Next, another conventional frequency discriminator is shown in FIG.
In FIG. 3, the modulation removing means 16 receives a quadrature signal obtained by quasi-coherent detection of a digital phase modulation signal containing an uncertain carrier frequency deviation, and removes the modulation of the input signal by multiplying operation. Receiving the output of the modulation removing means 16,
A cross product type frequency error detector including first and second delay means 11 and 12, first and second multipliers 13 and 14, and subtractor 15 detects frequency error information. Here, the delay time of the first and second delay means 11 and 12 is a modulation cycle. The sampler 17 receives the continuous output of the subtractor 15, and samples only the signal points showing correct frequency error information calculated using the converged signal points from among them by the modulation clock. The output of the sampler 17 becomes discrete frequency error information of one sample for each modulation cycle. Assuming that the frequency deviation of the received signal is Δ and the number of modulation phases is M, the signal r ′ (t) whose modulation has been removed by the modulation removing means 10 is r ′ (t) = exp (j
2 _Π MΔt). First and second delay means
If the delay time of 11 and 12 and T are set, the output d (n
T) becomes d (nT) = sin (2 Π MΔT) (n is an integer). From the above equation, there is no pattern jitter due to modulation in the output of the frequency discriminator having the configuration shown in FIG. On the other hand, however, the range of the frequency deviation that can be pulled in is | Δ | < _s / 2M, and the range becomes narrower as the number M of modulation phases increases. Here, _s is the modulation frequency and is represented by 1 / T.

(Problems to be Solved by the Invention) As described above, in the conventional frequency discriminator, if the modulation of the received signal is not removed before the cross product type frequency error detector, pattern jitter due to the modulation is a problem. Becomes On the other hand, when removing the modulation of the received signal,
The frequency deviation of the received signal is multiplied by M due to the multiplication operation, etc., and as a result, the frequency pull-in range becomes 1 / M. In addition, when large level noise is mixed, non-linear loss due to the removal of modulation becomes a problem. The object of the present invention is to perform equalization separately at different times within the same modulation code.
It is an object of the present invention to provide a frequency discriminator which realizes a wide frequency pull-in range at the same time by making the pattern jitter after the pull-in end zero by detecting the frequency error information using the point convergence signal.

(Means for Solving the Problem) A frequency discriminator according to the present invention receives a real part of a quadrature signal obtained by quasi-coherent detection of a digital phase modulation signal including an uncertain carrier frequency deviation, and within one modulation code section. First of
A first filter for equalizing the input signal so as not to receive the intersymbol interference at the time of 1 and the imaginary part of the orthogonal signal,
A second filter having the same characteristics as the first filter for equalizing the input signal so as not to receive intersymbol interference at the first time within the modulation code section; and a real part of the orthogonal signal,
A third filter for equalizing the input signal so as not to receive intersymbol interference at the second time within the modulation code section, and the imaginary part of the orthogonal signal are received at the second time within one modulation code section. The third signal is equalized so that the input signal is not subjected to intersymbol interference.
A fourth filter having the same characteristics as that of the first filter, first delay means for receiving the output of the first filter, and delaying the input signal by the time from the first time to the second time, Receiving the output of the second filter,
Second delay means for delaying the input signal by the time from the time to the second time, and a first multiplier for multiplying the output of the first delay means and the output of the fourth filter, A second multiplier for multiplying the output of the second delay means by the output of the third filter; a subtractor for subtracting the output of the second multiplier from the output of the first multiplier; And a sampler which receives the output of the subtractor and samples only the signal points showing the correct frequency error information with the modulation clock.

(Example) Next, this invention is demonstrated with reference to drawings. FIG. 1 shows a block diagram of a frequency discriminator according to the present invention. In the figure, a thick line shows an orthogonal signal (or a complex signal) and a thin line shows a real number signal.

In FIG. 1, a first filter 1 receives a real part of a quadrature signal obtained by quasi-coherent detection of a digital phase modulation signal including an indeterminate carrier frequency deviation, and receives a first time within one modulation code section. In addition, the input signal is prevented from receiving intersymbol interference. The second filter 2 receives the imaginary part of the orthogonal signal and prevents the input signal from receiving intersymbol interference at the first time within one modulation code section. The second filter 2 is the first
The filter 1 has the same characteristics as the filter 1. The third filter 3 is
The real part of the quadrature signal is received so that the input signal is not subjected to intersymbol interference at the second time within one modulation code section. Fourth
The filter 4 receives the imaginary part of the quadrature signal and prevents the input signal from receiving intersymbol interference at the second time within one modulation code section. The fourth filter 4 has the same characteristics as the third filter 3. Here, the first time is a time earlier than the second time. The first delay means 5 receives the output of the first filter 1 and delays the input signal by the time from the first time to the second time. Second delay means 6
Receives the output of the second filter 2 and delays the input signal by the time from the first time to the second time. The first multiplier 7 multiplies the output of the first delay means 5 and the output of the fourth filter 4. The second multiplier 8 multiplies the output of the second delay means 6 and the output of the third filter 3. The subtractor 9 subtracts the output of the second multiplier 8 from the output of the first multiplier 7. The first and second delay means 5 and 6, the first and second multipliers 7 and 8 and the subtractor 9 constitute a cross product type frequency detector. The sampler 10 receives the continuous output of the subtractor 9, and samples only the signal points showing correct frequency error information calculated using the converged signal points from among them by the modulation clock. The output of the sampler 10 becomes discrete frequency error information of one sample for each modulation period.

FIG. 4 shows a signal obtained by passing the received signal through the optimum filter. In the figure, one modulation code section is represented by T. FIG. 4 shows a signal obtained by equalizing the received signal with the first or second filter 1, 2. In the figure, the time from the starting point of time T to the first time when the signal is equalized is T ₁ . FIG. 5 shows a signal obtained by equalizing the received signal with the third or fourth filter 3, 4. In the figure, the time from the starting point of time T to the second time when the signal is equalized is T ₂ . At time T, the code does not change due to the modulation, and the modulation codes at the first time and the second time are the same. Therefore, the phase change caused in the time (T ₂ −T ₁ ) from the first time to the second time is due only to the frequency deviation.
Therefore, the frequency error information is detected by the cross product type frequency detector using the respective convergence signals at the first and second times. In FIGS. 4, 5, and 6, the two-phase modulation signal is described as an example, but the same applies to the M-phase modulation signal. The sampler 10 is for converting a continuous signal into a discrete signal (A / D conversion) and is placed at the final stage of the block in FIG. 1. There are several ways to think about it. For example, a configuration in which a sampler is placed after each of the first, second, third, and fourth filters to perform A / D conversion is naturally conceivable, and can be regarded as essentially the same as the configuration in FIG.

The above is the frequency discriminator by this invention.

(Effects of the Invention) As described above, according to the present invention, by observing the phase change between two converging signals that are separately equalized at different times within the same modulation code, the change in code due to modulation can be made independent. Instead, frequency error information can be detected. As a result, the pattern jitter due to the modulation disappears after the pulling-in when the average value of the frequency error becomes almost zero. Further, it is not necessary to remove the modulation, and it is possible to avoid the reduction of the frequency pull-in range due to the multiplication operation. Further, effects such as elimination of non-linear loss due to removal of modulation can be expected.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG.
FIG. 3 is a diagram for explaining the prior art, FIG. 4, and FIG.
FIG. 6 and FIG. 6 are waveform charts showing the operation of each part of the embodiment shown in FIG. In the figure, 1,2,3,4 ... filter, 5,6,11,12 ... delay means, 7,8,13,14
… Multiplier, 9,15… Subtractor, 10,17… Sampler.

Claims (1)

[Claims] 1. A real phase part of a quadrature signal obtained by quasi-coherent detection of a digital phase modulation signal including an uncertain carrier frequency deviation is received, and an input signal interferes with an input signal at a first time within one modulation code section. And a first filter for receiving the imaginary part of the orthogonal signal and performing equalization so that the input signal does not suffer intersymbol interference at a first time within one modulation code section. A second filter having the same characteristics as the first filter; and a third part that receives the real part of the orthogonal signal and equalizes the input signal so as not to undergo intersymbol interference at a second time within one modulation code section. And a fourth filter having the same characteristics as the third filter for receiving the imaginary part of the orthogonal signal and equalizing the input signal so as not to receive intersymbol interference at the second time within one modulation code section. Of the first filter and the output of the first filter, A first delay means for delaying an input signal by a time from a first time to the second time, and a time from the first time to the second time, receiving an output of the second filter. Second delays the input signal only
Delay means, a first multiplier that multiplies the output of the first delay means and the output of the fourth filter, and an output of the second delay means and the output of the third filter. A second multiplier and an output of the first multiplier from the second multiplier
2. A frequency discriminator comprising: a subtractor that subtracts the output of the multiplier of 1. and a sampler that receives the output of the subtractor and samples only a signal point indicating correct frequency error information with a modulation clock.