JPH047942A - Automatic frequency control system - Google Patents

Automatic frequency control system

Info

Publication number
JPH047942A
JPH047942A JP2109928A JP10992890A JPH047942A JP H047942 A JPH047942 A JP H047942A JP 2109928 A JP2109928 A JP 2109928A JP 10992890 A JP10992890 A JP 10992890A JP H047942 A JPH047942 A JP H047942A
Authority
JP
Japan
Prior art keywords
signal
output
filter
frequency
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2109928A
Other languages
Japanese (ja)
Other versions
JPH0722294B2 (en
Inventor
Naomasa Yoshida
尚正 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2109928A priority Critical patent/JPH0722294B2/en
Priority to CA002025135A priority patent/CA2025135C/en
Priority to AU62496/90A priority patent/AU628765B2/en
Priority to US07/582,147 priority patent/US5036296A/en
Publication of JPH047942A publication Critical patent/JPH047942A/en
Publication of JPH0722294B2 publication Critical patent/JPH0722294B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To attain automatic frequency control without pattern jitter by using a converging signal at two points at a different time in a modulation period so as to detect a frequency error and using its output so as to compensate the frequency fluctuation. CONSTITUTION:A sampler 2 receives a signal outputted from a complex number multiplier 1 and samples a signal by a clock being four times the modulation clock and outputs sample signals S101, S102, S103 at times T/4, 3T/4, T/2 for each modulation period T. The sample signal S103 is outputted externally as a reception signal whose frequency fluctuation is compensated and filters 3, 4, 5, 6 all have a same characteristic to apply equalization to the output from a sampler 2 so as to eliminate inter-code interference. Delay means 7, 8 give a delay of a time T/2 only to a signal outputted from the filters 3, 4. A signal representing the frequency fluctuation is obtained via multipliers 9, 10 and a subtractor 11. The frequency of the output from the subtractor 11 is controlled via the loop filter 12 and a voltage controlled oscillator VCO and the result is outputted to the complex number multiplier 1 as a compensation signal. Thus, the fluctuation of the carrier frequency without pattern jitter is compensated.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、位相偏移変調を用いたディジタル通信システ
ムにおいて、伝送路上で生じる搬送波周波数の不確定な
変動を受信器側で補償する自動周波数制御方式に関する
Detailed Description of the Invention (Industrial Application Field) The present invention is an automatic frequency system that compensates for uncertain carrier frequency fluctuations occurring on a transmission path on the receiver side in a digital communication system using phase shift keying. Regarding control method.

(従来の技術) 数GHzの高い搬送波周波数を用いるディジタル通信シ
ステムでは、伝送路上における周波数変換や無線局の移
動に伴うドツプラー効果等が原因となって搬送波周波数
に大きな変動が生じる。特に、低変調速度の通信システ
ムでは、最大周波数オフセットが変調周波数と同程度に
なる場合もある。一般に、この搬送波周波数の変動は、
受信器側での自動周波数制御によって補償される。
(Prior Art) In a digital communication system using a high carrier wave frequency of several GHz, large fluctuations occur in the carrier wave frequency due to frequency conversion on a transmission path, the Doppler effect due to the movement of a wireless station, and the like. Particularly in low modulation rate communication systems, the maximum frequency offset may be comparable to the modulation frequency. Generally, this carrier frequency variation is
Compensated by automatic frequency control at the receiver side.

従来の自動周波数制御方式としては、第2図に示すよう
なりロスプロダクト型周波数弁別器を用いた自動周波数
制街方式がある。第2図中で、結線は実信号、太線は直
交信号を示す。複素乗算器14は、PSK(位相偏移変
調)信号を準同期復調した直交信号を入力し、VCO<
電圧制御発振器)23から供給される補償信号により入
力する直交信号の周波数変動の補償を行う。サンプラ1
5は、複素乗算器14から出力される信号を受け、該信
号を外部から供給される変調クロックでサンプルし、変
調周期T毎に1/2変調周期の時刻T/2におけるサン
プルS(T/2)、すなわち信号点のサンプルを出力す
る。このサンプルS(T/2>は、周波数変動が補償さ
れた受信信号として外部に出力される。変調除去手段1
6は、サンプラ15から出力されるサンプルS(T/2
>を受け、逓倍操作により入力信号であるサンプルS(
T/2)の変調を除去する。遅延手段17は、変調除去
手段16から出力される信号の実部を受け、該実部に変
調周期Tの時間だけ遅延を与えて出力する。遅延手段1
8は、変調除去手段16から出力される信号の虚部を受
け、該虚部に変調周期Tの時間だけ遅延を与えて出力す
る。乗算器19は、遅延手段17の出力と変調除去手段
16から出力される信号の虚部とを乗算する。乗算器2
0は、遅延手段18の出力と変調除去手段16から出力
される信号の実部とを乗算する。減算器21は、乗算器
19の出力から乗算器20の出力を減算する。この減算
器21の出力が前記周波数変動を示す信号である。ルー
プフィルタ22は、この周波数変動信号を平均する。V
C023は、ループフィルタ22から出力される信号に
より出力信号の周波数が制御され、該出力信号を前記周
波数変動を補償する補償信号として複素乗算器14に出
力する。ここで、受信搬送波の周波数変動をΔf、PS
K信号の変調相数をM(Mは正の整数)とおくと、変調
除去手段16で変調を除去された信号r(t)は、 r (t)=exp (j 2πMΔft)と表される
。したがって、減算器21の出力d(nT)は、 d (nT)=s i n (2rMΔfT>(n=o
、  1.2.  ・・・) となる。上式より、引き込み可能な周波数変動の範囲1
Δf1は、 Δfl<fs/2M となる。ここで、fsは変調周波数で1/Tで表される
As a conventional automatic frequency control system, there is an automatic frequency control system using a loss product type frequency discriminator as shown in FIG. In FIG. 2, connections indicate real signals, and thick lines indicate orthogonal signals. The complex multiplier 14 inputs an orthogonal signal obtained by quasi-synchronously demodulating a PSK (phase shift keying) signal, and
A compensation signal supplied from the voltage controlled oscillator (voltage controlled oscillator) 23 compensates for frequency fluctuations of the input orthogonal signal. Sampler 1
5 receives the signal output from the complex multiplier 14, samples the signal using a modulation clock supplied from the outside, and samples S(T/2) at time T/2 of 1/2 modulation period every modulation period T. 2), that is, output samples of signal points. This sample S(T/2> is outputted to the outside as a received signal with frequency fluctuations compensated for. Modulation removal means 1
6 is the sample S(T/2
>, the input signal sample S(
T/2) modulation is removed. The delay means 17 receives the real part of the signal output from the modulation removal means 16, delays the real part by the time of the modulation period T, and outputs the delayed real part. Delay means 1
8 receives the imaginary part of the signal output from the modulation removal means 16, delays the imaginary part by the time of the modulation period T, and outputs the imaginary part. Multiplier 19 multiplies the output of delay means 17 and the imaginary part of the signal output from modulation removal means 16. Multiplier 2
0 multiplies the output of the delay means 18 and the real part of the signal output from the modulation removal means 16. Subtractor 21 subtracts the output of multiplier 20 from the output of multiplier 19. The output of this subtracter 21 is a signal indicating the frequency fluctuation. Loop filter 22 averages this frequency fluctuation signal. V
C023 has the frequency of the output signal controlled by the signal output from the loop filter 22, and outputs the output signal to the complex multiplier 14 as a compensation signal that compensates for the frequency fluctuation. Here, the frequency fluctuation of the received carrier wave is expressed as Δf, PS
Letting the number of modulation phases of the K signal be M (M is a positive integer), the signal r(t) from which modulation has been removed by the modulation removal means 16 is expressed as r (t) = exp (j 2πMΔft) . Therefore, the output d(nT) of the subtractor 21 is d(nT)=s i n (2rMΔfT>(n=o
, 1.2. ...) becomes. From the above formula, the range of frequency fluctuation that can be drawn in is 1.
Δf1 satisfies Δfl<fs/2M. Here, fs is a modulation frequency expressed as 1/T.

〈発明か解決しようとする課題) 以上に説明したように従来の自動周波数制御方式では、
周波数誤差を検出するために、受信信号の変調を逓倍操
作により除去する必要がある。その結果、変調相数が増
加するにしたがい周波数引き込み範囲が狭くなる。また
、低SN時には非線形損失が問題となってくる。
(Problem to be solved by the invention) As explained above, in the conventional automatic frequency control system,
In order to detect frequency errors, it is necessary to remove the modulation of the received signal by a multiplication operation. As a result, as the number of modulation phases increases, the frequency pull-in range becomes narrower. Furthermore, when the SN is low, nonlinear loss becomes a problem.

そこで本発明は、変調周期内の興なる時刻において、各
々別途等化した2点の収束信号を用いて周波数誤差を検
出し、その出力でVCOを制御して搬送波周波数変動を
補償することで、同期終了時のパターンジッタをなくし
、同時に広い周波数引き込み範囲を実現する自動周波数
制御方式を提供することを目的とする。
Therefore, the present invention detects frequency errors at different times in the modulation period using convergence signals at two points, each of which is equalized separately, and uses the output to control the VCO to compensate for carrier frequency fluctuations. The purpose of the present invention is to provide an automatic frequency control method that eliminates pattern jitter at the end of synchronization and at the same time realizes a wide frequency pull-in range.

(課題を解決するための手段) 本発明の自動周波数制御方式は、 搬送波周波数が不確定に変動する位相偏移変調信号を直
交周波数変換した信号または前記位相偏移変調信号を準
同期復調した直交信号を入力信号として入力し、外部か
ら供給される補償信号により前記入力信号の周波数変動
の補償を行う周波数変動補償手段と、 該周波数変動補償手段から出力される信号を受け、該信
号を外部から供給される変調クロ・ツクに同期したクロ
ックでサンプルし、変調周期毎に変調周期内の第1の時
刻と第2の時刻と1./2変変調期の時刻におけるサン
プルをそれぞれ第1のサンプル、第2のサンプルおよび
周波数変動を補償した受信信号として出力するサンプラ
と、該サンプラから出力される第1のサンプルの実部を
受け、該実部に対して符号間干渉をなくすように等化を
行う第1のフィルタと、 該第1のフィルタと同特性を有し、前記サンプラから出
力される第1のサンプルの虚部を受け、該虚部に対して
符号間干渉をなくすように等化を行う第2のフィルタと
、 前記サンプラから出力される第2のサンプルの実部を受
け、該実部に対して符号間干渉をなくすように等化を行
う第3のフィルタと、 該第3のフィルタと同特性を有し、前記サングラから出
力される第2のサンプルの虚部を受け、該虚部に対して
符号間干渉をなくすように等化を行う第4のフィルタと
、 前記第1のフィルタから出力される信号を受け、該信号
に前記第1の時刻から前記第2の時刻までの時間の遅延
を与える第1の遅延手段と。
(Means for Solving the Problems) The automatic frequency control method of the present invention provides a signal obtained by orthogonal frequency conversion of a phase shift keying signal whose carrier frequency fluctuates uncertainly, or a quadrature signal obtained by quasi-synchronously demodulating the phase shift keying signal. Frequency fluctuation compensating means receives a signal as an input signal and compensates for the frequency fluctuation of the input signal using a compensation signal supplied from the outside, and receives a signal output from the frequency fluctuation compensating means and receives the signal from the outside. Samples are performed using a clock synchronized with the supplied modulation clock, and the first and second times within the modulation cycle are sampled for each modulation cycle. a sampler that outputs samples at the time of the /2 modulation period as a first sample, a second sample, and a frequency fluctuation-compensated received signal, respectively; and receiving a real part of the first sample output from the sampler; a first filter that performs equalization on the real part so as to eliminate intersymbol interference; and a first filter that has the same characteristics as the first filter and receives the imaginary part of the first sample output from the sampler. , a second filter that performs equalization on the imaginary part so as to eliminate intersymbol interference; and a second filter that receives the real part of the second sample output from the sampler and equalizes the real part to eliminate intersymbol interference. a third filter that performs equalization to eliminate intersymbol interference; a fourth filter that performs equalization so as to eliminate the noise; and a first filter that receives the signal output from the first filter and applies a time delay to the signal from the first time to the second time. with delay means.

前記第2のフィルタから出力される信号を受け、該信号
に前記第1の時刻から前記第2の時刻までの時間の遅延
を与える第2の遅延手段と、前記第1の遅延手段から出
力される信号と前記第4のフィルタから出力される信号
とを乗算する第1の乗算器と、 前記第2の遅延手段から出力される信号と前記第3のフ
ィルタから出力される信号とを乗算する第2の乗算器と
、 前記第1の乗算器の出力と前記第2の乗算器の出力との
差を生成し、該差を前記周波数変動の信号として出力す
る減算器と、 該減算器から出力される前記周波数変動信号を受け、該
周波数変動信号を平均するループフィルタと、 該ループフィルタから出力される信号により出力信号の
周波数が制御され、該出力信号を前記周波数変動を補償
する前記補償信号として前記周波数変動補償手段に出力
する電圧制御発振器とを備える。
a second delay means that receives a signal output from the second filter and applies a time delay to the signal from the first time to the second time; a first multiplier for multiplying a signal output from the fourth filter by a signal output from the fourth filter; and a first multiplier for multiplying a signal output from the second delay means by a signal output from the third filter. a second multiplier; a subtracter that generates a difference between the output of the first multiplier and the output of the second multiplier and outputs the difference as a signal of the frequency fluctuation; and from the subtracter. a loop filter that receives the output frequency fluctuation signal and averages the frequency fluctuation signal; and a compensation circuit that controls the frequency of the output signal by the signal output from the loop filter and compensates for the frequency fluctuation of the output signal. and a voltage controlled oscillator that outputs a signal to the frequency fluctuation compensation means.

(実施例) 次に、本発明について図面を参照して説明する。(Example) Next, the present invention will be explained with reference to the drawings.

第1図は本発明の自動周波数制御方式の一実施例の構成
を示すブロック図である。本実施例においては、サンプ
ラ2に供給するタロツクとして変調クロックの4倍のク
ロックを用いると回路構成が容易になり、最も実用的で
あるから、サンプラ2に供給するクロックは変調クロッ
クの4倍のクロックとする。搬送波周波数が不確定に変
動するPSK(位相偏移変調)信号の周波数変動を補償
するために、複素乗算器1は、PSK信号を準同期復調
した直交信号を入力として、VCO(電圧制御発振器)
13から供給される補償信号でその周波数変動の補償を
行う、サンプラ2は、複素乗算器1から出力される信号
を受け、該信号を変調クロックの4倍のクロックでサン
プルし、変調周期T毎に1/4変調周期の時刻T/4と
、3/4変調周期の時83 T / 4と、1./2変
調周期の時刻T/2におけるサンプルS(T/4)10
1、S (3T/4)102、S (T/2)103を
出力する。サンプルS(T/2>103は、信号点のサ
ンプルとなり、周波数変動が補償された受信信号として
外部に出力される。フィルタ3は、サングラ2から出力
される1/4変調周期の時刻T/4のサンプルS(T/
4)101の実部Re[S (T/4 ) ]を受け、
該実部に対して符号間干渉をなくすように等化を行う。
FIG. 1 is a block diagram showing the configuration of an embodiment of the automatic frequency control system of the present invention. In this embodiment, if a clock that is four times the modulation clock is used as the tarok that is supplied to the sampler 2, the circuit configuration becomes easier and it is most practical. Clock. In order to compensate for frequency fluctuations of a PSK (phase shift keying) signal whose carrier frequency fluctuates uncertainly, the complex multiplier 1 inputs an orthogonal signal obtained by quasi-synchronously demodulating the PSK signal and converts it into a VCO (voltage controlled oscillator).
The sampler 2 receives the signal output from the complex multiplier 1, samples the signal at a clock four times the modulation clock, and performs compensation for the frequency fluctuation using the compensation signal supplied from the complex multiplier 1. At time T/4 of 1/4 modulation period, at time 83 T/4 of 3/4 modulation period, 1. Sample S(T/4)10 at time T/2 of /2 modulation period
1, S (3T/4) 102, and S (T/2) 103 are output. Sample S (T/2>103 is a signal point sample, and is outputted to the outside as a received signal with frequency fluctuations compensated for. Filter 3 uses time T/2 of 1/4 modulation period output from sunglasser 2. 4 sample S(T/
4) Receive the real part Re[S (T/4) ] of 101,
Equalization is performed on the real part to eliminate intersymbol interference.

フィルタ4は、フィルタ3と同特性を有し、サンプラ2
から出力される1/4変調周期の時刻T/4のサンプル
S(T/4)101の虚部I m [S (T/4 )
 ]を受け、該虚部に対して符号間干渉をなくすように
等化を行う。フィルタ5は、サンプラ2から出力される
3/4変調周期の時刻3T/4のサンプルS <3T/
4)102の実部Re [3(3T、”4)1を受け、
該実部に対して符号間干渉をなくすように等化を行う。
Filter 4 has the same characteristics as filter 3, and sampler 2
Imaginary part I m [S (T/4) of sample S (T/4) 101 at time T/4 of 1/4 modulation period output from
], and the imaginary part is equalized to eliminate intersymbol interference. The filter 5 receives the sample S<3T/ at time 3T/4 of the 3/4 modulation period output from the sampler 2.
4) Receive the real part Re of 102 [3(3T,”4)1,
Equalization is performed on the real part to eliminate intersymbol interference.

フィルタ6は、フィルタ5と同特性を有し、サンプラ2
から出力される3/4変調周期の時刻3T/4のサンプ
ルS (3T/4)102の虚部1 m [S (3T
/4 ) ]を受け、該虚部に対して符号間干渉をなく
すように等化を行う。遅延手段7はフィルタ3から出力
される信号を受け、該信号に1/2変調周期の時間T/
2だけ遅延を与える。遅延手段8はフィルタ4から出力
される信号を受け、該信号に1/2変調周期の時間T/
2だけ遅延を与える。乗算器9は、遅延手段7の出力と
フィルタ6の出力とを乗算する。乗算器10は、遅延手
段8の出力とフィルタ5の出力とを乗算する6減算器1
1は、乗算器9の出力から乗算器10の出力を減算する
。この減算器11の出力が前記周波数変動を示す信号で
ある。ループフィルタ12は、減算器11から出力され
る周波数変動信号を受け、該周波数変動信号を平均する
。VCO13は、ループフィルタ12から出力される信
号により出力信号の周波数が制御され、該出力信号を周
波数変動を補償する前記補償信号として複素乗算器1に
出力する。
Filter 6 has the same characteristics as filter 5, and sampler 2
The imaginary part 1 m [S (3T
/4) ], and equalizes the imaginary part so as to eliminate intersymbol interference. The delay means 7 receives the signal output from the filter 3, and applies a time T/2 of the 1/2 modulation period to the signal.
Gives a delay of 2. The delay means 8 receives the signal output from the filter 4, and applies a time T/2 of 1/2 modulation period to the signal.
Gives a delay of 2. Multiplier 9 multiplies the output of delay means 7 and the output of filter 6. The multiplier 10 includes a 6-subtractor 1 that multiplies the output of the delay means 8 and the output of the filter 5.
1 subtracts the output of multiplier 10 from the output of multiplier 9. The output of this subtracter 11 is a signal indicating the frequency fluctuation. The loop filter 12 receives the frequency fluctuation signal output from the subtracter 11 and averages the frequency fluctuation signal. The frequency of the output signal of the VCO 13 is controlled by the signal output from the loop filter 12, and outputs the output signal to the complex multiplier 1 as the compensation signal for compensating for frequency fluctuations.

第3図は搬送波周波数変動のないPSK信号を準同期復
調して一般に用いられる最適受信フィルタを通した後の
復調信号を示す図である。本図において、同一変調符号
を変調周期をTで表す。第4図は第1図の実施例におい
て準同期復調信号をフィルタ3または4で等化した後の
復調信号を示す図である。本図では、1/4変調周期の
時刻T/4で信号が等化されている。第5図は第1図の
実施例において準同期復調信号をフィルタ5または6で
等化した後の復調信号を示す図である。本図では、3T
/4変調信号の時刻3T/4で信号が等化されている6
時間Tでは変調による符号の変化は生じないから、時刻
T/4と時刻3T/4での変調符号は同一である。した
がって時刻T/4から時刻3T/4までの時間T/2で
生じた位相の変化は変調の影響を受けず、周波数変動だ
けに起因する。よって、クロスプロダクト型周波数弁別
器に、時刻T/4と時刻3T/4で各々等化した収束信
号を入力することで問波数詔差を横用できる。このよう
な方法で検出した周波数誤差に基づき、VC013を制
御し、搬送波周波数変動の補償を行うのが本発明の特徴
である。以上の説明に用いた第3図、第4図および第5
図では、2相または4相変胴信号を想定しているか、M
相変調信号においても同様の効果が得られることは言う
までもない。
FIG. 3 is a diagram showing a demodulated signal obtained by quasi-synchronously demodulating a PSK signal with no carrier frequency fluctuation and passing it through a generally used optimal reception filter. In this figure, the modulation period of the same modulation code is represented by T. FIG. 4 is a diagram showing a demodulated signal after the quasi-synchronous demodulated signal is equalized by filter 3 or 4 in the embodiment of FIG. In this figure, the signal is equalized at time T/4 of the 1/4 modulation period. FIG. 5 is a diagram showing a demodulated signal after the quasi-synchronous demodulated signal is equalized by filter 5 or 6 in the embodiment of FIG. In this diagram, 3T
The signal is equalized at time 3T/4 of the /4 modulated signal6
Since no change in code occurs due to modulation at time T, the modulation codes at time T/4 and time 3T/4 are the same. Therefore, the phase change that occurs during time T/2 from time T/4 to time 3T/4 is not affected by modulation and is caused only by frequency fluctuations. Therefore, by inputting the convergence signals equalized at time T/4 and time 3T/4 to the cross-product type frequency discriminator, the difference in frequency numbers can be used horizontally. A feature of the present invention is that the VC013 is controlled based on the frequency error detected by such a method to compensate for carrier frequency fluctuations. Figures 3, 4 and 5 used in the above explanation
In the diagram, whether a 2-phase or 4-phase variable barrel signal is assumed, or M
It goes without saying that similar effects can be obtained with phase modulation signals.

なお、第1図は、全ディジタル的に処理を行う自動周波
数制御方式の構成を示しているが、一部にアナログ処理
を取り入れることもできる。たとえば、複素乗算器1を
アナログ乗算器に置き換え、VC013にIP帯域のア
ナログVCOを用い、アナログ乗算器とサンプラ2との
間およびループフィルタ12とVC013との間に、各
々A/D変換器、D/A変換器をおく構成も当然考えら
れる。しかし、本質的には第1図と変わりない。
Although FIG. 1 shows the configuration of an automatic frequency control system that performs processing entirely digitally, it is also possible to partially incorporate analog processing. For example, the complex multiplier 1 is replaced with an analog multiplier, an IP band analog VCO is used as the VC013, and an A/D converter is installed between the analog multiplier and the sampler 2 and between the loop filter 12 and the VC013, respectively. Of course, a configuration in which a D/A converter is provided is also conceivable. However, it is essentially the same as Figure 1.

(発明の効果) 以上に説明しなように本発明では、変調周期内の異なる
時刻において、各々別途等化した2点の収束信号の位相
変化を観測することで、変調による符号変化に依存せず
周波数誤差を検出できる。
(Effects of the Invention) As described above, in the present invention, by observing the phase changes of convergent signals at two points that are separately equalized at different times within the modulation period, the dependence on the sign change due to modulation is eliminated. frequency error can be detected.

したかって、平均周波数誤差がほぼ零となる同期終了時
には、変調によるパターンジッタがなくなる。また、変
調除去手段を用いないから、広い周波数引き込み範囲を
実現でき、逓倍操作による非線形損失が回避できる等の
効果がある。
Therefore, at the end of synchronization when the average frequency error becomes almost zero, pattern jitter due to modulation disappears. Furthermore, since no modulation removal means is used, a wide frequency pull-in range can be achieved, and nonlinear losses due to multiplication operations can be avoided.

3.4.5.6・・・フ ・・・遅延手段、9,1 1.21・・・減算器、 13  23・ VCO3.4.5.6...F ...delay means, 9,1 1.21...Subtractor, 13 23・VCO

Claims (1)

【特許請求の範囲】 搬送波周波数が不確定に変動する位相偏移変調信号を直
交周波数変換した信号または前記位相偏移変調信号を準
同期復調した直交信号を入力信号として入力し、外部か
ら供給される補償信号により前記入力信号の周波数変動
の補償を行う周波数変動補償手段と、 該周波数変動補償手段から出力される信号を受け、該信
号を外部から供給される変調クロックに同期したクロッ
クでサンプルし、変調周期毎に変調周期内の第1の時刻
と第2の時刻と1/2変調周期の時刻におけるサンプル
をそれぞれ第1のサンプル、第2のサンプルおよび周波
数変動を補償した受信信号として出力するサンプラと、 該サンプラから出力される第1のサンプルの実部を受け
、該実部に対して符号間干渉をなくすように等化を行う
第1のフィルタと、 該第1のフィルタと同特性を有し、前記サンプラから出
力される第1のサンプルの虚部を受け、該虚部に対して
符号間干渉をなくすように等化を行う第2のフィルタと
、 前記サンプラから出力される第2のサンプルの実部を受
け、該実部に対して符号間干渉をなくすように等化を行
う第3のフィルタと、 該第3のフィルタと同特性を有し、前記サンプラから出
力される第2のサンプルの虚部を受け、該虚部に対して
符号間干渉をなくすように等化を行う第4のフィルタと
、 前記第1のフィルタから出力される信号を受け、該信号
に前記第1の時刻から前記第2の時刻までの時間の遅延
を与える第1の遅延手段と、 前記第2のフィルタから出力される信号を受け、該信号
に前記第1の時刻から前記第2の時刻までの時間の遅延
を与える第2の遅延手段と、 前記第1の遅延手段から出力される信号と前記第4のフ
ィルタから出力される信号とを乗算する第1の乗算器と
、 前記第2の遅延手段から出力される信号と前記第3のフ
ィルタから出力される信号とを乗算する第2の乗算器と
、 前記第1の乗算器の出力と前記第2の乗算器の出力との
差を生成し、該差を前記周波数変動の信号として出力す
る減算器と、 該減算器から出力される前記周波数変動信号を受け、該
周波数変動信号を平均するループフィルタと、 該ループフィルタから出力される信号により出力信号の
周波数が制御され、該出力信号を前記周波数変動を補償
する前記補償信号として前記周波数変動補償手段に出力
する電圧制御発振器とを備えることを特徴とする自動周
波数制御方式。
[Claims] A signal obtained by orthogonal frequency conversion of a phase shift keying signal whose carrier frequency fluctuates uncertainly or a quadrature signal obtained by quasi-synchronous demodulation of the phase shift keying signal is input as an input signal, and frequency fluctuation compensating means for compensating for frequency fluctuations of the input signal using a compensation signal; receiving a signal output from the frequency fluctuation compensating means; , outputs samples at a first time, a second time, and a time of 1/2 modulation period within the modulation period as the first sample, the second sample, and a frequency fluctuation-compensated received signal, respectively, for each modulation period. a sampler; a first filter that receives a real part of a first sample output from the sampler and performs equalization on the real part so as to eliminate intersymbol interference; and a first filter having the same characteristics as the first filter. a second filter that receives the imaginary part of the first sample output from the sampler and performs equalization on the imaginary part so as to eliminate intersymbol interference; a third filter that receives the real part of the sample of No. 2 and equalizes the real part so as to eliminate intersymbol interference; and a third filter that has the same characteristics as the third filter and is output from the sampler. a fourth filter that receives the imaginary part of the second sample and performs equalization on the imaginary part so as to eliminate intersymbol interference; and a fourth filter that receives the signal output from the first filter and applies the a first delay means for providing a time delay from the first time to the second time; a second delay means that provides a time delay until the time; a first multiplier that multiplies the signal output from the first delay means and the signal output from the fourth filter; a second multiplier that multiplies the signal output from the second delay means by the signal output from the third filter; and the output of the first multiplier and the second multiplier. a subtracter that generates a difference and outputs the difference as the frequency fluctuation signal; a loop filter that receives the frequency fluctuation signal output from the subtracter and averages the frequency fluctuation signal; and an output from the loop filter. an automatic frequency control system, comprising: a voltage controlled oscillator whose frequency of an output signal is controlled by a signal generated by the frequency fluctuation, and outputs the output signal to the frequency fluctuation compensating means as the compensation signal for compensating for the frequency fluctuation.
JP2109928A 1989-09-13 1990-04-25 Automatic frequency control method Expired - Fee Related JPH0722294B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2109928A JPH0722294B2 (en) 1990-04-25 1990-04-25 Automatic frequency control method
CA002025135A CA2025135C (en) 1989-09-13 1990-09-12 Frequency tracking circuit using samples equalized at different sampling instants of same clock period
AU62496/90A AU628765B2 (en) 1989-09-13 1990-09-13 Frequency tracking circuit using samples equalized at different sampling instants of same clock period
US07/582,147 US5036296A (en) 1989-09-13 1990-09-13 Frequency tracking circuit using samples equalized at different sampling instants of same clock period

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2109928A JPH0722294B2 (en) 1990-04-25 1990-04-25 Automatic frequency control method

Publications (2)

Publication Number Publication Date
JPH047942A true JPH047942A (en) 1992-01-13
JPH0722294B2 JPH0722294B2 (en) 1995-03-08

Family

ID=14522666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2109928A Expired - Fee Related JPH0722294B2 (en) 1989-09-13 1990-04-25 Automatic frequency control method

Country Status (1)

Country Link
JP (1) JPH0722294B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6674814B2 (en) 1999-07-07 2004-01-06 Mitsubishi Denki Kabushiki Kaisha Frequency error estimating apparatus and a frequency error estimating method
CN112748409A (en) * 2020-12-21 2021-05-04 中国航天科工集团八五一一研究所 FPGA-based interference signal compression storage method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6674814B2 (en) 1999-07-07 2004-01-06 Mitsubishi Denki Kabushiki Kaisha Frequency error estimating apparatus and a frequency error estimating method
CN112748409A (en) * 2020-12-21 2021-05-04 中国航天科工集团八五一一研究所 FPGA-based interference signal compression storage method
CN112748409B (en) * 2020-12-21 2024-02-13 中国航天科工集团八五一一研究所 FPGA-based interference signal compression storage method

Also Published As

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