JPH0642548B2 - Method of manufacturing semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a method of manufacturing an electrically rewritable nonvolatile semiconductor memory device.

(Prior Art) Conventionally, this type of non-volatile semiconductor memory device is, for example, a fourth semiconductor device.
It is configured as shown in the figure. In Fig. 4 (a)
The figure is a plan view of the pattern, the figure (b) is a sectional view taken along the line AA 'in the figure (a), and SG is a select transistor,
CT is a cell transistor (transistor for data storage)
Is shown. The select transistor SG includes N ⁺ type source / drain regions 12 and 13 formed on the main surface of the P-type semiconductor substrate 11 and these source / drain regions 12 and 13.
The gate electrode 16 is formed on the intervening channel region 14 via the gate insulating film 15. Further, the cell transistor CT has a first region on the N ⁺ type source / drain regions 17 and 18 formed on the main surface of the semiconductor substrate 11 and a channel region 19 between the source and drain regions 17 and 18.
The floating gate electrode 21 is formed via the gate insulating film 20 and the control gate electrode 23 is formed on the floating gate electrode 21 via the second gate insulating film 22. Above gate insulation film 20
Has a thin film region 20a for facilitating Fowler-Nordheim tunnel current flow during writing.
Electrons are injected into the floating gate electrode 21 via a. The gate electrode 16 of the select transistor SG and the floating gate electrode 21 of the cell transistor CT are formed of, for example, the same first polysilicon layer, and the control gate electrode 23 is formed of the second polysilicon layer.

However, in order to form the gate electrode 16 of the select transistor SG with the first polysilicon layer as described above, first, the first polysilicon layer is patterned to form the gate electrode 16 and the floating gate electrode 21. Then, the second gate insulating film 22 and the second polysilicon layer are sequentially formed, and the second polysilicon layer is patterned to form the control gate electrode 23. At this time, when patterning the second polysilicon layer, a mask shift easily occurs between the first polysilicon layer pattern (floating gate electrode 21) and the floating gate electrode 21 in the cell transistor CT and the control. In order to secure a sufficiently large coupling capacitance with the gate electrode 23, a margin for mask alignment must be provided, and the floating gate cannot be determined in a self-aligned manner. For this reason, the cell area increases and it is not suitable for miniaturization.
The same applies to the case where the select transistor SG is formed of the second polysilicon layer.

Floating gate electrode of the cell transistor CT
In order to form the control gate electrode 23 and the control gate electrode 23 in a self-aligned manner, after patterning the first polysilicon layer to pre-form only the gate electrode 16 of the select transistor SG, the gate electrode 16 is also insulated. A polysilicon layer of the same layer (second layer) as the control gate electrode 23 is formed through the film, and the second and first polysilicon layers are etched in the same pattern to form the cell transistor C.
There is also known a method in which the control gate electrode 23 of T and the floating gate electrode 21 are formed, and then the second polysilicon layer on the gate electrode 16 of the select transistor SG is removed by etching. The reason why the second polysilicon layer on the gate electrode 16 of the select transistor SG is removed in this way is that if it is left, it will be in a floating gate state, which may adversely affect the device characteristics. . However, when such a manufacturing method is used, when the second conductive layer is formed,
In order to form the cell transistor portion in a self-aligned manner, the first
The resist must be left in the portion where the second-layer polysilicon layer overlaps, and the resist must be formed inside the first-layer conductive layer in consideration of the mask shift. Moreover, in order to form the electrode of the cell transistor in a self-aligned manner,
In order to protect the pre-formed first conductive layer of the select transistor from being etched by the mask shift, it is necessary to cover the resist layer with a sufficiently large resist because it is necessary to provide a predetermined gap, and therefore, similar to the manufacturing method described above. There is a drawback that is not suitable for miniaturization.

(Problems to be Solved by the Invention) As described above, in the conventional semiconductor memory device manufacturing method, when the electrodes of the select transistor and the cell transistor are formed in a self-aligned manner, the conductive layer on the gate electrode of the select transistor floats. There is a drawback of being in a state. In addition, there is a drawback that the floating conductive layer of the select transistor cannot be removed without increasing the cell area.

The present invention has been made in view of the above circumstances,
The purpose thereof is that the conductive layer on the gate electrode of the select transistor may be in a floating state or the cell area may increase even though the select transistor and the cell transistor are formed in a self-aligned manner. An object of the present invention is to provide a manufacturing method of a semiconductor memory device which does not exist.

[Configuration of Invention] (Means and Actions for Solving Problems) That is, in the present invention, in order to achieve the above object, a first insulating film is formed on a semiconductor substrate, and the first insulating film is formed. First polysilicon layer (first conductive layer) on the insulating film
To form. Next, a second insulating film is formed on the polysilicon layer, the second insulating film and the first polysilicon layer are selectively removed to form a first opening, and then the whole surface is formed. A second polysilicon layer (second conductive layer) is formed.
Subsequently, the second polysilicon layer is selectively removed to form a second opening, and the second polysilicon layer and the second polysilicon layer are formed.
The insulating film and the first polysilicon layer are selectively removed in the same pattern in a self-aligned manner. And the third on the whole surface
Forming an insulating film, forming contact holes on the first and second polysilicon layers in the first and second openings, respectively, and forming a wiring layer on the third insulating film. The first polysilicon layer and the second polysilicon layer are connected to each other.

According to such a manufacturing method, since the first-layer polysilicon layer and the second-layer polysilicon layer are etched in the same pattern, it is not necessary to consider mask misalignment, resulting in an increase in pattern area. Instead, the floating gate electrode and the control gate electrode of the cell transistor can be formed in a self-aligned manner. Further, since the gate electrode of the select transistor and the second-layer polysilicon layer remaining on this gate electrode are connected to each other, the device characteristics due to the polysilicon layer on the gate electrode being in a floating state It is possible to prevent adverse effects.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. 3 (a) and 3 (b) respectively show a pattern plan view and a sectional configuration view of the memory cell portion (select transistor SG and cell transistor CT) of the semiconductor memory device, and FIG. The same reference numerals are given to the same components. The difference from the configuration of FIG. 4 is that, as shown in the figure, the silicon oxide film 22 ₁ / silicon nitride film 22 ₂ / on the gate electrode 16 of the select transistor SG.
It is that the silicon oxide film 22 ₃ 3-layer polycrystalline silicon layer 24 of the insulating film of the same second layer and the control gate electrode 23 of the cell transistor CT via structure consisting of is formed. The three-layer structure film is used as an insulating film between the floating gate electrode 21 and the control gate electrode 23 in the cell transistor CT. The polysilicon layer 24 is electrically connected to the gate electrode 16 so as not to be in a floating state during operation. This connection portion is provided at several places on the same word line, for example.

FIGS. 1 (a) to 1 (1) sequentially show a manufacturing process of a connecting portion between the gate electrode 16 and the polysilicon layer 24.
The pattern plan view of the figure is shown in FIG. The memory cell portion shown in FIG. 3 and the connection portion between the first polysilicon layer (gate electrode 16) and the second polysilicon layer 24 shown in FIGS. 1 and 2 are as follows. To be formed.

First, as shown in FIG. 3A, a field oxide film 25 for element isolation is formed on a semiconductor substrate 11, and impurity element ions are implanted into the element region isolated by the field oxide film 25 to form an N ⁺ -type The diffusion layer 17 is formed. Next, an insulating film (gate insulating films 15 and 20) is formed on the semiconductor substrate 11 in the element region, and the gate oxide film 20 in the thin film formation region (20a) on the diffusion layer 17 is selectively removed. After that, again the semiconductor substrate 11
The thin film region with a thickness of about 100Å by thermal oxidation of 20
a is formed.

Next, a first polysilicon layer 26 is deposited on the entire surface of the field oxide film 25 and the insulating film 20. Subsequently, this by performing thermal oxidation of the polysilicon layer 26 to form a silicon oxide film 22 ₁ on the surface, depositing an Si ₃ N ₄ film 22 ₂ on the silicon oxide film 22 _1.
Subsequently, a silicon oxide film 22 ₃ is formed on the Si ₃ N ₄ film 22 ₂ to form an ONO structure film of oxide film / nitride film / oxide film. This ONO structure film is used because the dielectric constant of the nitride film is higher than that of the oxide film (SiO ₂ film), and the first-layer polysilicon layer 26 and the second-layer polysilicon to be formed are composed of only the oxide film. This is because a large capacitance can be obtained with a small pattern area as compared with the case where a capacitance between the layers is obtained. The insulating film between the first polysilicon layer 26 and the second polysilicon layer is the first polysilicon layer 26.
In order to reduce the leakage of charges from the floating gate electrode 21 made of, and to improve the breakdown voltage between the first polysilicon layer 26 and the second polysilicon layer, a certain amount of film Thickness is required. Therefore, Si ₃
If the N ₄ film is used, a large capacity can be obtained with the same thickness as when only the SiO ₂ film is used. In the nonvolatile semiconductor memory device, a high potential is applied to the control gate electrode 23 made of the second polysilicon layer, and the potential of the floating gate electrode 21 is changed by capacitive coupling between the control gate electrode 23 and the floating gate electrode 21. Since electrons are injected into the floating gate electrode 21 from the thin oxide film portion (the thin film region 20a) by increasing the voltage, the larger the capacitance between the floating gate electrode 21 and the control gate electrode 23 is, the larger the potential of the floating gate electrode 21 becomes. This is preferable because the rise is large.

Next, in order to pattern the first-layer polysilicon layer 26, a photoresist 27 is applied on the entire surface and patterning is performed ((b) figure). Next, using the photoresist pattern 27 as a mask, the silicon oxide film 22 ₃ ,
The silicon nitride film 22 ₂ , the silicon oxide film 22 ₁ and the polysilicon layer 26 are removed to form an opening 26a ((c)).
Figure). In the memory cell portion, the inside of the broken line in FIG. 3 (a) is a portion to be removed. At this time, the polysilicon layer 26 of the peripheral circuit other than the memory cell portion is also patterned at the same time. Subsequently, the photoresist pattern 27 used as a mask for the etching is removed, the side wall of the polysilicon layer 26 is oxidized, and then the second polysilicon layer 28 is deposited (FIG. 3D). At this time, the above-mentioned second
Since the polysilicon layer 28 of the layer is formed, the polysilicon layer 28 of the peripheral circuit portion except the memory cell portion is etched and removed in the next step. At this time, in order to make contact between the first polysilicon layer 26 and the second polysilicon layer 28, a photoresist 29 is applied and patterned as shown in FIG. The second polysilicon layer is formed by using the photoresist pattern 29 as a mask.
Etch 28. As a result, a portion (opening 28) where the second polysilicon layer 28 is not present in the memory cell array.
a) is formed (Fig. (f)).

Next, the select transistor SG and the cell transistor C
In order to form T, a photoresist 30 is applied again on the entire surface and patterned (FIG. 3G). Using the photoresist pattern 30 as a mask, the second polysilicon layer 28 and the silicon oxide film 22 are formed. ₃ , silicon nitride film 2
2 ₂ , the silicon oxide film 22 ₁ and the first polysilicon layer 26 are selectively removed ((h) figure). At this time, the control gate electrode 23 of the cell transistor CT, the floating gate electrode 21, the second gate electrode (second polysilicon layer) 24 of the select transistor and the first
The gate electrode 16 is formed by the same resist pattern 30 in a self-aligned manner.

After that, an oxide film 31 is formed on the entire surface (Fig. (I)), and a photoresist 32 is applied on the oxide film 31 and patterned (Fig. (J)). Then, using the photoresist pattern 32 as a mask, a contact hole is formed. 33 ₁ and 33 ₂ are formed ((k) figure).

After that, an aluminum layer 34 is formed on the entire surface by vapor deposition, and the aluminum layer 34 is patterned to provide wiring. By the aluminum wiring 34, the first polysilicon layer 26 and the second polysilicon layer of the select transistor SG are formed.
28 is connected, and the first gate electrode 16 and the second gate electrode 24 of the select transistor SG are electrically connected.

Then, impurity ions are implanted using the control gate electrode 23 and the second gate electrode 24 as a mask to form the N ⁺ -type diffusion layers 12, 13, and 18 in a self-aligned manner.

According to such a manufacturing method, the floating gate electrode 21 and the control gate electrode 23 of the cell transistor CT can be formed in a self-aligning manner, and the select transistor SG can be formed.
Since the first gate electrode 16 and the second gate electrode 24 are electrically connected at the connection portion shown in FIGS. 1 and 2, the second polysilicon layer (second gate electrode 24 ) Does not float and it is not necessary to remove this polysilicon layer 24. Also, the cell transistor C
When the floating gate electrode 21 of T and the control gate electrode 23 are formed in a self-aligned manner, the gate electrode 16 of the select transistor SG is damaged due to damage caused by mask misalignment.
A second layer formed on the gate electrode 16 to protect the
It is not necessary to make the polysilicon layer of the first layer sufficiently large. Therefore, the pattern area can be reduced and miniaturization is possible.
Further, the gate electrode of the select transistor SG is formed of two polysilicon layers (first gate electrode 16 and second gate electrode 16).
Since it is formed by parallel connection of 24), the wiring resistance of the word line can be reduced to about 1/2 and the access speed can be increased.

In the above-described embodiment, the contact holes for connecting the first and second polysilicon layers are formed in the portions each having only one polysilicon layer. This is because the yield at the time of exposure is better when the holes are formed in a small number of areas. Although the polysilicon layer of the peripheral circuit is patterned at the same time when the opening 26a (FIG. 1 (c)) is formed, this may be performed in separate steps. For example, after removing the second-layer polysilicon layer 28 of the peripheral circuit, the first-layer polysilicon layer of the peripheral circuit may be patterned. In this case, the first polysilicon layer may be deposited, patterned, and then oxidized to form the Si ₃ N ₄ film. Furthermore,
The step of selectively removing the second-layer polysilicon layer 28 to form the second opening 28a is performed by forming the second-layer polysilicon layer 28 on the entire surface and then selecting the select transistor and the cell transistor. Alternatively, the second polysilicon layer 28, the second insulating film 22, and the first polysilicon layer 26 may be selectively removed in a self-aligned manner. Also,
Formation of N ⁺ -type diffusion layer 12, 13, 18 is a gate electrode 23 and 24 may be performed in a self-aligned manner as the mask, for example, a self-aligning manner N gate electrodes 23 and 24 as a mask ^- -type impurity layer Then, after patterning is performed by covering with a resist again, N type impurities are ion-implanted to form the N ⁺ type impurity layer away from the gate electrodes 23 and 24. By doing so, the breakdown voltage becomes high and a higher voltage can be applied, so that the efficiency of electron injection / emission programming can be improved.

Further, although the ONO structure film is used as the insulating film between the floating gate electrode 21 and the control gate electrode 23 of the cell transistor CT in the above embodiment, it goes without saying that one layer of silicon oxide film may be used. .

As described above, according to the present invention, although the select transistor and the cell transistor are formed in a self-aligned manner, the conductive layer on the gate electrode of the select transistor is in a floating state, A method for manufacturing a semiconductor memory device that does not increase the cell area can be obtained.

[Brief description of drawings]

1 to 3 are diagrams for explaining a method of manufacturing a semiconductor memory device according to an embodiment of the present invention, and FIG. 4 is a diagram for explaining a method of manufacturing a conventional semiconductor memory device. . SG ... Select transistor, CT ... Cell transistor, 11 ... Semiconductor substrate, 15, 20 ... First insulating film, 16, 21,
26 ... First polysilicon layer (first conductive layer), 22 ₁ , 2
2 ₂ , 22 ₃ ... Second insulating film, 26a ... First opening, 23, 24, 2
8 ... second polysilicon layer (second conductive layer), 28a ... second hole, 31 ... third insulating film, 33 _1, 33 ₂ ... contact hole 34 ... wiring layer.

Claims (6)

[Claims] 1. A method of manufacturing a semiconductor memory device, comprising: a memory cell including a select transistor and a cell transistor, wherein the cell transistor has a floating gate electrode; forming a first insulating film on a semiconductor substrate; A step of forming a first conductive layer on the first insulating film, a step of forming a second insulating film on the first conductive layer, and a step of forming a second conductive layer on the entire surface. , A step of selectively removing the second conductive layer to form an opening, and self-aligning the second conductive layer, the second insulating film, and the first conductive layer of the select transistor and the cell transistor. Selectively and selectively removing the third insulating film and the third insulating film formed on the entire surface of the third insulating film and the second insulating film located on the first conductive layer in the opening. First contact ho A step of forming a second contact hole in the third insulating film located on the second conductive layer, and a wiring layer formed on the third insulating film to form the first conductive film. And a step of connecting the second conductive layer to the second conductive layer. 2. A method of manufacturing a semiconductor memory device, comprising: a memory cell including a select transistor and a cell transistor, wherein the cell transistor has a floating gate electrode; and a step of forming a first insulating film on a semiconductor substrate. A step of forming a first conductive layer on the first insulating film, a step of forming a second insulating film on the first conductive layer, and a step of forming a second conductive layer on the entire surface. A step of selectively removing the second conductive layer, the second insulating film, and the first conductive layer of the select transistor and the cell transistor in a self-aligned manner, and selectively removing the second conductive layer. To form an opening, and a third insulating film is formed on the entire surface to form the third insulating film and the second insulating film located on the first conductive layer in the opening. First contact ho A step of forming a second contact hole in the third insulating film located on the second conductive layer, and a wiring layer formed on the third insulating film to form the first conductive film. And a step of connecting the second conductive layer to the second conductive layer. 3. A method of manufacturing a semiconductor memory device, comprising: a memory cell including a select transistor and a cell transistor, wherein the cell transistor has a floating gate electrode; forming a first insulating film on a semiconductor substrate; A step of forming a first conductive layer on the first insulating film, a step of selectively removing the first conductive layer to form a first opening, and a step of forming the first conductive layer on the first conductive layer. A step of forming a second insulating film, a step of forming a second conductive layer on the entire surface, a step of selectively removing the second conductive layer to form a second opening, The step of selectively removing the second conductive layer, the second insulating film, and the first conductive layer of the select transistor and the cell transistor in a self-aligned manner, and forming the third insulating film on the entire surface to form the first conductive layer. , The second in the second aperture A step of the conductive layer and the second conductive layer forming the respective contact holes, the third
Forming a wiring layer on the insulating film of the first conductive layer and the second conductive layer.
And a step of connecting the conductive layer with the conductive layer. 4. A method of manufacturing a semiconductor memory device, comprising: a memory cell including a select transistor and a cell transistor, wherein the cell transistor has a floating gate electrode; forming a first insulating film on a semiconductor substrate; A step of forming a first conductive layer on the first insulating film, a step of selectively removing the first conductive layer to form a first opening, and a step of forming the first conductive layer on the first conductive layer. Forming a second insulating film on the entire surface, forming a second conductive layer on the entire surface, the second conductive layer, the second insulating film and the first conductive layer of the select transistor and the cell transistor. And selectively removing the self-alignment
Selectively removing the conductive layer to form a second opening, and forming a third insulating film on the entire surface to form a second insulating film on the first conductive layer in the first and second openings. A step of forming contact holes on the second conductive layer, and
Forming a wiring layer on the insulating film of the first conductive layer and the second conductive layer.
And a step of connecting the conductive layer with the conductive layer. 5. A method of manufacturing a semiconductor memory device comprising a memory cell including a select transistor and a cell transistor, wherein the cell transistor has a floating gate electrode, and a step of forming a first insulating film on a semiconductor substrate, A step of forming a first conductive layer on the first insulating film, a step of forming a second insulating film on the first conductive layer, the second insulating film and the first conductive film. A step of selectively removing the layer to form a first opening; a step of forming a second conductive layer on the entire surface; and a step of forming the second conductive layer of the select transistor and the cell transistor,
Selectively removing the insulating film and the first conductive layer in a self-alignment manner, a step of selectively removing the second conductive layer to form a second opening, and a third surface over the entire surface. And forming contact holes on the first conductive layer and the second conductive layer in the first and second openings, and wiring on the third insulating film. And a step of forming a layer to connect the first conductive layer and the second conductive layer to each other. 6. A method of manufacturing a semiconductor memory device, comprising: a memory cell including a select transistor and a cell transistor, wherein the cell transistor has a floating gate electrode; and a step of forming a first insulating film on a semiconductor substrate, A step of forming a first conductive layer on the first insulating film, a step of forming a second insulating film on the first conductive layer, the second insulating film and the first conductive film. A step of selectively removing the layer to form a first opening, a step of forming a second conductive layer on the entire surface, and a step of selectively removing the second conductive layer to form a second opening And a step of selectively removing the second conductive layer, the second insulating film, and the first conductive layer of the select transistor and the cell transistor in a self-aligned manner, and a third insulating layer over the entire surface. The film is formed and the first and second Forming a contact hole on each of the first conductive layer and the second conductive layer in the opening; and forming a wiring layer on the third insulating film to form the first conductive layer and the first conductive layer. And a step of connecting to the second conductive layer.