JPH0642388Y2 - Multi-chip package - Google Patents
Multi-chip packageInfo
- Publication number
- JPH0642388Y2 JPH0642388Y2 JP1988034683U JP3468388U JPH0642388Y2 JP H0642388 Y2 JPH0642388 Y2 JP H0642388Y2 JP 1988034683 U JP1988034683 U JP 1988034683U JP 3468388 U JP3468388 U JP 3468388U JP H0642388 Y2 JPH0642388 Y2 JP H0642388Y2
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- flange
- chip package
- cooling plate
- cooling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
Description
【考案の詳細な説明】 〔産業上の利用分野〕 本考案は、マルチチップ・パッケージに関し、特に大型
コンピュータや高周波通信装置などの高速な信号処理を
要求される電子機器に使用するのに適するLSIパッケー
ジ等のマルチチップ・パッケージに関する。[Detailed Description of the Invention] [Industrial field of application] The present invention relates to a multi-chip package, and particularly to an LSI suitable for use in electronic devices that require high-speed signal processing, such as large computers and high-frequency communication devices. Related to multi-chip packages such as packages.
従来、この種のLSIパッケージは、装置の処理能力の高
速化を達成するため、LSIチップの処理能力の高速化、
およびLSIチップ間相互の配線距離の短縮のためのLSIチ
ップの実装密度の増大と、それに伴う配線の高密度化に
たいする努力がなされて来た。Conventionally, this type of LSI package has been designed to achieve high-speed processing of an LSI chip in order to achieve high-speed processing of the device.
In addition, efforts have been made to increase the packaging density of LSI chips in order to shorten the wiring distance between LSI chips and to increase the wiring density accordingly.
一方、LSIチップ、とくに論理処理用LSIの処理能力の高
速化のために、論理回路形式にECL（エミッタ・カップ
ルド・ロジック）もしくは、CML（カレント・モード・
ロジック）を用いることが広く行なわれている。これら
の高速論理処理用LSIは消費電力が大きい上に、前記の
理由で複数のLSIが高密度に実装されているので、この
ようなマルチチップ・パッケージは第２図に示すように
液冷方式が主流となりつつある。また、マルチチップ・
パッケージを構成する配線基板にはセラミックを基材と
したものが実用化されている。たとえばこのマルチチッ
プ・パッケージは（日経エレクトロニクス1985年６月17
日号P243〜P266）に開示されている。第２図においては
配線基板にはフランジと冷却板とが取付けられ、冷却板
と配線基板との間には伝熱材が充填されて間接液冷方式
によるマルチチップ・パッケージが構成されている。On the other hand, in order to speed up the processing capacity of LSI chips, especially LSIs for logic processing, the logic circuit format is ECL (emitter coupled logic) or CML (current mode
Logic) is widely used. Since these high-speed logic processing LSIs consume a large amount of power and a plurality of LSIs are mounted at high density for the above-mentioned reason, such a multi-chip package has a liquid cooling system as shown in FIG. Is becoming mainstream. In addition, multi-chip
As a wiring board that constitutes a package, a ceramic board has been put into practical use. For example, this multi-chip package (Nikkei Electronics June 17, 1985
It is disclosed in the Japanese issue P243-P266). In FIG. 2, a flange and a cooling plate are attached to the wiring board, and a heat transfer material is filled between the cooling plate and the wiring board to form a multichip package by an indirect liquid cooling system.
さらに、実装の高密度化のためには配線基板は大きいほ
うが有利であり、もっとも望ましいのは１つの装置が１
枚の配線基板で成り立っていることである。（参照：日
経エレクトロニクス1985年12月30日号P59〜P62） 〔考案が解決しようとする課題〕 しかし、上述したマルチチップ・パッケージは配線基板
が大型化すると、この配線基板に取付ける部品と配線基
板との熱膨張の差によるひずみが無視出来なくなってく
る。とくに配線基板の表面を保護するための封止材は、
配線基板の線に沿って配線基板の表面と隙間なく接着し
ている必要があるため、配線基板と封止材との熱膨張率
の違いが大きいと封止効果が損なわれ、あるいは配線基
板が破損してしまう。一例として、封止材をステンレス
鋼、配線基板を１辺20センチメートルのアルミナとして
摂氏０度から摂氏300度まで変化したときの熱膨張の差
を計算してみると、ステンレス鋼の線膨張率は1.64×10
-5／℃、アルミナの線膨張率を7.6×10-6／℃であるか
ら20cm×（16.4−7.6）×10-6×300＝0.0528cmつまり約
0.5mmとなり、無視できない値であることが分かる。Further, it is advantageous that the wiring board is large in order to increase the packaging density, and the most desirable one is one device.
It consists of a single wiring board. (Reference: December 30, 1985, P59-P62, Nikkei Electronics) [Problems to be solved by the invention] However, when the wiring board of the above-mentioned multi-chip package becomes large, the components to be mounted on this wiring board and the wiring board The strain due to the difference in thermal expansion between and cannot be ignored. In particular, the sealing material for protecting the surface of the wiring board is
Since it is necessary to adhere to the surface of the wiring board along the lines of the wiring board without any gaps, if the difference in the coefficient of thermal expansion between the wiring board and the sealing material is large, the sealing effect is impaired, or the wiring board is It will be damaged. As an example, let us calculate the difference in thermal expansion when the sealing material is made of stainless steel and the wiring board is made of alumina with a side of 20 cm, and the coefficient of thermal expansion changes from 0 degrees Celsius to 300 degrees Celsius. Is 1.64 x 10
-5 / ℃, the coefficient of linear expansion of alumina is 7.6 × 10 -6 / ℃, so 20 cm × (16.4-7.6) × 10 -6 × 300 = 0.0528 cm or about
It is 0.5 mm, which is a value that cannot be ignored.
本考案のマルチチップ・パッケージは封止材を複数の部
分に分割するとともに、封止材のそれぞれの部分をゴム
もしくは金属ベローズなどの弾性のある部材で相互に接
続して封止効果を損なわずに封止材の熱膨張差を吸収す
ることを特徴としている。The multi-chip package of the present invention divides the encapsulant into a plurality of parts and connects each part of the encapsulant to each other with elastic members such as rubber or metal bellows without impairing the encapsulating effect. It is characterized by absorbing the difference in thermal expansion of the sealing material.
〔実施例〕 次に本考案の実施例について図面を参照して詳細に説明
する。[Embodiment] Next, an embodiment of the present invention will be described in detail with reference to the drawings.
第１図（Ａ），（Ｂ）は、本考案の一実施例を示す。第
１図（Ａ）において、本実施例は１辺の長さが15cmの正
方形の配線基板10に裏面に入出力ピン11が、表面にLSI
チップ12がそれぞれ取付けられている。そしてこの基板
の周囲にはフランジ20が４分割されて取付けられてい
て、このフランジのそれぞれの部分はゴム継手13で互い
に繋ぎ合わされている。1 (A) and (B) show an embodiment of the present invention. In FIG. 1 (A), the present embodiment has a square wiring board 10 having a side length of 15 cm, an input / output pin 11 on the back surface and an LSI on the front surface
Chips 12 are attached to each. A flange 20 is divided into four parts and attached around the periphery of the substrate, and respective parts of the flange are connected to each other by a rubber joint 13.
さらに、フランジ20の上面にはこれも４つに分割された
冷却板21が貼り付けられ、配線基板10,フランジ20,冷却
板21で封止容器が形成されている。この封止容器には、
シリコン樹脂系の伝熱材14が充填されており、冷却板の
もたらす低温はこの伝熱材を通じてLSIチップ12に伝え
られる。冷却板の内部は第１図（Ｂ）に示すように冷却
液の流路22が設けられていて、低温の冷却液がこの中を
流れている。そして冷却板が分割されているので、それ
ぞれの冷却板の流路を接続するためにベローズ25が用い
られている。Further, a cooling plate 21 which is also divided into four parts is attached to the upper surface of the flange 20, and the wiring board 10, the flange 20 and the cooling plate 21 form a sealed container. In this sealed container,
A silicon resin-based heat transfer material 14 is filled, and the low temperature generated by the cooling plate is transmitted to the LSI chip 12 through this heat transfer material. As shown in FIG. 1 (B), a cooling liquid flow path 22 is provided inside the cooling plate, and a low-temperature cooling liquid flows therein. Since the cooling plates are divided, the bellows 25 are used to connect the flow paths of the respective cooling plates.
冷却板各部の相互接続はベローズだけではなく、ゴム継
手等の部材も用いて伝熱材14の漏洩や封止効果の低下が
起こらないようになっている。Not only the bellows but also a member such as a rubber joint is used for interconnecting each part of the cooling plate so that leakage of the heat transfer material 14 and deterioration of the sealing effect do not occur.
以上説明したように、本考案には配線基板が大型になっ
ても封止材を取付けることができるという効果がある。As described above, the present invention has an effect that the sealing material can be attached even if the wiring board becomes large in size.
第１図（Ａ）および（Ｂ）は、本考案の一実施例を示す
縦断面図および斜視図、第２図は、従来のパッケージを
示す斜視図である。 10,30……配線基板、11……入出力ピン、12,32……LSI
チップ、13……ゴム継手、14……伝熱材、20,40……フ
ランジ、21,41……冷却板、22……冷却液流路、23,43…
…冷却液入り口、24,44……冷却液出口、25……ベロー
ズ。1 (A) and 1 (B) are a longitudinal sectional view and a perspective view showing an embodiment of the present invention, and FIG. 2 is a perspective view showing a conventional package. 10,30 …… Wiring board, 11 …… I / O pins, 12,32 …… LSI
Tip, 13 …… Rubber joint, 14 …… Heat transfer material, 20,40 …… Flange, 21,41 …… Cooling plate, 22 …… Coolant flow path, 23,43…
… Coolant inlet, 24,44 …… Coolant outlet, 25 …… Bellows.
Claims (1)
ミックを基材とする配線基板と、配線基板の周囲に設け
られたフランジと、該フランジと周囲が接し前記配線基
板に対向して配置されている冷却板とこれらの部材によ
って構成される空隙に充填された伝熱材によって前記配
線基板もしくは配線基板に搭載されたLSIチップを冷却
する間接液冷方式のマルチチップ・パッケージにおい
て、前記フランジおよび冷却板がそれぞれ複数の部分に
分割され各部分は弾性を有する部材で相互に接続されて
成るマルチチップ・パッケージ。1. A wiring board having a length of one side exceeding 10 cm and using ceramic as a base material, a flange provided around the wiring board, and the flange and the circumference being in contact with each other and facing the wiring board. In an indirect liquid cooling type multi-chip package for cooling the wiring board or an LSI chip mounted on the wiring board by a heat transfer material filled in a space formed by a cooling plate and these members, A multi-chip package in which a flange and a cooling plate are each divided into a plurality of parts, and each part is connected to each other by an elastic member.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988034683U JPH0642388Y2 (en) | 1988-03-15 | 1988-03-15 | Multi-chip package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988034683U JPH0642388Y2 (en) | 1988-03-15 | 1988-03-15 | Multi-chip package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01137598U JPH01137598U (en) | 1989-09-20 |
| JPH0642388Y2 true JPH0642388Y2 (en) | 1994-11-02 |
Family
ID=31261374
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988034683U Expired - Lifetime JPH0642388Y2 (en) | 1988-03-15 | 1988-03-15 | Multi-chip package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0642388Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017158226A (en) * | 2016-02-29 | 2017-09-07 | 株式会社安川電機 | Linear motor |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110232887A1 (en) * | 2010-03-29 | 2011-09-29 | Zaffetti Mark A | Cold plate with integral structural fluid port |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59200495A (en) * | 1983-04-27 | 1984-11-13 | 株式会社日立製作所 | Multichip module |
-
1988
- 1988-03-15 JP JP1988034683U patent/JPH0642388Y2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017158226A (en) * | 2016-02-29 | 2017-09-07 | 株式会社安川電機 | Linear motor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01137598U (en) | 1989-09-20 |
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