JPH0642320B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention includes a sense amplifier for detecting the content of data read from a memory cell, and generates a reference potential used in this sense amplifier. The present invention relates to a semiconductor memory device having improved means.

(Prior Art) Conventionally, a semiconductor memory device, for example, a floating gate type MOSFE
EPROM (Erasable and TROM) using T as a memory cell
Programmable ROM) is configured as shown in the circuit diagram of FIG. In FIG. 9, MC ₁₁ , MC ₁₂ ,
, MC _1n , ..., MC _mn are floating gate type MOS
Memory cell consisting of FET, DC is floating gate type MOS
Dummy cells composed of FETs, WL ₁ , WL ₂ , ..., WL
_m are row lines, BL ₁ , BL ₂ , ..., BL _n are column lines, DBL is a dummy column line, 11 is a decoder, 12 is a column decoder, and BT ₁ , BT ₂ , ..., BT _n are column gates. MOSFET and DBT are column gate MOSF
It is equivalent to ET and the gate is supplied with the power supply voltage _Vcc ,
MOSFET which is always in a conductive state, 13 is an N-channel MOSFET, QM _{1 to} QM ₆ and a P-channel MOS
A first load circuit composed of an FET QM ₇ , 14 is an N-channel MOSFET QD _{1 to} QD ₆ and a P-channel MO.
A second load circuit composed of the SFET QD ₇ , 15 is a sense amplifier, and 16 is an output buffer. It should be noted that all MOSFETs that do not specify a channel are N-channel MOSFETs.

In the EPROM having such a configuration, the reference reference potential Vref generated by the second load circuit 14 and the row decoder 11 and the column decoder 1 based on the data of the dummy cell DC.
The sense amplifier 15 compares the potential Vin generated by the first load circuit 13 based on the data read from the memory cell MC selected according to the output of 2 with the selected memory cell MC. The stored data is detected, and the sense amplifier 15 supplies the read data to the output buffer 16.

For the dummy cell DC, a MOSFET equivalent to the memory cell MC on the main body side is used, and the dummy column line DBL is used.
Also, the same one as the column line BL is used.

In each memory cell of such an EPROM, data is programmed by selectively injecting electrons into the floating gate. That is, when electrons are injected to the floating gate is sufficiently higher voltage than the normal power supply voltage V _cc to the column line and row line selected by the row decoder 11 and column decoder 12, for example 12.5V~21V of It is performed by applying a voltage. When such a high voltage is applied, impact ionization occurs in the channel region near the drain of the memory cell located at the intersection of the selected column line and row line, which is caused by this. Electrons, and electrons of the right pair are injected into the floating gate. The threshold voltage of the memory cell into which electrons have been injected is sufficiently higher than that of the memory cell into which electrons have not been injected. That is, the memory cell in which electrons are injected into the floating gate maintains the off state even when the control gate, that is, the row line is supplied with the signal (power supply voltage V _cc ) at the level "1", and the one in which the electrons are not injected is on. It becomes a state. On the other hand, since electrons are not injected into the dummy cell DC, it becomes equivalent to a memory cell on the main body side where electrons are not injected, and there is no difference between the potentials Vref and Vin as it is. Therefore, the load MOSF in the second load circuit 14
The channel width WD ₇ of ET QD _7, the first load circuit 13
Channel width WM ₇ of MOSFET QM ₇ for load in
The current supply capacity of the MOSFET QD ₇ is set to be larger than that of the MOSFET QM ₇ by increasing the value. As a result, even when a memory cell into which electrons have not been injected is selected, a predetermined potential difference is generated between the potentials Vref and Vin. Also, when the memory cell in which electrons are injected is selected, the potential Vin is set to the threshold voltage of only minus potential of MOSFET QM ₇ for the load from the supply voltage V _cc. In the future, a memory cell in which electrons are injected is a memory cell that stores “0”,
The memory cells that are not implanted will be described as "1" memory cells.

By the way, in the above EPROM, a sense amplifier is used.
The output buffer 16 receives the data read in 15, and the data is output from the output buffer 16 to the outside. Since the output buffer 16 needs to charge and discharge a large external load capacitance, noise is generated in the power supply when data is output from the output buffer 16. The value of the power supply voltage _Vcc fluctuates due to this noise. At this time, as described above, the load MOSFET QD for the dummy cell side
₇ and the MOSFET QM ₇ for load on the memory cell side have different current supply capacities, a difference occurs in the response to the fluctuation of the power supply voltage, and the magnitude relationship between the potential Vin and the potential Vref is reversed. , The sense amplifier 15 may output incorrect data. Therefore, it is necessary to avoid driving of the output buffer which causes the malfunction of the sense amplifier as much as possible.

However, in the EPROM of FIG. 9, the row lines are switched,
When the data of the memory cell of "1" storage of the different row line next to the memory cell of "1" storage is continuously read, the memory cell of the non-selected destination is turned off, but the newly selected memory cell is selected. Does not turn on sufficiently at the selected initial stage. That is, the threshold voltage of the memory cell having the floating gate structure as described above is about 2 V, and the memory cell is momentarily turned off when the row line is switched. For this reason, the column line on the Vin side is charged when the row line is switched, and the potential V
in temporarily rises. By the way, since the dummy cell DC is set to be always on by the power supply voltage _Vcc , the reference potential Vref is always constant as shown in the waveform diagram of FIG. On the other hand, when the data of the memory cell storing "1" is continuously read as described above, the potential Vin temporarily rises when the memory cell is switched as shown in FIG. Then, as shown in the figure, the potential Vin crosses the reference potential Vref,
The sense amplifier 15 temporarily outputs different data, and the output data from the output buffer 16 changes to "1" level, "0" level, "1" level in a short period. Such a change in the output data causes the power supply noise as described above. Moreover, when the output data of the output buffer 16 changes from the “0” level to the “1” level, the output buffer 16 is charged in the “1” level direction while discharging to the “0” level. Is done. At this time,
MOS (not shown) discharging to "0" level
The FET is suddenly turned off and the discharge current becomes 0 in a short time.
become. Therefore, the rate of change of the current with time di / dt
Becomes nearly infinity, and the inductance component existing in the wiring may cause a large fluctuation in the ground voltage, resulting in malfunction.

In order to prevent such malfunction due to fluctuations in the ground voltage, the conventional EPROM having a configuration as shown in FIG.
Is being considered.

The EPROM of FIG. 11 is provided with the same number of dummy cells DC _{1 to} DC _m as the row lines, the drain of each dummy cell is connected in parallel to the dummy column line DBL, and each dummy cell D is connected.
The control gates of C _{1 to} DC _m are connected to _m row lines WL _{1 to} WL _m.
The corresponding one is connected respectively.

With such a configuration, since each dummy cell is also controlled by the signal of the row line, the row line is switched to switch the data of the memory cell of the "1" memory next to the memory cell of the "1" memory next to the memory cell of the "1" memory. In the case of continuous reading, the dummy column line DBL is also charged by the load circuit at the time of switching the row line similarly to the column line BL, and as shown in the waveform diagram of FIG. 12, the reference potential Vref and the potential Vin (“1 It increases with the increase of "level". In this case, the potential Vin does not cross the reference potential Vref, the output data from the output buffer 16 does not change, and the ground voltage does not change.

However, since the potentials Vin and Vref rise due to the charging action at the time of switching the row lines, they depend on the current supply capability of the load MOSFETs QM ₇ and QD ₇ in the load circuits 13 and 14. That is, as described above, the MOSFET Q
Since D ₇ has a larger current supply capacity,
As shown in FIG. 2, the potential Vref rises to a level considerably higher than the potential Vin (“1” level). Therefore, as shown in the waveform diagram of FIG. 13, the potential Vref is always constant for the read time when the row line is switched and the data of the memory cell of "0" storage is read from the memory cell of "1" storage. It will be delayed by the time T1 compared to the time.

(Problems to be Solved by the Invention) As described above, in the conventional semiconductor memory device, noise is generated in the power supply due to the fluctuation of the input potential during the transition period when the selection of the row line is switched, and this noise causes malfunction. In the conventional different semiconductor memory device in which such a defect is improved, the data read during the transition period when the selection of the row line is switched because the change in the reference potential is larger than the change in the input potential. It has the drawback of being slow.

The present invention has been made in consideration of the above circumstances, and an object thereof is to prevent noise from being generated in a power supply even during a transition period in which selection of row lines is switched and to improve a data reading speed. An object of the present invention is to provide a semiconductor memory device that can be used.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor memory device of the present invention includes: a row line; a memory cell selected by the row line; a column line for receiving data from the memory cell; A first load circuit connected to the column line, a first dummy cell selected by the row line, a dummy column line to which the first dummy cell is connected, and a second dummy cell connected to the dummy column line. Load circuit, a second dummy cell connected to the dummy column line and having a gate supplied with a predetermined potential, and a sense amplifier for detecting stored data in the memory cell based on a potential difference between the column line and the dummy column line. And is provided.

A semiconductor memory device of the present invention includes a row line, a memory cell selected by the row line, a column line for receiving data from the memory cell, and a first load circuit connected to the column line. , A first dummy cell selected by the row line, and a dummy column line to which the first dummy cell is connected,
A second load circuit connected to the dummy column line, a pulse signal generation circuit for detecting a change in address input and generating a pulse signal, and a pulse signal generation circuit connected to the dummy column line and generated by the pulse signal generation circuit. It is characterized by comprising a second dummy cell whose conduction is controlled by a pulse signal, and a sense amplifier which detects stored data in the memory cell based on a potential difference between the column line and the dummy column line.

Further, the semiconductor memory device of the present invention includes a row line, a memory cell selected by the row line, a column line for receiving data from the memory cell, and a first load circuit connected to the column line. A dummy cell selected by the row line, a dummy column line to which the dummy cell is connected, a pulse signal generation circuit that detects a change in address input and generates a pulse signal, and the pulse signal connected to the dummy column line A second load circuit whose current supply capability to the dummy column line is controlled according to the pulse signal generated by the generation circuit, and the stored data of the memory cell is detected based on the potential difference between the column line and the dummy column line. And a sense amplifier that operates.

(Operation) According to the present invention, the current flowing through the dummy column line at the time of switching the row line is achieved by connecting the second dummy cell, which is controlled to be in the ON state at all times or during the transition period at the time of switching the row line, to the dummy column line. By changing the amount, the rise of the reference potential at the time of switching the row line is suppressed.

Further, according to the present invention, the current supply capability for the dummy column line in the second load circuit is changed during the transition period when the row line is switched, so that the rise of the reference potential is suppressed when the row line is switched.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing the entire configuration of a semiconductor memory device according to the present invention when implemented in an EPROM using a floating gate type MOSFET as a memory cell as in the conventional case. In FIG. 1, MC ₁₁ , MC ₁₂ , ..., MC _1n ,
, MC _mn are memory cells each composed of a floating gate type MOSFET, DC ₁ , DC ₂ , ..., DC _m are dummy cells (first dummy cells) each composed of a floating gate type MOSFET, and DC _{m + 1} is a floating gate type MOSFET.
A dummy cell (second dummy cell), WL ₁ , W
L ₂ , ..., WL _n are row lines, BL ₁ , BL ₂ ,
, BL _n are column lines, DBL is a dummy column line, 11 is a decoder, 12 is a column decoder, BT ₁ , BT ₂ , ..., BT
_n is a column gate MOSFET, DBT is equivalent to a column gate MOSFET, and the power supply voltage V is applied to the gate.
MOSFET which is supplied with _{cc and} is always in a conductive state,
13 is a first load circuit composed of N-channel MOSFETs QM _{1 to} QM ₆ and P-channel MOSFET QM ₇ ,
Reference numeral 14 is a second load circuit including N-channel MOSFETs QD _{1 to} QD ₆ and P-channel MOSFET QD ₇ ′, 15 is a sense amplifier, and 16 is an output buffer. In the case of this embodiment as well, all MOSFETs whose channels are not specified are N-channel MOSFETs.

The drains of the dummy cells DC ₁ , DC ₂ , ..., DC _m are connected in parallel to the dummy column line DBL,
Further, each control gate is connected to a corresponding _{one of the} row lines WL _{1 to} WL _m . Further, the drain of the dummy cell DC _{m + 1} is connected to the dummy column line DBL, and the power supply voltage V _cc is constantly supplied to its control gate.

Each of the first and second load circuits 13 and 14 has the same structure as the conventional one. For example, in the first load circuit 13,
The MOSFET QM ₁ is provided between the common connection point of the column gate MOSFETs BT _{1 to} BT _n and the node of the potential Vin.
Is inserted between the source and drain. This MOSF
ET QM ₁ has two MOSFET QMs at the gate
₂ , QM ₃ and is supplied with a DC bias potential V ₁ lower than the power supply voltage V _cc . The source of the MOSFET QM ₄ is connected between the common connection point of the column gate MOSFETs BT _{1 to} BT _n and the power supply voltage V _cc.
The space between the drains is inserted. This MOSFET QM
The gate of 4 has two MOSFETs QM ₅ and QM ₆
And a DC bias potential V ₂ having a value lower than the DC bias potential V ₁ is supplied. The value of this DC bias potential V ₂ is an N channel in which the substrate bias effect is taken into consideration in the column line potential when a memory cell whose threshold voltage is set low is selected and a predetermined current flows between its source and drain. It is set to a value including the threshold voltage of the MOSFET. Further, the node of the potential Vin and the power supply voltage V
A source-drain portion of a P-channel MOSFET QM ₇ is inserted between _cc and _cc . This MOSFET
The gate of QM ₇ is connected to its drain side, that is, the node of potential Vin. The MOSFET QM ₄ provided in the load circuit 13 is for initial charging which quickly charges the selected column line BL when the selected column line BL is charged from the initial 0V.
No. ₄ is turned off when the column line potential becomes equal to or higher than the column line potential when a predetermined current flows through the memory cell. The second load circuit 14 is also configured in the same manner, but the dummy column line DBL is always supplied with the power supply voltage V _{cc at} its gate and connected to the dummy cell DC _{m + 1 which} is always turned on. Therefore, the dummy column line DBL is connected to the dummy cell DC _{m + 1} and one row line WLi from the second load circuit 14.
Discharge is performed through one dummy cell DCi selected by (i = 1, 2, ... M). Therefore, in order to maintain the reference potential Vref at an intermediate potential between the “1” level and the “0” level of the input potential Vin on the main body memory cell side, the load MOSFET in the second load circuit 14 is kept.
The current supply capacity of QD ₇ ′ is set to about twice that of the corresponding MOSFET QD ₇ of the conventional device shown in FIG.

Next, in the memory device having such a configuration, the operation when the row lines are switched and data is continuously read from two memory cells selected by different row lines will be described. When the row lines are switched, as shown in the waveform diagram of FIG. 2 (a), the potential of the non-selected row line WLi drops from "1" level to "0" level and is selected. Row line WLj
Potential rises from "0" level to "1" level. The current flowing through the second load circuit 14 at the time of switching the row line changes as shown by the solid line in FIG. 2 (b). That is, the value of the current x in the figure is the dummy cells DC ₁ to DC ₁ when the "1" level signal which is the power supply voltage Vcc is supplied to the gate.
Any one of DC _m or dummy cell DC
a current flowing through the _{m + 1,} the value of the current a is the minimum value of any one of current flowing out of the dummy cell DC ₁ to DC _m when switching comparatively row line. Therefore, in the circuit of this embodiment, the maximum value of the current flowing through the second load circuit 14 when the row line is switched is 2x, and the minimum value thereof is x + a. In addition,
The alternate long and short dash line in FIG. 2 (b) shows the change in the current flowing through the second load circuit 14 of the conventional device of FIG. 10 when the row line is switched.

Fig. 3 shows a load circuit 14 made based on Fig. 2 above.
FIG. 6 is a waveform diagram showing a level change of the reference potential Vref with respect to the current flowing through the line. In FIG. 3, the potential Vin (“1” level) obtained when reading the data of the memory cell of “1” storage and the data of the memory cell of “0” storage are read together with the reference potential Vref. The level changes of the obtained potential Vin (“0” level) and the reference potential Vref (conventional) of the conventional device of FIG. 10 are also shown.

Reference potential Vref in the conventional device of FIG.
Is the point A where the curve of the potential Vref (conventional) intersects the current x.
However, in the case of the device of this embodiment, the potential Vref
Is the potential at the point B at which the current 2x intersects. This is because when any one row line is selected, in addition to any one of the dummy cells DC _{1 to} DC _m driven by that row line, the dummy cell DC _{m + 1} that is always driven is also selected.
Is connected to the dummy column line DBL, so that when the doubled cell current flows, the MOSFET Q in the second load circuit 14 is provided so that the reference potential of the same value as the conventional one can be obtained.
This is because the current supply capacity of D ₇ ′ is set.

By having such a change characteristic of the potential Vref, the potential Vin (“1” level) is shown in the figure when the charging action works most when switching the row lines, that is, when the value of the flowing current is the smallest. When it rises to point C, the reference potential Vref (conventional) in the conventional device of FIG. 10 rises to the potential of point D, which is the intersection with the current value a. On the contrary,
In the case of the device of this embodiment, the reference potential Vref does not rise to the potential at point E, which is the intersection with the current value x + a.

FIG. 4 shows a reference potential Vref when the data of the memory cell of "1" storage next to the memory cell of "1" storage is read continuously by switching the row line in the above-described embodiment device. FIG. 7 is a waveform diagram showing a change in potential Vin (“1” level). As described above, the level at which the reference potential Vref rises when the charging action is most exerted when the row lines are switched is significantly suppressed as compared with the case of FIG. Moreover, the reference potential Vref does not intersect with the potential Vin as seen in the conventional device shown in FIG.

Therefore, as shown in the waveform diagram of FIG. 5, when the row line is switched and the data of the memory cell of "0" memory is read from the memory cell of "1" memory, the read time is shown by the broken line. Compared with the rise of the reference potential, the rise of the reference potential in the device of this embodiment, which is indicated by the alternate long and short dash line, is faster by a smaller amount, and can be shortened by the time T2 than the delay time T1 of the data read in FIG. . As a result, the data read speed can be increased.

In this embodiment, the case where the power supply voltage _Vcc is supplied to the gate of the dummy cell DC _{m + 1} has been described, but this is not limited to the power supply voltage Vcc as long as it is a constant voltage, and based on the level of this constant voltage. The reference potential can be adjusted. Further, in this embodiment, m pieces of dummy cells _DC 1 to DC _m which is controlled by the row line
If, has been described for connecting the dummy cell _{DC m + 1} in the same dummy column line DBL, which is the m-number of dummy cells _DC 1 to DC _m, independently for the dummy cell _{DC m + 1,} the dummy column line, the column gate Similar reference potentials can be obtained by providing MOSFETs and load circuits equivalent to MOSFETs, and connecting the outputs of both load circuits to the input of the sense amplifier 15.

FIG. 6 is a circuit diagram showing a structure of a semiconductor memory device according to another embodiment of the present invention. Similar to the device of the embodiment shown in FIG. 1, this embodiment also implements the present invention on an EPROM using a floating gate type MOSFET as a memory cell. The device of this embodiment is different from the device of FIG. ₁ in that the source voltage V _cc is not always supplied to the gate of the dummy cell DC _{m + 1} , but the output of the row address buffer 17 supplied with the row address is supplied. In response to this, an address transition detector (hereinafter referred to as ATD) 18 for generating a pulse signal having a predetermined pulse width when the row address changes is provided, and an output pulse signal from this ATD 18 is supplied to the dummy cell DC _{m + 1} . It is designed to be supplied to the gate. In FIG. 6, 19 is a column address buffer to which a column address is supplied, and the row decoder 11 and the column decoder 12 are supplied with the outputs of the row address buffer 17 and the column address buffer 19. ing.

In the device of this embodiment, a pulse signal is generated from the ATD 18 during the transitional period when the row address is changed and the row line is switched, and the dummy cell DC _{m + 1} is turned on only when the row line is switched. As a result, the amount of current flowing through the dummy column line DBL at the time of switching the row line is increased, which suppresses the rise of the reference potential Vref.

In the case of the device of this embodiment, the dummy cell DC _{m + 1} is turned off after the row lines are completely switched. That is, normally, the dummy cell driven by the row line is the dummy cell D.
Since it is any one of C _{1 to} DC _m , the current driving capability of the load MOSFET QD ₇ ′ in the second load circuit 14 is the same as that of the conventional device shown in FIG.
Set equal to SFET QD ₇ .

In each of the above embodiments, when the row line is switched, the discharge current of the dummy column line DBL is increased to change the reference potential Vref.
Since the current supply capacity of the second load circuit 14 to the node is substantially reduced so as to suppress the rise of the reference potential Vref at the time of switching the row line, the dummy cell DC _{m + 1} as described above. Even if the current supply capacity of the second load circuit 14 is controlled without providing the above, the same effect can be obtained.

FIG. 7 shows the configuration of the embodiment apparatus in which the current supply capacity of the second load circuit 14 is controlled as described above. The device of this embodiment has two load Ps in the second load circuit 14.
Channel MOSFETs QD _7a and QD _7b are provided in parallel, the gate of one MOSFET QD _7a is connected to its drain, and the output pulse from the ATD 18 is supplied to the gate of the other MOSFET QD _7b. is there.

In a device having such a configuration, when switching the row line, A
MOSFET by the pulse signal output from TD18
The QD _7b is turned off, and the amount of current supplied to the node of the reference potential Vref decreases, whereby the rise of the reference potential Vref is suppressed. In the device of this embodiment, after the row lines are completely switched, the two MOSFETs QD _{7a, 7b} for load in the load circuit 14 shown in FIG.
Both MOSFET QDs because both are turned on.
The sum of the current drive capacities of _{7a and 7b} is set to be equivalent to that of the MOSFET QD ₇ in the conventional device shown in FIG. In the case of the device of the embodiment shown in FIG. _{7, a} load circuit may be formed independently for each of the two load MOSFETs QD _{7a, 7b} .

FIG. 8 is a timing chart for explaining the operation of the ATD 18 used in the apparatus of the embodiment shown in FIGS. 6 and 7. That is, this ATD 18 generates a pulse signal having a predetermined pulse width that becomes "1" level during the switching of the row line when the row address from the outside changes and the row line switches in accordance with this address change. To do. Such a circuit can be easily constructed by combining a signal delay circuit and a logic circuit.

It is needless to say that the present invention is not limited to the above embodiment and various modifications can be made. For example, in the above embodiment, the case where the present invention is applied to the EPROM has been described.
Ordinary mask ROM using T as a memory cell and selectively implanting ions in the channel region in the course of the structure process to form high threshold voltage and low threshold voltage.
Needless to say, the present invention can be implemented.

Further, in each of the embodiments, the case of using the P-channel MOSFET as the load MOSFET has been described, but this is an N-channel MOSFE as long as it has an equivalent current supply capacity.
It is also possible to use T. However, an N-channel MOSF is used as the load MOSFET of the embodiment apparatus of FIG.
When using ET, it is necessary to generate a pulse signal having a phase opposite to that of the above case in the ATD 18. In each of the embodiments, the dummy cell DC _{m + 1} does not necessarily have to be the same as the memory cell.

[Effects of the Invention] As described above, according to the present invention, there is provided a semiconductor memory device in which noise is not generated in the power supply even during the transition period when the selection of the row line is switched, and the data reading speed can be improved. can do.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing the structure of a semiconductor memory device according to an embodiment of the present invention, FIGS. 2 to 5 are waveform diagrams for explaining the device of the above embodiment, and FIG. 6 is another embodiment of the present invention. FIG. 7 is a circuit diagram showing a configuration according to another embodiment of the present invention, FIG. 7 is a circuit diagram showing a configuration according to still another embodiment of the present invention, and FIG. 8 is a diagram showing a configuration used in the embodiment apparatus of FIGS. 6 and 7 above. 9 is a timing chart showing the operation of a partial circuit, FIG. 9 is a circuit diagram of a conventional device, FIG. 10 is a waveform diagram of the conventional device of FIG.
FIG. 11 is a circuit diagram of another conventional device different from the above,
2 and 13 are waveform diagrams for explaining the conventional apparatus of FIG. 11, respectively. MC _{11 to} MC _{1n to} MC _mn ... Memory cell, DC ₁
~ DC _{m + 1} ... dummy cell, WL _{1 to} WL _m ... row line, BL _{1 to} BL _n ... column line, DBL ... dummy column line,
11 ... Row decoder, 12 ... Column decoder, BT _{1 to} BT _n
...... Column gate MOSFET, DBT ...... MOSFE
T, 13 ... first load circuit, 14 ... second load circuit, 15
...... Sense amplifier, 16 …… Output buffer, 17 …… Row address buffer, 18 …… Address transition detector (ATD), 19 …… Column address buffer.

Front page continued (72) Inventor Hiroto Nakai 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Inside the Tamagawa Plant, Toshiba Corporation (72) Inventor Isao Sato 25 Kawasaki-ku, Kawasaki-ku, Kanagawa Prefecture 1 Toshiba Micro Inside Engineering Co., Ltd. (72) Inventor Shigeru Kumagai 25-1 Ekimaehonmachi, Kawasaki-ku, Kawasaki City, Kanagawa Prefecture Toshiba Micro Engineering Co., Ltd.

Claims (3)

[Claims] 1. A row line, a memory cell selected by the row line, a column line for receiving data from the memory cell, a first load circuit connected to the column line, and the row line. A selected first dummy cell, a dummy column line to which the first dummy cell is connected, a second load circuit connected to the dummy column line, and a predetermined potential at the gate connected to the dummy column line A semiconductor memory device comprising: a second dummy cell to be supplied; and a sense amplifier that detects stored data in the memory cell based on a potential difference between the column line and the dummy column line. 2. A row line, a memory cell selected by the row line, a column line for receiving data from the memory cell, a first load circuit connected to the column line, and the row line. A first dummy cell to be selected, a dummy column line to which the first dummy cell is connected, a second load circuit connected to the dummy column line, and a change in address input is detected to generate a pulse signal. Based on a potential difference between the column line and the dummy column line, the second dummy cell connected to the dummy column line and controlled in conduction by the pulse signal generated by the pulse signal generation circuit. A semiconductor memory device comprising: a sense amplifier that detects data stored in a memory cell. 3. A row line, a memory cell selected by the row line, a column line for receiving data from the memory cell, a first load circuit connected to the column line, and the row line. A dummy cell to be selected, a dummy column line to which the dummy cell is connected, a pulse signal generation circuit for detecting a change in address input and generating a pulse signal, and a pulse signal generation circuit connected to the dummy column line and generated by the pulse signal generation circuit. A second load circuit whose current supply capability to a dummy column line is controlled according to a pulse signal generated by the pulse signal, and a sense amplifier which detects stored data in the memory cell based on a potential difference between the column line and the dummy column line. A semiconductor memory device comprising: