JPH0642213B2 - Address conversion method - Google Patents
Address conversion methodInfo
- Publication number
- JPH0642213B2 JPH0642213B2 JP61036301A JP3630186A JPH0642213B2 JP H0642213 B2 JPH0642213 B2 JP H0642213B2 JP 61036301 A JP61036301 A JP 61036301A JP 3630186 A JP3630186 A JP 3630186A JP H0642213 B2 JPH0642213 B2 JP H0642213B2
- Authority
- JP
- Japan
- Prior art keywords
- tlb
- buffer
- main
- common area
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Memory System Of A Hierarchy Structure (AREA)
Description
【発明の詳細な説明】 〔概要〕 変換索引バッファをユーザ用と共通域用に分け、ユーザ
用を更に主及び副に分け、使用頻度の高い共通域用に障
害が発生した場合、主と共通域用を入れ換えて使用し、
此の動作をフラグにより制御する。DETAILED DESCRIPTION [Outline] The conversion index buffer is divided into a user area and a common area, and a user area is further divided into a main area and a sub area. When a failure occurs in a frequently used common area, it is shared with the main area. Use by changing the area
This operation is controlled by a flag.
本発明は変換索引バッファのアドレス変換方式に係り、
特に多重仮想記憶による変換索引バッファのアドレス変
換方式に関するものである。The present invention relates to a translation lookaside buffer address translation method,
In particular, the present invention relates to an address conversion method of a conversion index buffer using multiple virtual memories.
〔従来の技術〕 仮想記憶方式の計算機に於ける動的アドレス変換（ＤＡ
Ｔ−dynamic address translation）とは命令の実行中
に仮想アドレスを実アドレスに変換することであり、此
の動的アドレス変換を高速に行うハードウェアを変換索
引バッファと云う。[Prior Art] Dynamic address translation (DA
T-dynamic address translation) is a translation of a virtual address into a real address during execution of an instruction, and hardware for performing this dynamic address translation at high speed is called a translation lookaside buffer.
尚変換索引バッファ（translation lookaside buffer）
を以下ＴＬＢと称す。A translation lookaside buffer
Is hereinafter referred to as TLB.
第３図〜第５図は従来のＴＬＢによるアドレス変換の説
明図である。3 to 5 are explanatory views of address conversion by the conventional TLB.
図中、３は論理アドレス、20はＴＬＢ、21は変換テーブ
ル、22はユーザ用ＴＬＢ、23は共通域用ＴＬＢ、24は主
ＴＬＢ、25は副ＴＬＢ、26は比較回路、12は実アドレス
である。尚以下全図を通じ同一記号は同一対象物を表
す。In the figure, 3 is a logical address, 20 is a TLB, 21 is a conversion table, 22 is a user TLB, 23 is a common area TLB, 24 is a main TLB, 25 is a sub TLB, 26 is a comparison circuit, and 12 is a real address. is there. The same symbols represent the same objects throughout the drawings.
第３図に示す様にＴＬＢによるアドレス変換はＴＬＢに
よる変換及びテーブルによる変換を同時に行い、ＴＬＢ
20でミスヒットした場合、テーブル21によるアドレス変
換の値をＴＬＢ20に登録し、再度ＴＬＢ20をアクセスし
て実アドレス12を求める方式である。As shown in FIG. 3, the TLB address translation is performed simultaneously with the TLB translation and the table translation.
When there is a mishit in 20, the value of the address conversion by the table 21 is registered in the TLB 20, and the TLB 20 is accessed again to obtain the real address 12.
然しＴＬＢ20の容量は小さく、登録出来るアドレス変換
対の数が少ないので高ヒット率は望めず、此の為アドレ
ス変換速度が遅くなると云う欠点がある。However, since the capacity of the TLB 20 is small and the number of address translation pairs that can be registered is small, a high hit rate cannot be expected, which has the drawback of slowing down the address translation speed.
又多重仮想記憶で使用した場合には、アクセス頻度の高
い共通域用のアドレスにより、他の登録出来るアドレス
数が少なくなってＴＬＢの利用効率が悪くなり、ヒット
率が低下する。When used in multiple virtual memory, the number of other registerable addresses decreases due to the common area addresses that are frequently accessed, and the TLB utilization efficiency deteriorates, and the hit rate decreases.
此の欠点を解決する為、第４図に示す様にＴＬＢ20をユ
ーザ用ＴＬＢ22と共通域用ＴＬＢ23の二つに分けたり、
第５図に示す様に主ＴＬＢ24と副ＴＬＢ25に分けて共に
ユーザ用に割当てヒット率の向上を計ろうとする方式が
採られている。In order to solve this drawback, as shown in FIG. 4, the TLB 20 is divided into a user TLB 22 and a common area TLB 23.
As shown in FIG. 5, a system is adopted in which the main TLB 24 and the sub TLB 25 are divided and both are designed to improve the allocation hit ratio for the user.
然しながら前者の方式ではユーザ用ＴＬＢ22に共通域用
のアドレスが登録されないので多少登録数が増加するが
ＴＬＢの容量が小さいので其程ヒット率は向上しない。
又後者の方式も用途別に分けていないだけで条件は同じ
である。但し前者の利点はＴＬＢのパージ（無効化）の
時共通域用のアドレスを振り分けなくて済むのでパージ
の効率は良い。However, in the former method, since the common area address is not registered in the user TLB 22, the number of registrations increases a little, but the capacity of the TLB is small, so the hit rate does not improve so much.
The latter method is also the same except that it is not divided according to use. However, the former advantage is that the purging efficiency is good because the address for the common area does not have to be allocated when purging (invalidating) the TLB.
何れにしてもＴＬＢに障害が発生した場合、障害が発生
したＴＬＢを切り離したり、障害が発生した部分を切り
離したりするだけであるのでＴＬＢの登録出来る容量は
小さくなり、ヒット率は低下すると云う欠点があった。In any case, when a failure occurs in the TLB, the TLB in which the failure has occurred or the part in which the failure has occurred are only disconnected, so the capacity that can be registered in the TLB becomes smaller and the hit rate decreases. was there.
上記問題点は第１図の原理図に示す様に変換索引バッフ
ァを共通域用ＴＬＢ９とユーザ用ＴＬＢ13に分け、ユー
ザ用ＴＬＢ13を主ＴＬＢ７と副ＴＬＢ８に分け、フラグ
用レジスタ１に切替えフラグＦを設け、切替えフラグＦ
が１の時は主ＴＬＢ７を主ＴＬＢ、共通域用ＴＬＢ９を
共通域用ＴＬＢとして使用し、切替えフラグＦが０の時
は主ＴＬＢ７を共通域用ＴＬＢ、共通域用ＴＬＢ９を主
ＴＬＢとして使用する様にし、切替えフラグＦが１の
時、主ＴＬＢ７に障害が発生した場合、切替えフラグＦ
を０として共通域用ＴＬＢ９を主ＴＬＢとする切替えを
行うことにより解決される。As for the above problem, as shown in the principle diagram of FIG. 1, the conversion index buffer is divided into a common area TLB 9 and a user TLB 13, the user TLB 13 is divided into a main TLB 7 and a sub TLB 8, and a switching flag F is set in the flag register 1. Provided, switching flag F
When is 1, the main TLB7 is used as the main TLB and the common area TLB9 is used as the common area TLB. When the switching flag F is 0, the main TLB7 is used as the common area TLB and the common area TLB9 is used as the main TLB. Similarly, when the switching flag F is 1 and a failure occurs in the main TLB 7, the switching flag F
Is set to 0 and switching is performed by using the common area TLB 9 as the main TLB.
本発明に依るとＴＬＢをユーザ用と共通域用に分け、更
にユーザ用ＴＬＢを主ＴＬＢと副ＴＬＢに分けて大容量
化を計り、又アクセス頻度の高い共通域用ＴＬＢに障害
が発生した場合、主ＴＬＢを共通域用にし、共通域用Ｔ
ＬＢの内障害が発生した箇所のみを切り離して主ＴＬＢ
とし、此れ等の動作を全てフラグにより行うので、ＴＬ
Ｂの有効利用が可能となり、ＴＬＢのヒット率が向上
し、障害発生時のシステム低下を最少に出来ると云う効
果が生まれる。According to the present invention, the TLB is divided into a user area and a common area, and the user TLB is further divided into a main TLB and a sub-TLB to increase the capacity, and a failure occurs in the common area TLB that is frequently accessed. , Main TLB for common area, common area T
Main TLB by disconnecting only the location of the failure in the LB
Since all of these operations are performed by flags, TL
B can be effectively used, the hit rate of TLB is improved, and the system degradation at the time of failure can be minimized.
第２図は本発明に依るアドレス変換方式の一実施例を示
すブロック図である。FIG. 2 is a block diagram showing an embodiment of the address conversion system according to the present invention.
図中、１はフラグ用レジスタ、２は比較対象アドレス用
レジスタ、４、５は夫々比較回路、６、10は夫々セレク
タ、７は主ＴＬＢ、８は副ＴＬＢ、９は共通域用ＴＬ
Ｂ、11は３ステートバッファ、13はユーザ用ＴＬＢであ
る。In the figure, 1 is a flag register, 2 is a comparison target address register, 4 and 5 are comparison circuits, 6 and 10 are selectors, 7 is a main TLB, 8 is a sub TLB, and 9 is a common area TL.
B and 11 are 3-state buffers, and 13 is a user TLB.
本発明に於いてＴＬＢは共通域用ＴＬＢ９とユーザ用Ｔ
ＬＢ13に分けられ、更にユーザ用ＴＬＢ13は主ＴＬＢ７
と副ＴＬＢ８に分けられる。In the present invention, the TLB is the TLB 9 for the common area and the TLB for the user.
It is divided into LB13, and the user TLB13 is the main TLB7.
And sub-TLB8.
又主ＴＬＢ７は共通域用としても使用され、共通域用Ｔ
ＬＢ９は主ＴＬＢとしても使用される。The main TLB7 is also used for the common area, and the T for the common area is used.
LB9 is also used as the main TLB.
此の様に主ＴＬＢ７を主ＴＬＢとして使用し、ユーザ用
ＴＬＢ13をユーザ用ＴＬＢとして使用するために切替え
フラグＦを設ける。As described above, the switching flag F is provided to use the main TLB 7 as the main TLB and the user TLB 13 as the user TLB.
本発明では切替えフラグＦ＝１の場合には、ユーザ用Ｔ
ＬＢ13の主ＴＬＢ７と副ＴＬＢ８は夫々主ＴＬＢ及び副
ＴＬＢとして使用される。In the present invention, if the switching flag F = 1, the T for user is
The main TLB7 and the sub-TLB8 of LB13 are used as the main TLB and the sub-TLB, respectively.
切替えフラグＦ＝０の場合には、共通域用ＴＬＢ９が主
ＴＬＢとして使用され、主ＴＬＢ７は共通域用として使
用される。When the switching flag F = 0, the common area TLB 9 is used as the main TLB, and the main TLB 7 is used as the common area.
又比較対象アドレス用レジスタ２には、論理アドレス３
が共通域のアドレスであるか否かを判定する為のアドレ
スが格納されている。The logical address 3 is stored in the comparison target address register 2.
An address for determining whether or not is a common area address is stored.
此の様に設定することにより、論理アドレス３の値が共
通域のアドレスであるか否かにより主ＲＬＢとして共通
域用ＴＬＢ９か又は主ＴＬＢ７が選択される。By setting in this way, the common area TLB 9 or the main TLB 7 is selected as the main RLB depending on whether or not the value of the logical address 3 is the address of the common area.
フラグ用レジスタ１から出力された切替えフラグＦを比
較回路４によりチェックする。The comparison circuit 4 checks the switching flag F output from the flag register 1.
今仮にＦ＝１とする。Suppose now that F = 1.
此の時、比較回路５により論理アドレス３の値と比較対
象アドレス用レジスタ２の値が比較される。若し論理ア
ドレス３が共通域のアドレスでない場合は、比較回路５
と切替えフラグＦの値でセレクタ６により主ＴＬＢ７が
選択され、主ＴＬＢ７、及び副ＴＬＢ８がアクセスされ
る。At this time, the comparison circuit 5 compares the value of the logical address 3 with the value of the comparison target address register 2. If the logical address 3 is not the address in the common area, the comparison circuit 5
The main TLB 7 is selected by the selector 6 by the value of the switching flag F and the main TLB 7 and the sub TLB 8 are accessed.
若し論理アドレス３の値が共通域のアドレスである場合
は、比較回路５と切替えフラグＦの値でセレクタ６によ
り共通域用ＴＬＢ９が選択され、共通域用ＴＬＢ９がア
クセスされる。If the value of the logical address 3 is an address in the common area, the selector 6 selects the common area TLB 9 according to the values of the comparison circuit 5 and the switching flag F, and the common area TLB 9 is accessed.
論理アドレス３の値が共通域のアドレスでない時、主Ｔ
ＬＢ７をアクセスし、実アドレスが求められれば此の値
を実アドレス12に出力して終了する。When the value of logical address 3 is not a common area address, the main T
When LB7 is accessed and the real address is obtained, this value is output to the real address 12 and the process ends.
然し主ＴＬＢ７でミスヒットし、副ＴＬＢ８でヒットし
た時は此の値を実アドレス12に出力すると共にセレクタ
10によりフラグＦを見て何れのＴＬＢが主ＴＬＢとなっ
ているかを識別し（此の場合は主ＴＬＢ７である）、副
ＴＬＢ８でヒットした値を主ＴＬＢ７に登録し、主ＴＬ
Ｂ７で追い出されたアドレスを副ＴＬＢ８に登録する。However, when the main TLB7 misses and the sub-TLB8 hits, this value is output to the real address 12 and the selector
The flag F is checked by 10 to identify which TLB is the main TLB (in this case, the main TLB7), the value hit in the sub TLB8 is registered in the main TLB7, and the main TL7 is registered.
The address evicted in B7 is registered in the sub-TLB8.
又副ＴＬＢ８でもミスヒットした時はテーブル変換によ
りアドレスを求め、論理アドレスが共通域のアドレスで
あるか否かを比較し、又フラグＦを見て共通域のアドレ
スでなければ主ＴＬＢ７に登録し、共通域のアドレスで
あれば共通域用ＴＬＢ９に登録し、其の後再びＴＬＢに
アクセスして実アドレスを求める。When the sub-TLB8 also has a mishit, an address is obtained by table conversion, whether or not the logical address is a common area address is compared, and the flag F is checked, and if it is not a common area address, it is registered in the main TLB7. If it is a common area address, it is registered in the common area TLB 9, and then the TLB is accessed again to obtain the real address.
尚セレクタ10は主ＴＬＢ７及び共通域用ＴＬＢ９でヒッ
トした場合は副ＴＬＢ８とは接続されていない状態とな
る。When the selector 10 hits the main TLB 7 and the common area TLB 9, the selector 10 is not connected to the sub TLB 8.
尚上記説明では主ＴＬＢ７が主ＴＬＢとして使用される
場合、即ち、Ｆ＝１の場合に就いて述べたが、共通域用
ＴＬＢ９が主ＴＬＢとして使用される場合、即ち、Ｆ＝
０の場合に就いても全く同様に動作する。In the above description, the case where the main TLB 7 is used as the main TLB, that is, the case where F = 1 is described, but when the common area TLB 9 is used as the main TLB, that is, F =
Even if it is 0, the same operation is performed.
今Ｆ＝１の場合には、共通域用ＴＬＢ９に障害が発生し
た場合は、切替えフラグＦ＝１であるのでフラグ書換え
信号が共通域用ＴＬＢ９から出力されてフラグ用レジス
タ１に格納されている切替えフラグＦ＝０とし、主ＴＬ
Ｂ７と共通域用ＴＬＢ９が入れ換わる。又切替えフラグ
Ｆを書き替えた後は切替えフラグＦ＝０となるので３ス
テートバッファ11がインヒビットされ、フラグ書換え信
号は機能しない。In the case of F = 1 now, when a failure occurs in the common area TLB 9, the switching flag F = 1, so the flag rewriting signal is output from the common area TLB 9 and stored in the flag register 1. Switching flag F = 0, main TL
B7 and TLB9 for common area are exchanged. Further, after the switching flag F is rewritten, the switching flag F = 0, so that the 3-state buffer 11 is inhibited and the flag rewriting signal does not function.
従って一度障害が発生して共通域用ＴＬＢ９が主ＴＬＢ
として動作している時に、共通域用ＴＬＢ９に障害が発
生しても切替えは行われず、障害発生信号により障害発
生フラグが立ち、これにより障害発生の箇所のみ切り離
されて使用される。Therefore, once a failure occurs, the common area TLB9 is the main TLB.
In this case, even if a failure occurs in the TLB 9 for common area, switching is not performed, and a failure occurrence flag is raised by the failure occurrence signal, whereby only the location where the failure has occurred is separated and used.
以上詳細に説明した様に本発明の方式を採ることによ
り、主ＴＬＢにはアクセス頻度の高いアドレスが常に登
録される様になる。As described in detail above, by adopting the method of the present invention, an address with high access frequency is always registered in the main TLB.
又共通域用とユーザー用に分けているのでバージの時共
通域用のアドレスを振り分けなくても良いためパージの
効率が良くなる。Further, since the address is divided into the common area and the user area, it is not necessary to allocate the address for the common area when the barge occurs, so that the purging efficiency is improved.
更にユーザー用ＴＬＢを主ＴＬＢ７と副ＴＬＢ８の二つ
に分け、副ＴＬＢ８は主ＴＬＢ７より低速であるが大容
量のＴＬＢを使用することにより共通域用ＴＬＢ９に障
害が発生して主ＴＬＢ７に入れ換わってもＴＬＢの容量
は充分有るのでヒット率に大きい影響を与えない。Further, the user TLB is divided into a main TLB7 and a sub-TLB8. The sub-TLB8 is slower than the main TLB7, but by using a large capacity TLB, a failure occurs in the common area TLB9 and it is replaced with the main TLB7. However, since the capacity of the TLB is sufficient, it does not significantly affect the hit rate.
此の結果、ＴＬＢの有効利用、ヒット率の向上が計ら
れ、障害発生時にもシステム全体の性能低下を最少に抑
えることが可能となると云う大きい効果がある。As a result, it is possible to effectively use the TLB and improve the hit rate, and it is possible to minimize the performance deterioration of the entire system even when a failure occurs.
第１図は本発明の原理図である。 第２図は本発明に依るアドレス変換方式の一実施例を示
すブロック図である。 第３図〜第５図は従来のＴＬＢによるアドレス変換の説
明図である。 図中、１はフラグ用レジスタ、２は比較対象アドレス用
レジスタ、３は論理アドレス、４、５は夫々比較回路、
６、10は夫々セレクタ、７は主ＴＬＢ、８は副ＴＬＢ、
９は共通域用ＴＬＢ、11は３ステートバッファ、12は実
アドレス、13はユーザ用ＴＬＢ、20はＴＬＢ、21は変換
テーブル、22はユーザ用ＴＬＢ、23は共通域用ＴＬＢ、
24は主ＴＬＢ、25は副ＴＬＢ、26は比較回路、30は利用
装置である。FIG. 1 is a principle diagram of the present invention. FIG. 2 is a block diagram showing an embodiment of the address conversion system according to the present invention. 3 to 5 are explanatory views of address conversion by the conventional TLB. In the figure, 1 is a flag register, 2 is a comparison target address register, 3 is a logical address, 4 and 5 are comparison circuits, respectively.
6 and 10 are selectors, 7 is a main TLB, 8 is a sub TLB,
9 is a common area TLB, 11 is a 3-state buffer, 12 is a real address, 13 is a user TLB, 20 is a TLB, 21 is a conversion table, 22 is a user TLB, and 23 is a common area TLB,
Reference numeral 24 is a main TLB, 25 is a sub TLB, 26 is a comparison circuit, and 30 is a utilization device.
Claims (1)
換索引バッファを備え、 利用装置(30)が該論理アドレスを発することにより記憶
装置の特定アドレスを該変換索引バッファを介してアク
セスする仮想記憶方式の計算機に於いて、 該変換索引バッファを共通域用バッファ（９）とユーザ
用バッファ(13)に分け分割し、 該ユーザ用バッファ(13)を主バッファ(7)と副バッファ
(8)に分割して構成すると共に、 外部からの設定に応じ該利用装置(30)による利用変換バ
ッファとして共通域用バッファ（９）又は主バッファ
(7)を指定する切換えフラグ（Ｆ）を設け、 該切替えフラグ（Ｆ）が通常モードを示す時には該主バ
ッファ(7)をユーザ用バッファとして使用し、 該切替えフラグ（Ｆ）が異常モードの時には該主バッフ
ァ(7)を共通域用バッファ、該共通域用バッファ（９）
を主バッファとして使用することを特徴とするアドレス
変換方式。1. A virtual storage system comprising a translation index buffer for translating a logical address into a physical address, wherein a utilization device (30) issues the logical address to access a specific address of a storage device through the translation index buffer. In this computer, the conversion index buffer is divided into a common area buffer (9) and a user buffer (13), and the user buffer (13) is divided into a main buffer (7) and a sub-buffer.
It is divided into (8) and configured, and the common area buffer (9) or the main buffer is used as a conversion buffer for use by the utilization device (30) according to an external setting.
A switching flag (F) designating (7) is provided, and when the switching flag (F) indicates the normal mode, the main buffer (7) is used as a user buffer, and the switching flag (F) indicates the abnormal mode. Sometimes the main buffer (7) is a common area buffer, and the common area buffer (9)
An address conversion method characterized by using as a main buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61036301A JPH0642213B2 (en) | 1986-02-20 | 1986-02-20 | Address conversion method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61036301A JPH0642213B2 (en) | 1986-02-20 | 1986-02-20 | Address conversion method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62192832A JPS62192832A (en) | 1987-08-24 |
| JPH0642213B2 true JPH0642213B2 (en) | 1994-06-01 |
Family
ID=12465994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61036301A Expired - Lifetime JPH0642213B2 (en) | 1986-02-20 | 1986-02-20 | Address conversion method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0642213B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0612330A (en) * | 1992-06-24 | 1994-01-21 | Nec Corp | Storage control system |
| US20070094476A1 (en) * | 2005-10-20 | 2007-04-26 | Augsburg Victor R | Updating multiple levels of translation lookaside buffers (TLBs) field |
-
1986
- 1986-02-20 JP JP61036301A patent/JPH0642213B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62192832A (en) | 1987-08-24 |
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