WO2021208489A1

WO2021208489A1 - Data writing method and apparatus, and electronic device

Info

Publication number: WO2021208489A1
Application number: PCT/CN2020/139418
Authority: WO
Inventors: 付鹏
Original assignee: 北京磐易科技有限公司
Priority date: 2020-04-17
Filing date: 2020-12-25
Publication date: 2021-10-21
Also published as: CN111831587A

Abstract

Disclosed are a data writing method and apparatus, and an electronic device. The data writing method comprises the following steps: acquiring data to be written into a cache memory (401); extracting from the data missed data that was missed by a writing operation (402); if the missed data is write-only data and data is written for the first time into a write-in address corresponding to the writing operation for the missed data corresponding, then writing the missed data into the cache memory (403).

Description

Data writing method, device and electronic equipment

Cross-references to related applications

This application claims the priority of Chinese Patent Application No. 202010307935.X filed in China on April 17, 2020, the entire content of which is incorporated herein by reference.

Technical field

The present disclosure relates to the field of computer technology, and in particular to a data writing method, device and electronic equipment.

Background technique

Generally speaking, there is a big gap in the access speed between the processor (CPU) of an electronic device and the external main memory. If a high-speed CPU directly accesses a low-speed external main memory, the low-speed reading and writing of the external main memory will reduce the CPU's performance. effectiveness. Therefore, at present, the problem of the access speed mismatch between the CPU and the external main memory is mainly solved by the way of CPU + cache (high-speed buffer memory) + main memory.

At present, the data writing methods in the cache mainly include write-through and write-back. Among them, the write-through always writes data to the main memory during a write operation, and the write-back method is When the write cache misses, the data corresponding to the cache address is first read from the main memory to the cache and then the data is written into the cache. Therefore, the data writing methods in the related technology all need to read and write data from the main memory, resulting in low efficiency of data writing.

Summary of the invention

The embodiments of the present disclosure provide a data writing method, device, and electronic equipment to solve the problem of low efficiency of the current data writing method.

In order to solve the above technical problems, the present disclosure is implemented as follows:

In the first aspect, an embodiment of the present disclosure provides a data writing method, including the following steps:

Acquiring data to be written into the cache memory;

Extracting the missed data of the write operation missed in the data;

If the missed data is write-only data and the write address corresponding to the write operation of the missed data writes data for the first time, the missed data is written into the cache memory.

Optionally, the cache memory includes multiple lines of write addresses, and before extracting the missed data of the write operation missed in the data, the method further includes:

An indicator corresponding to the write address in each row is generated, and the indicator is used to indicate whether the corresponding write address is the first write data.

Optionally, the missed data is write-only data, including:

The write address corresponding to the write operation of the missed data is data of a write-only address, where the write-only address is a write address of the cache memory that meets a preset range.

Optionally, the writing the missed data into a cache memory includes:

The missed data is written into a target address, and the indicator corresponding to the target address is switched to correspond to non-first write data, wherein the target address is a write address in the write-only address.

Optionally, after writing the missed data into the cache memory, the method further includes:

If the write operation of all the missed data is completed, the indicator corresponding to the data written for the first time among the indicator flags of the write-only address is switched to corresponding to the data not written for the first time.

Optionally, after switching the indicator corresponding to the data written for the first time among the indicator flags of the write-only address to the data corresponding to the non-first written data, the method further includes:

Extracting hit data hit by a write operation in the data to be written, and writing the hit data to the cache memory in a write-back manner.

Optionally, after extracting the missed data of the write operation missed in the data, the method further includes:

If all the write operations of the write-only data are completed, the instruction mark corresponding to the first write data among the instruction marks of the write-only address is switched to correspond to the non-first write data.

In a second aspect, embodiments of the present disclosure provide a data writing device, including:

The acquisition module is used to acquire the data to be written into the high-speed buffer memory;

An extraction module for extracting missed data in the data that is missed by a write operation;

The writing module is configured to write the missed data into the cache memory if the missed data is write-only data and the write address corresponding to the write operation of the missed data writes data for the first time.

In a third aspect, embodiments of the present disclosure provide an electronic device, including a processor, a memory, and a computer program stored on the memory and capable of running on the processor, the computer program being executed by the processor When realizing the steps of the data writing method as described in any one of the above.

In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium on which a computer program is stored, and the computer program is executed by a processor to implement the steps of the data writing method described in any one of the above.

In the embodiment of the present disclosure, the data to be written into the cache memory is obtained; the miss data of the write operation missed in the data is extracted; if the miss data is write-only data and the write operation of the miss data corresponds If data is written to the write address for the first time, the missed data is written to the cache memory. In this way, by writing the miss, the corresponding write address as the first write data and write-only data directly to the cache memory, without going through the main memory, the number of accesses to the main memory can be reduced, thereby improving the data writing efficient.

Description of the drawings

In order to explain the technical solutions of the embodiments of the present disclosure more clearly, the following will briefly introduce the accompanying drawings used in the description of the embodiments of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained from these drawings without creative labor.

Figure 1 is a schematic structural diagram of an electronic device in the related art;

Figure 2 is a diagram of the index directory structure of the cache in the related technology;

Figure 3 is a schematic diagram of a data write-back operation in related technologies;

4 is a flowchart of a data writing method provided by an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of the structure of an electronic device in an embodiment of the present disclosure;

FIG. 6 is a structural diagram of the index directory of the cache in an embodiment of the present disclosure;

FIG. 7 is another flowchart of the data writing method provided by an embodiment of the present disclosure;

FIG. 8 is another flowchart of the data writing method provided by an embodiment of the present disclosure;

FIG. 9 is a schematic structural diagram of a data writing device in an embodiment of the present disclosure.

Detailed ways

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present disclosure.

As shown in Figure 1, the technical solution of this embodiment is applied to Central Processing Unit (CPU) + high-speed buffer memory (cache) + main memory (Dynamic Random Access Memory, DRAM, referred to as main memory for short) ) Structured electronic equipment, in which the CPU, cache, and main memory are sequentially connected in communication.

In related technologies, the basic operations of the cache are divided into reading and writing. Among them, the write operation mainly includes two types: write-through and write-back.

Write-through means that when a cache write hits, the processor writes data to the main memory while writing to the cache; when a cache write misses, it directly writes data to the main memory. In this way, the data in the memory and the data in the cache are synchronized. This method is simple and reliable. However, each write operation to the cache requires a write operation to the main memory, so the main memory bus takes up a large bandwidth and is inefficient. .

Write-back refers to when the CPU writes to the cache, it only modifies the contents of the cache without writing it to the main memory immediately, and only writes it back to the main memory when the cache line is swapped out.

As shown in Figure 2, when the cache write misses, a cache line is allocated in the cache for the main memory block that contains the writing to be written (the main memory block filled with shadow in the figure), and the cache line is copied to the cache and then modified It is stored locally in the cache. After that, multiple reads and writes to the cache line will hit and be completed quickly in the cache. Each cache line must be configured with a modification bit dirty to reflect whether the line has been modified by the CPU.

Please refer to Figure 3. Figure 3 is a diagram of the index directory structure corresponding to the cache. The tag is used to store the high-order address of the cache and the main memory address mapping, the status indicator dirty is used to indicate whether the cache content has been modified by the CPU, and valid indicates the cache line. is it effective.

In order to ensure that the cache data (cache data) is consistent with the main memory data (main memory data), the corresponding cache line data is written back to the slower main memory only when the dirty bit is valid when the cache line needs to be replaced. This method reduces The number of accesses to the main memory improves efficiency, but the cache line still needs to be read from the main memory when the write misses. For the above-mentioned write-through and write-back process, please refer to related technologies for details, which will not be repeated here.

The embodiment of the present disclosure provides a data writing method.

As shown in FIG. 4, in one embodiment, the data writing method includes the following steps:

Step 401: Obtain data to be written into the cache memory.

Generally speaking, data is sent from the CPU to the cache to be further written into the cache. For the specific process, please refer to related technologies, which will not be repeated here.

Step 402: Extract the missed data of the write operation missed in the data.

In this embodiment, the write operation data that misses the write operation among the data sent by the CPU to the cache is first obtained, in other words, it is to detect whether the write operation of the cache hits.

Finding useful data in the cache is called a write hit. When there is no data required by the CPU in the cache, it is called a write miss. The specific definition can refer to related technologies, and no further restrictions are made here. .

Step 403: If the missed data is write-only data and the write address corresponding to the write operation of the missed data writes data for the first time, write the missed data into the cache memory.

In this embodiment, it is further determined that the write only data in the missed data, and the corresponding write operation address has not written data before, this write operation is the first write of data at the write address, which will satisfy these requirements. The conditional data is written directly into the cache.

As an optional specific implementation manner, the definition of write-only data in this step 403 means that the write address corresponding to the write operation of the data is the data of the write-only address, where the write-only address is the cache The write address of the memory that meets the preset range.

Specifically, a write-only address range (write only region) can be set in the write address included in the cache in advance. In this embodiment, the write address of the cache that meets the write-only address range is called a write-only address, and the write operation When the corresponding write address is the write-only address, the data corresponding to the write operation is considered to be write-only data.

During implementation, as shown in Figure 5, the range of the write-only address can be increased on the cache port, so as to realize the screening of the write-only address.

For the data that meets the above conditions in the process of processing, the CPU only needs to write the value directly, and does not need to care about the value stored in the write address. Therefore, in the process of writing these data, there is no need to access the data initiated to the main memory. Read operation.

In this way, by writing the miss, the corresponding write address as the first write data and write-only data directly to the cache memory, without passing through the main memory, the number of accesses to the main memory can be reduced, thereby improving the data writing efficient.

Optionally, in a specific implementation, the cache memory includes multiple lines of write addresses.

Before the above step 402, it further includes:

Please refer to Figure 3 and Figure 6 at the same time. Different from the related technology shown in Figure 3, the index directory of the cache shown in Figure 6 further adds the indicator sflag, and each line of write address has an indicator. To indicate whether the row write address is the first write data.

For example, if the row writes data for the first time, that is, before this write operation, the row has not written data, the value of the indicator flag is set to 1, if the row is not written for the first time, that is, in this write If the row has written data before the operation, the value of the indicator is set to 0. In this way, by indexing the value of the indicator of the write address, it can be determined whether the write address is the first time data is written.

As shown in Figure 5, during implementation, the refresh control of the indicator sflag can be added to the port of the cache, so as to realize the refresh and switch of the indicator sflag.

Further, the above step 403 also includes:

If the write address corresponding to one write operation is the time write data, after the data is written to the write address, in order to avoid the subsequent impact when the data is written to the address again, adjust the corresponding indicator mark.

For example, if the indicator has a value of 1 when it indicates that data is written for the first time, and a value of 0 when it indicates that data is not written for the first time, then the value of the indicator will be cleared to 0 after the data is written for the first time, so as to avoid repetition. An error is indicated when writing.

That is to say, the above step 403 is only executed during the first write operation for a write address, and will not affect subsequent reads and writes.

Further, after step 403, it also includes:

If all the write operations of the write-only data are completed, the indicator mark corresponding to the first write data among the instruction marks of the write-only address is switched to correspond to the non-first write data.

It should be understood that all the write-only data here includes the write-only data in the hit data and the write-only data in the non-hit data. That is to say, when the writing operation of all the write-only data is completed, all the remaining indication marks are switched to correspond to the data not written for the first time, so as to avoid affecting the reading and writing of the non-write-only data.

Obviously, the data obtained in the above step 301 also includes the hit data hit by the write operation. In addition, for the miss data, it also includes the data that does not meet the conditions in step 303, that is, the non-write-only data or the miss data in the miss data. The write address corresponding to the write operation in the hit data is not the data where the data is written for the first time.

These data also need to be written into the cache. In order to avoid the loss of these data, further, the technical solution of this embodiment may further include after step 303:

Extracting hit data hit by a write operation in the data to be written, and writing the hit data to the cache memory in a write-back manner; and

If the missed data is non-write-only data or the write address corresponding to the write operation of the missed data is not the first write data, the missed data is written to the cache memory in a write-back manner .

In this way, by writing the remaining data into the cache memory in a write-back manner, it is possible to avoid data loss and ensure that all data is written into the cache memory.

Please refer to FIG. 7 and FIG. 8 at the same time. The technical solution of this embodiment can be summarized as follows.

First, all sflags are set, that is, the refresh all indication flag sflag corresponds to the first write data.

Next, it is checked whether the operation performed by the CPU is a write operation. If the operation performed by the CPU is a read operation, it is executed in a conventional write-back manner. For details, refer to related technologies.

Further, detect whether the cache write operation is missed, whether the write address corresponding to the write operation belongs to a preset write-only address, and whether the indicator sflag of the write address corresponding to the write operation is 1, that is, whether the indicator sflag indicates the first write Into the data.

If the data satisfies all the above conditions at the same time, the data is directly written into the cache memory. At this time, the other data in the cache line is overwritten as invalid data, and the tag is updated at the same time. At the same time, the corresponding indicator sflag is switched, and the corresponding The indication flag sflag is switched to indicate that the data is not written for the first time, or it is called the clear indication flag sflag.

When the write operation of all write-only data is completed, or all the write-only operations are completed, all the remaining indication flags sflag are cleared to 0 to avoid affecting the non-write-only data.

In this way, please refer to Figure 2 and Figure 7 at the same time. Compared with the related technology shown in Figure 2, the technical solution of this embodiment does not involve the read operation in the main memory. Therefore, the technical solution of this embodiment can reduce the cache direction. The number of reads of the main memory improves the efficiency of the main memory bandwidth usage.

As shown in FIG. 9, an embodiment of the present disclosure provides a data writing device 900, including:

The obtaining module 901 is used to obtain data to be written into the cache memory;

The extraction module 902 is configured to extract the missed data of the write operation missed in the data;

The writing module 903 is configured to write the missed data into the cache memory if the missed data is write-only data and the write address corresponding to the write operation of the missed data writes data for the first time.

Optionally, it also includes:

The generating module is used to generate an indicator corresponding to the write address in each row, and the indicator is used to indicate whether the corresponding write address is the first write data.

Optionally, the missed data is write-only data, including: data whose write address corresponding to the write operation of the missed data is a write-only address, wherein the write-only address is the data of the cache memory The write address that meets the preset range.

Optionally, the writing module 903 is specifically configured to: write the missed data to the target address, and switch the indicator corresponding to the target address to correspond to the non-first write data, wherein the target The address is the write address in the write-only address.

Optionally, it further includes: a switching module, which is used to switch the indicator corresponding to the first write data among the indicator flags of the write-only address in the indicator flag of the write-only address to the corresponding non-first write data.

Optionally, it further includes a write-back module, configured to extract hit data hit by a write operation in the data to be written, and write the hit data into the cache memory in a write-back manner.

Optionally, it further includes a write-back module, which is used to write the missed data if the missed data is non-write-only data or the write address corresponding to the write operation of the missed data is not the first write data Write to the cache memory in a write-back manner.

Since the data writing device 900 of this embodiment can implement all the technical solutions of the foregoing data writing method embodiments, it can at least achieve similar or substantially the same technical effects, which will not be repeated here.

The embodiments of the present disclosure also provide an electronic device, including a processor, a memory, and a computer program stored on the memory and capable of running on the processor. When the computer program is executed by the processor, the implementation is as follows: The steps of the data writing method described in any one of the above.

The embodiment of the present disclosure also provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of the data writing method described in any one of the above are implemented.

It should be noted that it should be understood that the division of the various modules of the above device is only a division of logical functions, and may be fully or partially integrated into a physical entity in actual implementation, or may be physically separated. And these modules can all be implemented in the form of software called by processing elements; they can also be implemented in the form of hardware; some modules can be implemented in the form of calling software by processing elements, and some of the modules can be implemented in the form of hardware. For example, the determining module may be a separately established processing element, or it may be integrated in a chip of the above-mentioned device for implementation. In addition, it may also be stored in the memory of the above-mentioned device in the form of program code, which is determined by a certain processing element of the above-mentioned device. Call and execute the functions of the above-identified module. The implementation of other modules is similar. In addition, all or part of these modules can be integrated together or implemented independently. The processing element described here may be an integrated circuit with signal processing capability. In the implementation process, each step of the above method or each of the above modules can be completed by an integrated logic circuit of hardware in the processor element or instructions in the form of software.

For example, each module, unit, sub-unit or sub-module may be one or more integrated circuits configured to implement the above method, for example: one or more application specific integrated circuits (ASIC), or one or Multiple microprocessors (digital signal processor, DSP), or one or more field programmable gate arrays (Field Programmable Gate Array, FPGA), etc. For another example, when one of the above modules is implemented in the form of processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processors that can call program codes. For another example, these modules can be integrated together and implemented in the form of a system-on-a-chip (SOC).

The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present application described herein, for example, can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations of them are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those clearly listed. Those steps or units may include other steps or units that are not clearly listed or are inherent to these processes, methods, products, or equipment. In addition, the use of "and/or" in the description and claims means at least one of the connected objects, such as A and/or B and/or C, which means that it includes A alone, B alone, C alone, and both A and B. Exist, B and C exist, A and C exist, and A, B, and C all exist in 7 situations. Similarly, the use of "at least one of A and B" in this specification and claims should be understood as "A alone, B alone, or both A and B exist".

The above are only specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present disclosure. It should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

A data writing method includes the following steps:

Acquiring data to be written into the cache memory;

Extracting the missed data of the write operation missed in the data;

If the missed data is write-only data and the write address corresponding to the write operation of the missed data writes data for the first time, the missed data is written into the cache memory.
5. The data writing method according to claim 1, wherein the cache memory includes multiple lines of write addresses, and before extracting the missed data of the write operation missed in the data, the method further comprises:

An indicator corresponding to the write address in each row is generated, and the indicator is used to indicate whether the corresponding write address is the first write data.
3. The data writing method of claim 2, wherein the missed data is write-only data, including:

The write address corresponding to the write operation of the missed data is data of a write-only address, where the write-only address is a write address of the cache memory that meets a preset range.
5. The data writing method according to claim 3, wherein the writing the missed data to a cache memory comprises:

The missed data is written into a target address, and the indicator corresponding to the target address is switched to correspond to non-first write data, wherein the target address is a write address in the write-only address.
5. The data writing method according to claim 4, wherein after writing the missed data into a cache memory, the method further comprises:

If the write operation of all the missed data is completed, the indicator corresponding to the data written for the first time among the indicator flags of the write-only address is switched to corresponding to the data not written for the first time.
5. The data writing method according to claim 5, wherein after switching the indicator corresponding to the data written for the first time among the indicator flags of the write-only address to the data corresponding to the non-first write data, the method further comprises:

The hit data hit by the write operation in the data to be written is extracted, and the hit data is written into the cache memory in a write-back manner.
The data writing method according to any one of claims 1 to 6, wherein after said extracting the missed data of the write operation missed in the data, the method further comprises:

If all the write operations of the write-only data are completed, the instruction mark corresponding to the first write data among the instruction marks of the write-only address is switched to correspond to the non-first write data.
A data writing device includes:

The acquisition module is used to acquire the data to be written into the high-speed buffer memory;

An extraction module for extracting missed data in the data that is missed by a write operation;

The writing module is configured to write the missed data into the cache memory if the missed data is write-only data and the write address corresponding to the write operation of the missed data writes data for the first time.
An electronic device comprising a processor, a memory, and a computer program stored on the memory and capable of running on the processor, the computer program being executed by the processor to implement any of claims 1 to 7 One of the steps of the data writing method.
A computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of the data writing method according to any one of claims 1 to 7 when the computer program is executed by a processor.