JPH0641344B2 - Sorter control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sorter.

[Conventional technology]

Conventionally, the sorting box of the sorter is controlled by inputting sorting information of the sorter by software and calculating the next sorting code by calculation or the like.

[Problems to be solved by the invention]

In the conventional sorter described above, there is no other way but to manage the sorting box by software, and when the sorting box becomes full due to overflow during sorting, the sorting status of the sorter is checked,
Since it takes time to transfer the next code, there is a disadvantage that it will be rejected unless the number of divided forms per unit time is reduced.

[Means for solving problems]

The sorting control circuit of the sorter according to the present invention sequentially and automatically senses the sorters when a sorting box for storing sorting designation codes indicating sorting designations of sorting boxes of the sorter is stored, and an overflow of the sorting boxes is detected. A sense circuit, a second storage unit that stores integrated information of the sort boxes of the sorter sensed by the sense circuit for each sorter, and a sort box of the sorter that is selectively read from the second storage unit. The accumulation information and the accumulation designation code read out in the priority order to be accumulated from the first storage unit are compared, and the division box designated by the accumulation designation code is empty according to the accumulation information of the sort box of the sorter. If it is determined that the integrated designating code at that time is determined to be the currently most prioritized integrated designating code and is output, a discriminating circuit that discriminates in the discriminating circuit. The integrated designation code of the highest priority has and a transfer circuit for transferring to the sorter.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a sorting control circuit for a sorter according to the present invention.

The memory 5 stores the sort code (sorter and sort box number) of the sorter into which the form is sorted in order of priority. This classification code has a sorter number of 1 in the upper 4 bits.
Designate in hexadecimal and assign the designation of each division box in bits with the lower 11 bits. In other words, a maximum of 11 bins can be specified. The maximum data that can be stored is 64K. Counter 11
Generates an address signal for the memory 5. The classification code is set in the register 8 by the set pulse when the form is next sent. From the register 9, when the division code is transferred to the sorter, the division code sample pulse synchronized with the internal synchronization clock is output to the sorter. Flip flop 10
When the sorter causes an overflow (when the form has exceeded the specified value in the sorting box), that state is set, and the counter is activated accordingly. When the counter 1 is activated, the sorter device number is automatically sensed from 1 to 5, and the F / F (flip-flop) 10 is reset and stopped. The decoder 2 decodes the output of the counter 1. When the sorter devices No. 1 to 5 are sensed, the register 3 ₁ , 3 ₂ , ..., 3 ₅ stores the sorter classification information output from the sensed sorter by the decode signal of the decoder 2. It The selector 4 receives the selection signals from the internal command register (not shown) and registers 3 ₁ , 3 ₂ ,
..., select the sorter classification information of 3 _5, to output. AND gate 6 _{0-6 10} takes a logical product of the outputs of the selectors 4 in the memory 5. Buffer 7 inputs the respective outputs of the AND gate 6 _{0-6 10} of the memory 5, and adds the minus sign data in the memory 5 coincides with the output of the selector 4. C
A PU (not shown) can be input from the buffer 7. The CPU sets an address (initial value "0" in the case of initial priority) corresponding to a value storing the current highest priority in the counter 11 and inputs it until the minus sign disappears. Since the CPU has an automatic increment function, the CPU can sequentially input data from the higher priority to the lower priority by continuing to input the data in the memory 5. Register 8 the data when the minus sign disappears
You can set it as it is.

In the present embodiment, automatic selection of sorter information is limited to a maximum of 5 units, but it is possible to increase the size infinitely by adding a counter or the like and designating a priority sequence by adding a memory at a maximum of 64K. Of course.

〔The invention's effect〕

As described above, the present invention automatically selects the sorter classification status and discriminates the highest priority code of the next code, so that (1) the form in the classification can be quickly switched to the next classification box. Yes, (2) Software processing can be performed efficiently, (3) Program memory capacity can be reduced, (4) Priority can be arbitrarily changed, so divide in any order There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a sorting control circuit for a sorter according to the present invention. 1 ... Counter, 2 ... Decoder, 3 _{1 to} 3 ₅ ... Register, 4 ... Selector, 5 ... Memory, 6 _{0 to} 6 ₁₀ ... Open collector AND circuit, 7 ... Buffer, 8,9 ...... Register, 10 …… Flip-flop, 11 …… Counter.

Claims (1)

[Claims] 1. A first storage unit for storing a stacking designation code indicating a stacking designation of sorting boxes of a sorter in the order of stacking priority; a sense circuit for automatically sensing the sorters sequentially when an overflow of the sorting boxes is detected; A second storage unit that stores, for each sorter, the integrated information of the sorting boxes of the sorter sensed by the sense circuit; the integrated information of the sorting boxes of the sorter that is selected and read from the second storage unit and the first storage unit. 1 is compared with a stacking designation code read out in the order of priority to be stacked, and the sorting box designated by the sorting designation code is determined to be an empty sorting box based on the sorting information of the sorting box of the sorter. In this case, a discrimination circuit that discriminates and outputs the integrated designation code at that time as the current highest priority integrated designation code, and the highest priority discriminated by the discrimination circuit. And a transfer circuit for transferring the integrated designation code to the sorter.