JPH0731635B2 - Information processing equipment - Google Patents

Description

The present invention relates to a memory access method for an information processing apparatus in which a storage device is pipeline-controlled.

[Conventional technology]

Conventionally, a storage device that is pipeline-controlled by an information processing device has a configuration such that the entire storage area has a single access time. Low cost memory was used.

[Problems to be Solved by the Invention]

In the above-described conventional information processing apparatus, since the storage device is pipeline-controlled despite the demand for high-speed memory access, the access time hierarchy that is the most orthodox, performance, and cost effective It is very difficult to form the structure. Therefore, in order to improve the performance, an approach is adopted in which all the storage devices are unified with an expensive memory per capacity in a fast access time, but as a result, there is a disadvantage that price performance is deteriorated.

[Means for Solving the Problems]

In the information processing device of the present invention, the storage device is TA ₁ , TA ₂ , ..., TA _m (TA ₁ <TA ₂ <... <TA _m ).
It has m kinds of storage areas with access times of, and sends memory request instruction information including read / write designation and address designation when the storage device needs to be accessed. It is composed of an information processing unit that adds data and sends it, and a shift register that shifts at regular intervals. When a memory request for reading is sent, access history information indicating the reply timing for the request is sent to the shift register. From the first stage of the above, regarding the access times TA ₁ , TA ₂ , ..., TA _m of the storage device, D ₂ = TA _m
−TA ₂ , D ₃ = TA _m −TA ₃ , ..., D _m = TA _m −TA _m D _i (i
= 2,3, ..., m) The access history register held in m-1 registers shifted by the time, the memory request instruction information sent by the information processing unit, and the write data at the time of writing are read / read. A memory request including a write designation and an address designation is generated, and if the request is a write designation, write data is sent to the storage device together with the memory request, and if a read designation is specified, a storage area related to the address designated by the request. From the access time of and the access history information related to the already sent memory request stored in the access history register, the reply timing when the generated memory request is sent matches the reply timing related to the already sent request. If it is determined that they do not match, the request is stored in the storage device. A memory request generator that, while sending out, registers access history information related to that request in the access history register, and if it determines that they match, suspends sending of the memory request and waits until it is determined that they do not match. Is.

Further, the information processing apparatus of the present invention sends memory request instruction information including read / write designation and address designation when access to the storage device is necessary, and additionally sends write data in the case of write designation. An access history register that is composed of a processing unit and a shift register that shifts at regular intervals, and that holds a plurality of bits of access history information that indicates the reply timing for a read-requested memory request , A memory request ID detection unit that decodes the multi-bit access history information held by the access history register and outputs ID information indicating the reply timing for the already sent memory request, and the memory request sent by the information processing unit Read by receiving instruction information and write data at the time of writing / Generates a memory request including write designation and address designation, sends write data together with the memory request to the storage device if the request is write designation, and stores the write address with the address designated by the request if read designation From the access time of the area and the ID information related to the already sent memory request output by the ID detection unit, the reply timing when the generated memory request is sent matches the reply timing related to the already sent request. If it is determined that they do not match, the request is sent to the storage device, and multiple-bit access history information related to the request is registered in the access history register, and it is determined that they match. Waits until the memory request is suspended and a mismatch is determined. To those having a memory request generator.

[Action]

The access history for the storage device is retained, and when the storage device is newly accessed, the already-accessed access history is referenced, so memory requests for storage areas with different access times are sent, and memory requests for which the reply timing has already been sent. It can be sent at a timing that does not collide with the reply timing of.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the information processing apparatus of the present invention, FIG. 2 is a block diagram showing the configuration of the access history register 120, and FIG. 3 is an information processing unit 100 outputting memory request instruction information. FIG. 4 is a timing chart showing an example of timing, and FIG. 4 is a memory request generation unit for the output timing of the memory request instruction information in FIG.
5 is a timing chart showing the output timing of the memory request of 110 and the reply timing of the main storage device 130.

As shown in FIG. 1, this information processing apparatus includes an information processing apparatus 100, a memory request generator 110, an access history register 120, and a main storage device 130.

The information processing unit 100 operates in the machine cycle "C", performs normal information processing, and stores memory request instruction information for read / write designation and address designation when access to the main storage device 130 is required. Output to the request generation unit 110. Further, when write is designated, write data is added and output to the memory request generation unit 100.

The main storage device 130 includes a memory request input port 131, a write data input port 132, and a reply data output port 133.
It has a storage area A1 with access time "14C", a storage area A2 with access time "26C" and a storage area A3 with access time "30C", and accepts memory requests at time "2C".
If read is specified, the reply data output port uses the data at the specified address as reply data at the reply timing after the access time of the storage area corresponding to the specified address after receiving the memory request. Output to the information processing unit 100 via 133.

The access history register 120 is the memory request generation unit 1
If the memory request sent by 10 is read,
The access request information is stored in the memory request generation unit 11 according to the storage area corresponding to the address specified by the request.
The access information input from 0 and further indicating the reply timing regarding the already sent memory request is output to the memory request generation unit 110. This access history register 120, as shown in FIG.
Main memory devices to be accessed are TA ₁ , TA ₂ , ..., TA _m (TA ₁ <TA ₂ <... <TA _m , which are composed of 8-bit (AR0 to AR7) shift registers for shifting data for each ) Has m kinds of storage time of m kinds of access time, D ₂ = TA _m −TA ₂ , D ₃ = TA _m −TA _{3 for} the access times TA ₁ , TA ₂ , ..., TA _m . _{, ..., D m = TA m} -TA m consisting of D _i
Considering (i = 2,3, ..., m), the memory request generation unit
The access history information from 110 is input to m-1 registers of the register AR0 of the first stage and the register of the stage shifted by D _i time from the first stage. In this embodiment, the main storage device 130
Has _three kinds of storage times A1, A2, A3 with three kinds of access times “14C”, “26C”, “30C”, m = 3, and D ₃ = TA ₃ −TA ₃ = 0. register _{D 2 = TA 3 -TA 2 =} 30C-26C = 4C , and the access history information is input, the first stage of the register AR0 and from the register AR0 time "4C" component, that is, the 2-bit-shifted register AR2 . The access history information A from the memory request generation unit 110 is input to this register AR0, and the access history information B output from the register AR1 and the access history information B from the memory request generation unit 110 are input to the register AR2. A gate circuit 121 for inputting and is provided, and access history information B or access information C is input. The access information output to the memory request generation unit 110 is the access information C that is the output of the register AR1 and the access information D that is the output of the register AR7.

The memory request generation unit 110 receives the memory request instruction information from the information processing unit 100, and further receives write data when the instruction information is write designation, and generates a memory request including a request, a read / write designation and an address. . If this memory request is a read designation, the reply timing when the newly generated memory request is sent, with the contents of the access information C and D output from the access history register 120 taken into consideration, has already been sent. After confirming that the reply timing of the memory request does not match, that is, the collision does not occur, the main memory device 130 sends the memory request to the main memory device 130 at the timing when the next memory request can be accepted, and at the same time, access History register 120
The access history information A or B is output to. Further, when it is recognized that the reply timing conflicts, the sending of the memory request is suspended until it is confirmed that there is no conflict. Further, when the memory request is the write designation, since there is no reply data, the memory request and the write data are unconditionally sent to the main storage device 130 at a timing at which the memory request can be accepted.

Here, in Table 1, when the memory request generated by the memory request generation unit 110, the access information C and D output from the access history register 120, and the memory request are sent from the memory request generation unit 110, The relation with the data set in the registers AR0 and AR2 is shown.

Table 1 shows that the memory request generation unit 110 generates a memory request at time t, refers to the access information C and D output from the access history register 120, and then sends or holds the memory request at time t + 2C. The setting data to the registers AR0 and AR2 of the judgment and access history register 120 is shown. When the memory request specifies write (W), the storage area to be accessed and access information C, D
The memory request can be sent out regardless of the contents of, and the setting data at that time is "0" to the register AR0 and the output of the register AR1 at the time t to the register AR2, that is, the contents of the access information C. is there. When the memory request is the read (R) designation, the access to the storage area A2 will be described as an example. In this case, if the access information C is "0", the memory request can be sent, and the register at this time can be sent. The setting data for AR0 and AR2 is
They are "0" and "1", respectively. Also, access information C
If the value is "1", the output of the memory request is suspended, and "0" and the content of the register AR1 at the time t, that is, the content "1" of the access information C are set in the registers AR0 and AR2, respectively. In addition, "-" in the table is indefinite and indicates that either "0" or "1" may be used.

Therefore, from the contents of Table 1, the access history register 12
As for the access information C output from the register AR1 of 0, a memory request for reading is sent to the storage area A3 before the time "2C", and the reply timing for the request is after "28C" from the present time, that is, This means that the main storage device 130 can receive the memory request next time, which is after the time “26C” from the timing after the time “2C”. Also, access history register 12
As for the access information D output from the register AR7 of 0, the memory request for reading is sent to the storage area A2 before the time “10C”, and the reply timing for the request is after the time “16C” from the present time, that is, This means that the main storage device 130 can receive the memory request next time, which is after the time “14C” from the timing after the time “2C”. Further, as for the access information D, a memory request for reading is sent to the storage area A3 before the time "14C", and the reply timing for the request is after the time "16C" from the present time, that is, the main memory device 130 It also indicates that the memory request can be accepted after the time “14C” from the timing after the time “2C”.

Next, the operation of this embodiment will be described.

First, referring to FIG. 3, considering the timing t of the cycle “2C”, the information processing unit 100 at times t ₀ , t ₂ , t ₃ , t ₄ , t ₆ , t ₈ , t _11.
It is assumed that the memory request instruction information is issued from. Table 2 shows the memory request transmission timing of the memory request generation unit 110 that has received the memory request instruction information and the contents held in the access history register 120 in correspondence with the timing shown in FIG.

Here, it is assumed that before time t ₀ , there is no memory request being processed in the main storage device 130 and the access history register 120 does not hold any access history information. Therefore, the contents of the access history register 120 at time t ₀ are all “0”.

First, at time t ₀ , the information processing unit 100 determines that the access time “30
When the memory request instruction information M ₀ of the read designation for the storage area A3 of C "is sent to the memory request generation unit 110,
The memory request generation unit 110 generates the memory request R ₀ and refers to the access information C and D. Here, since the access information C and D are both “0”, the memory request generation unit 110 sends the memory request R ₀ to the main storage device 130 at the next timing, that is, time t ₁ after the time “2C”.
At the same time, the access history information A is set to "1" in the register AR0 of the access history register 120 as shown in Table 1 above. Also, the contents of register AR1 are shifted to register AR2, but at time t ₀ , register AR1
Since the content of is 0, the register AR2 is set to 0. The reply timing RD ₀ for the memory request sent at the time t ₁ becomes the time t ₁₆ after the time “30C” as shown in FIG. 4, and the data set in the access history register 120 indicates that. It will be.

Subsequently, at time t ₂ , the memory request instruction information M ₁ for writing to the storage area A 2 is sent together with the write data WD ₁ , but in the case of writing, there is no reply data, so the time is unconditionally “2C”. Write data W at time t ₃ later
A memory request R ₁ is sent to the main storage device 130 together with D ₁ to perform writing. At this time, for the access history register 120, “0” is registered in the register AR0,
Is to AR2 the content "1" at the time t ₂ of the register AR1, are set, respectively. Furthermore, at time t ₃ , access time is “26C”
When the memory request instruction information M ₂ for reading is sent to the storage area A 2 of the memory request generation unit 110
Is adapted to generate a memory request R _2, that the access information C, and with reference to D are both "0", i.e. it was confirmed that reply timing for the memory request R ₂ does not collide with the reply timing other requests Then, at time t ₄ , the memory request R ₂ is sent to the main storage device 130.
Send to. Reply timing RD ₂ for the memory request R _2, as shown in FIG. 4, the time t ₁₇ after the time "26C" from time t _4. Further, the contents of the access history register 120 at the time t ₄ are the setting data at the time of sending the memory request R ₂ in Table 1, "0" as the access history information A to the register AR0, and access to the register AR2. Since the history information B is "1", the registers AR2 and AR3 hold "1". Then, at this time t ₄ , when the memory request instruction information M ₃ for the read designation for the storage area A ₃ is transmitted, the memory request generation unit 110 generates the memory request R ₃ at the time t ₅ . In this case for reading the specified memory requests to storage A3 may send the access information C, the memory request regardless of the content of D R ₃ in Table 1. Reply timing RD for the memory request R _{3 3} is, as shown in FIG. 4, the time t ₂₀ after the time "30C"
Becomes Further, the setting data to the access history register 120 when the memory request R ₃ is sent is the access history information A to the register AR 0 is “1”, and the register AR 2 is the content of the register AR 1 at the time t _4. is there. Therefore, the contents of the access history register 120 at time t _5, the register AR0, AR3 and AR4 is set to "1".

Subsequently, at time t ₆ , when the memory request instruction information M ₄ for reading the storage area A 1 is transmitted, the memory request generation unit 110 generates the memory request R ₄ and refers to the access information C and D. , After confirming that the reply timings do not conflict, the memory request R ₄ is transmitted at time t ₇ . Reply timing RD ₄ for the memory request R _4, as shown in FIG. 4, the time "1
4C is a time t ₁₄ after ". The contents of the access history register 120 at time t ₇ register AR2, AR5 and AR6 is" 1 ".

Next, when the memory request instruction information M ₅ of the read designated for storage A1 at time t ₈ is sent, the access information together with the memory request generator 110 generates a memory request R ₅ C, refer to D. At this time, the contents of the access history register 120 are registers AR3, AR6 and AR7, that is, the access information D is "1". In this case, sending at time t ₉ the memory request R ₅ for storage A1 in Table 1 is held pending, access history register at time t ₉
The contents of 120 are "1" in registers AR4 and AR7. Therefore, at this time as well, since the access information D is "1", the transmission of the memory request R ₅ at time t ₁₀ is also suspended. Then, at time t ₁₀ , the contents of the access history register 120 are referred to again, but here, only the contents of the register AR5 are “1”, and the access information C and D are both “0”. It is determined that the timings do not conflict, and the memory request R ₅ will be transmitted at the next time t ₁₁ . The setting data for the access history register 120 at this time is “0” for the register AR0, the content “0” for the register AR1 at time t ₁₀ for the register AR2, and the setting data for the access history register 120 at time t ₁₁ . Only the contents of register AR6 are "1". Furthermore, at this time, storage area A1
When the memory request instruction information M ₆ is sent to
The memory request generation unit 110 generates the memory request R ₆ and refers to the access information C and D to confirm that the reply timing does not conflict, and then sends the memory request R ₆ at time t ₁₂ . This memory request
Reply timing RD ₆ for R ₆ is a time t ₁₉ after the time "14C".

FIG. 5 is a block diagram showing a second embodiment of the present invention.

In this embodiment, the memory request generation unit 110 includes a selector 111, and receives the access information from the access history register 120 via the selector 111. Main memory 130 is memory request input port 131
And a write data input port 132 and a reply data output port 133.
Storage area of A ₁ , TA ₂ , ..., TA _m (TA ₁ <TA ₂ <... <TA _m ) A1, A
2, ..., Am. The access history register 120 is composed of n stages of registers AR0, AR1, ...
It is a shift register that shifts for each C ", and a gate circuit is provided at the input ends of the third-stage register AR2 to the last-stage register ARn-1, and the output from each previous-stage register,
Alternatively, the access history information from the memory request generation unit 110 is input. This access history register 120
Is storage A2 in the main storage device 130 described above, ..., Am access time _{TA 2, TA 3, ...,} D with respect to _{TA m 2 = TA m -TA 2} , D 3 = TA m -TA 3 , …………… Considering D _i (i = 2,3, ..., m) such that D _m = TA _m −TA _m , the first-stage register AR
M− between 0 and the register of the stage shifted by D _i time from the first stage
Access history information is input to one register. This access history information is directly input to the register AR0 of the first stage from the memory request generation unit 110, and for the registers of the other stages after the register AR2, it is mainly input by the switching unit 122 provided in those input units. After switching according to the number m of storage areas in the storage device 130, it is input from the memory request generation unit 110 to the register of the necessary stage. Further, the access information output from the access history register 120 to the memory request generation unit 110 is sent to the selector 111 of the memory request generation unit 110 as the output of the registers after the second-stage register AR1. The required access information is selected according to the number m of storage areas and their access times.

For example, as in the first embodiment described above, the number of storage areas is three, and their access times are "14C", "26C", "30".
If it is "C", the number of stages of the access history register 120 is "30C-
Since "14C = 16C", eight stages are required, and the switching unit 122 performs switching so that access history information is input to the register AR2 in the third stage. Also, the memory request generator
The selector 111 of 110 selects the output of the second-stage register AR1 and the output of the eighth-stage register AR7 of the access history register 120.

Also, the number of storage areas has been changed to four, A1 to A4, and the access times are "14C", "18C", "26C", and "30", respectively.
If it is C ", similarly, a register of 8 stages is required, and the switching unit
122 switches so that the access history information is input to the third-stage register AR2 and the seventh-stage register AR6, and the selector 111 of the memory request generation unit 110 causes the access history register 120 to select the second-stage AR1 and 6 of the access history register 120. The output from the register AR5 in the second stage and the register AR7 in the eighth stage is selected. And storage area A
The access history information for each memory request when a read-specified memory request is sent to 2, A3, A4 is
In the case of storage area A2, to the register AR6 in the seventh row of the access history register 120, in the case of storage area A3, to the register AR4 in the third row,
In the case of the storage area A4, the data is input to the first-stage register AR0. In this case, the memory request generator 110
As for the output of the register AR1 of the access history register 120 selected by the selector 111, the memory request for reading is sent to the storage area A4 at the access time “30C” before the time “2C”, From time “28C”,
That is, the time from the timing after the time "2C" after which the main memory device 130 can accept the memory request
It indicates that the reply timing is after 6C ".
Similarly, as for the output of the register AR5, the memory request of the read designation for the storage area A4 before the time "10C" and the read designation for the storage area A3 of the access time "26C" before the time "6C" are designated. Memory request is sent, and the main memory 130 can receive the memory request next time from the timing "2C" after the time "18C"
It indicates that the later is the reply timing. In addition, the output of register AR7 is
Before "C", or before memory "A3" at time "10C", or at memory time "18C" before memory "A2" at time "2C", the specified memory request is sent. Both indicate that the main memory 130 is the reply timing after the time “14C” from the timing after the time “2C” at which the main memory device 130 can receive the memory request. Storage area A3,
The output of the register AR5 is the storage area A2, the output of the register AR7 is the storage area A1, and there is a possibility that the reply timing of the memory request for each storage area may collide with the reply timing of the already sent memory request. It will be.

As described above, according to the present embodiment, even when the number of storage areas in the main storage device 130 or its access time changes, the switching unit 122 of the access history register 120 and the selector 111 of the memory request generation unit 110. It can be dealt with by operating.

FIG. 6 is a block diagram of the third embodiment of the present invention.

In this embodiment, a memory request ID detection unit 140 is provided between the memory request generation unit 110 and the access history information, and the main storage device 130 stores the storage area A1 with access time “14C” and access time “26C”. It has a storage area A2 and a storage area A3 with an access time of "30C". The memory request generation unit 110 similarly generates a memory request to the main storage device 130, and refers to the ID information A, B, C output from the memory request ID detection unit 140 to confirm that the reply timing does not conflict. And then send a memory request,
At that time, 2-bit coded access history information is output to the access history register 120. The access history register 120, as shown in FIG.
It is a shift register composed of registers (AR0 to AR7) of stages, and this shift timing is time "2C". Further, the access history information from the memory request generation unit 110 is stored in the register AR0 at the first stage, and the outputs of the register AR1, the register 5 and the register AR7 are sent to the memory request ID detection unit 140 as the access information A, B, C, respectively. Sent out. The memory request ID detection unit 140 receives the access information A, B, C from the access history register 120, detects the reply timing for the read-specified memory request sent by the memory request generation unit 110 from the information, ID information A, B, C indicating the reply timing
Is output to the memory request generation unit 110.

Here, Table 3 shows the relationship between the access history information and the ID information A, B, C.

In Table 3, the memory request generation unit 110 generates a memory request at time t, and the memory request ID detection unit 14
After referring to the ID information A, B, and C, which is the output of 0, it is shown at time t + 2C whether the memory request is sent or held and the access history information which is the setting data to the access history register 120. . First, when the memory request is the write designation (W), since there is no reply data from the main storage device 130, the memory request can be sent regardless of the contents of the ID information A, B, C, and the access history information at that time is " 00 ”. Next, in the case of the read (R) designation, for example, when the storage area to be accessed is considered as A2, if the content of the ID information A is "0", the memory request can be sent regardless of the ID information B and C, The access history information at that time is "0
1 ”. If the content of the ID information A is "1", I
The output of the memory request is suspended regardless of the D information B and C, and the access history information at that time is "00". In addition,
In the table, "-" indicates indefinite, and "0" or "1" may be used. Therefore, the ID information A indicates the presence / absence of a collision with the reply timing relating to the already sent memory request when the read-specified memory request is sent to the storage area A2. In this case, the ID information A is before the time "2C", that is, at the time t-2C.
A memory request for reading is sent to the storage area A3, and the reply timing is "28C" after the time t, that is, the time "2C" when the main memory device 130 can accept the next memory request. It indicates that the time is "26C" after the later timing. Also,
The ID information B, C indicates whether or not there is a collision with the reply timing relating to the already sent memory request when the read-specified memory request is sent to the storage area A1. In this case, the ID information B is before the time "10C", that is, at time t-
A memory request for reading is sent to the storage area A2 in 10C, and the reply timing is "16C" after the time t, that is, the time "2C" when the main memory device 130 can accept the memory request next time. "It indicates that the time is" 14C "after the later timing.
The information C indicates that the read-specified memory request is sent to the storage area A3 before the time "14C", and the reply timing is also after the time "14C".

As described above, in this embodiment, the memory request generation unit 110
The access history information output from the memory request ID detection unit 140 is held in the access history register 120 for a certain period of time and is similarly output as 2-bit access information.
The memory request ID detector 140 decodes the access information, and sends it to the memory request generator 110 as ID information indicating the reply timing relating to the already sent memory request.

FIG. 8 is a block diagram of the fourth embodiment of the present invention.

In this embodiment, the memory request generation unit 110 includes a selector 111, and receives the ID information from the memory request ID detection unit 140 via the selector 111. The access history register 120 is a 2-bit 8-stage shift register as in the case of the third embodiment described above, and the outputs of the registers AR1 to AR7 excluding the first stage register AR0 are used as access information for the memory request ID detection unit. Connected to 140. Also, the memory request ID detection unit 140
The output corresponding to each access information from the access history register 120 is connected to the selector 111 of the memory request generation unit 110 as ID information. The memory request generation unit 110 controls the selector 111 to select necessary ID information according to the access time of the storage area included in the main storage device 130. For example, as described above, if there are three storage areas A1, A2, and A3 and the access times are "14C", "26C", and "30C", respectively, the access history register
Select the ID information corresponding to the output of the registers AR1, AR5, AR7 of 120.

Also, the access time of the storage area has been changed
If 1, A2 and A3 are "14C", "20C" and "30C" respectively, the reply timing can be predicted by selecting the ID information corresponding to the outputs of the access history register 120 registers AR2, AR4 and AR7. You can As described above, according to this embodiment, it is possible to deal with the change of the access time of the storage area provided in the main storage device 130.

FIG. 9 is a block diagram of the fifth embodiment of the present invention.

In this embodiment, the memory request ID detector 140 includes a selector 141. Also in this case, similarly, the outputs of the registers AR1 to AR7 from the access history register 120 are connected to the memory request ID detection unit 140, and the memory request ID detection unit 140 controls the selector 141 to respond to the access time of the storage area. Access information you have selected. Further, in this embodiment, since there are three storage areas A1, A2, and A3, the memory request ID detector 140 outputs three pieces of ID information to the memory request generator 110.

Here, assuming that the access times of the storage areas A1, A2, and A3 are "14C", "26C", and "30C", respectively, the selector 141 selects the output of the levels AR1, AR5, and AR7 of the access history register 120. Become. When the access time is changed to be "14C", "20C", "30C", the outputs of the registers AR2, AR4 and AR7 are selected.

Therefore, also in the present embodiment, it is possible to deal with the change of the access time of the storage area in the same way as when the memory request generation unit 110 is provided with the selector.

〔The invention's effect〕

As described above, according to the present invention, when the memory request generation unit sends a memory request to the storage device, the access history is held in the access history register for a certain period of time so that the next memory request is stored in the register. It is possible to send a memory request to the storage device after confirming that the reply timing does not conflict by referring to the access history of the above, and it is determined as an access history register without significantly changing the conventional access control. Hierarchical structure of access time in a pipeline-controlled storage device, which has been the most orthodox, performance, and cost effective in the past, simply by adding a memory request generator that has functions and the smallest hardware. It becomes possible to adopt Even if the location of the access time is changed, there is an effect that it corresponds without significantly changing the hardware.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the information processing apparatus of the present invention, FIG. 2 is a block diagram showing the configuration of the access history register 120, and FIG. 3 is an information processing unit 100 outputting memory request instruction information. FIG. 4 is a timing chart showing an example of timing, and FIG. 4 is a memory request generation unit for the output timing of the memory request instruction information in FIG.
Timing charts showing the output timing of the memory request of 110 and the reply timing of the main storage device 130, and FIGS. 5 to 9 are block diagrams showing other embodiments of the present invention. 100 ... Information processing unit, 110 ... Memory request generation unit, 111,
141 ... Selector, 120 ... Access history register, 121 ... Gate circuit, 122 ... Switching unit, 130 ... Main storage device, 131 ... Memory request input port, 132 ... Write data input port, 133 ... Reply data output port, 140 ... Memory Request ID detector.

Claims (2)

[Claims] 1. When a plurality of storage areas having different access times are provided and a memory request from the outside reads data, the reply timing is set after the access time of the storage area storing the designated data. In an information processing apparatus that includes a storage device that outputs the data as reply data and pipeline-controls the storage device, the storage devices include TA ₁ , TA ₂ , ..., TA _m (TA ₁ <TA ₂ <... < T
It has m kinds of storage areas with an access time of (A _m ), and sends memory request instruction information including read / write designation and address designation when storage device access is required, and when writing is designated. Is composed of an information processing unit that sends write data and sends it, and a shift register that shifts at regular intervals. When a memory request for reading is sent, access history information indicating the reply timing for the request is sent. , From the first stage of the shift register to the access times TA ₁ , TA ₂ , ..., TA _m of the storage device, D ₂ = TA _m
−TA ₂ , D ₃ = TA _m −TA ₃ , ..., D _m = TA _m −TA _m D _i (i
= 2,3, ..., m) The access history register held in m-1 registers shifted by the time, the memory request instruction information sent by the information processing unit, and the write data at the time of writing are read / read. A memory request including a write designation and an address designation is generated, and if the request is a write designation, write data is sent to the storage device together with the memory request, and if a read designation is specified, a storage area related to the address designated by the request. From the access time of and the access history information related to the already sent memory request stored in the access history register, the reply timing when the generated memory request is sent matches the reply timing related to the already sent request. If it is determined that they do not match, the request is stored in the storage device. It has a memory request generation unit that sends the access request, registers access history information related to that request in the access history register, and if it determines that they match, holds the sending of the memory request and waits until it is determined that they do not match. An information processing device characterized by: 2. When a plurality of storage areas having different access times are provided and a memory request from the outside reads data, the reply timing is set after the access time of the storage area storing the designated data. In an information processing apparatus that includes a storage device that outputs the data as reply data and pipeline-controls the storage device, when access to the storage device is required, memory request instruction information including read / write designation and address designation is transmitted. When a write request is made, it is composed of an information processing unit that sends write data and sends it, and a shift register that shifts at regular intervals.When a read-specified memory request is sent, the reply timing for that request is sent. Access history register that holds multiple bits of access history information indicating , A memory request ID detection unit that decodes the multi-bit access history information held by the access history register and outputs ID information indicating the reply timing for the already sent memory request, and the memory request sent by the information processing unit In response to the instruction information and the write data at the time of writing, a memory request including read / write designation and address designation is generated. When the request is write designation, the write data is sent to the storage device together with the memory request, and the read designation is performed. If there is, the reply timing when the generated memory request is sent from the access time of the storage area related to the address specified by the request and the ID information related to the already sent memory request output by the ID detection unit. And the reply timing related to the already sent request match If it is determined that they do not match, the request is sent to the storage device, and multiple-bit access history information related to the request is registered in the access history register, and it is determined that they match. And a memory request generation unit that waits until a non-coincidence is determined by suspending the transmission of the memory request.