JPH0638501B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to an MES-FET (field effect transistor having a metal-semiconductor structure using a Schottky barrier) and an M-FET.
The depletion region control type field effect transistor (hereinafter, referred to as DIS-FET) having the characteristics of IS-FET (insulating gate type field effect transistor having a metal-insulator-semiconductor structure) is also provided.
(Referred to as “)”.

[Outline of Invention]

The DIS applied to the nonvolatile semiconductor memory device of the present invention
In the -FET, the conventional MIS-FET simply miniaturized the size of the element, but the pattern is changed by the short channel effect in which a leak current occurs that flows unintentionally between the source and the drain in the off state. The semiconductor device has a speed equal to or higher than that of a MIS-FET having a limit that cannot be scaled down (miniaturized), that is, a channel length of 0.1 to 1 μ, and has an effect not seen in the past.

The DIS-FET used in the nonvolatile positive memory device of the present invention
The basic characteristics are that it operates at low voltage (0.1-2V) and bulk mobility (μ _e 〜 1500).
_{^{cm 2 / VS, μ i ~500cm}} 2 / VS) utilizing same pattern 3-6 times faster than the dominant MIS-FET is surface mobility conventionally known to be perforated at the scale, the depletion layer The barrier is controlled by the work function of the gate electrode or the impurity level, the complementary type can be manufactured on the same substrate as compared with the MES-FET, and the use of silicon nitride for the insulating film provides higher reliability than the MES-FET. If it has heat resistance, it is a self-aligned MIS,
-Because the characteristics of FET can be used as they are, and bulk majority carriers are used, the channel length is 0.1 μm.
In addition, the leakage of the subthreshold current is extremely small, and well-known LSI technology and CAD technology can be directly applied to system design.
Since it has heat resistance in the DIS-FET region, multilayer wiring is possible and it can be applied to nonvolatile RAM.

It has an extremely great effect that it can have all of the many features desired by the IC, LSI, and VLSI industries up to now.

[Conventional technology and its problems]

Conventionally, the DIS used in the nonvolatile semiconductor memory device of the present invention
A MES-FET is known as a transistor having a structure relatively similar to that of a -FET. This is shown in FIG. 1 in a longitudinal sectional view.

In the MES-FET shown in FIG. 1, the substrate semiconductor (1) has a silicon semiconductor region (2) of the opposite conductivity type formed by an ion implantation method of light doping rather than the source (5) and the drain (6). Further, a Schottky barrier of platinum (3) is formed on this semiconductor region (2). This Schottky barrier creates a depletion layer in the semiconductor region and the source (5)
It is intended to control the current flowing from the drain to the drain (6).

However, in this MES-FET structure, platinum is in direct contact with the silicon semiconductor semiconductor region (2), so there is a manufacturing variation. Further, the P-channel type cannot be used conventionally. In addition, it has no heat resistance. Electrode (3) and source (5),
Since the drain (6) is easily short-circuited, there are many drawbacks such as the need to provide the void (60).

[Problems to be Solved by the Present Invention]

The nonvolatile semiconductor memory device according to the present invention is the MES-FE.
Another object is to provide a non-volatile semiconductor memory device configured by using a DIS-FET, which is intended to eliminate the above-mentioned drawbacks while taking advantage of the characteristics that T uses low voltage operation and bulk mobility.

[Embodiment] FIG. 2 shows D used in the nonvolatile semiconductor memory device of the present invention.
The longitudinal cross-sectional view of the 1st example of IS-FET is shown.

In FIG. 2, a semiconductor such as silicon (crystal orientation (100)
The P ⁻ (ρ ≧ 10 Ωcm or more) type was used as the substrate (1). Further, this upper surface is selectively masked with silicon nitride or the like, and selectively oxidized at a known high pressure (about 10 to 15 atm) at 800 to 1000 ° C. to a thickness of 0.5 to 2 μm to form a field insulator ( 7) was formed. Furthermore, a P-type region (1
0) is formed to a thickness of 0.3 to 1 μm by an ion implantation method, and in addition, a semiconductor region (2) is formed on the upper surface in an amount of 50 to 30 μm.
It was produced by using the second ion implantation method to a thickness of 00Å, especially 100 to 500Å. This semiconductor region (2) forms a depletion layer, and the depletion layer is formed on its lower surface, that is, the semiconductor region (2) and P
It must be lightly doped so that it can be easily spread to the bonding surface of the mold region (10) by the potential of the electrode. The impurity concentration was controlled to 10 ^{14 to} 3 × 10 ¹⁶ cm ^-3 . Further, the source (5) and the drain (6) were formed by the third ion implantation to have a concentration of 10 ¹⁷ to 10 ¹⁹ cm ⁻³ . The distance between the pair of impurity regions was 0.1 to 1 μm. The source (5) and the drain (6) are manufactured by, for example, 0.1 to 1 μm in the normally-off state of the semiconductor region (2) and the lower side thereof.
A semiconductor layer that prevents the occurrence of a short channel effect in which the leak current of the order of 10 ^-9 to 10 ^-12 A unintentionally flows between the source and the drain with a shortened m and the channel length (1
The production of 0) and the order thereof may be changed.

In this DIS-FET, after the surface of the semiconductor layer is sufficiently cleaned, a silicon nitride film is applied to the upper surface for 2 to 200 times.
It was formed to a thickness of Å. This silicon nitride is manufactured by the following 2
Used one. That is, the plasma nitriding method can be used. This plasma nitriding method uses 0.1 to 0.1% of this semiconductor.
Soaked in atmosphere at a pressure of 10 torr, soaked the atmosphere of ammonia (NH ₃₎ or nitrogen mixed gas (N ₂₎ and hydrogen (H _2), in addition 5～5000MH _z example of this gas 1
It was induced plasma at 3.56MH _z. The surface of a semiconductor is nitrided by chemically activating a reactive nitride gas.

A film thickness of 2 to 30Å can be obtained when the temperature of the semiconductor substrate is room temperature to 300 ° C, and a film thickness of 20 to 200Å can be obtained at 300 to 800 ° C.

The DIS-FET is characterized by using such a silicon nitride film and being able to substantially function as a DIS-FET as a modification of the MIS-FET even if it is thin enough to pass the nitride film tunnel current.

The film formed by such plasma nitriding method is Si ₃ N ₄
The silicon nitride film has the above structure, but when natural oxide is present on the semiconductor surface, it has the structure of SiO _x N _y .

A nitride film may be formed by implanting nitridation near the surface of the semiconductor by an ion implantation method instead of the plasma nitriding method.

Further, instead of such an insulating film, a semi-insulating film can be used. The semi-insulating film is mixed on the surface of the semiconductor at a pressure of 0.001 to 1 torr at a ratio of SiH ₄ / NH ₃ / H ₂ = 1 / 0.5 to 10/0 to 50, and vapor phase growth is performed on the surface where the semiconductor is formed. (500-800 ° C). In addition, the plasma vapor phase method (room temperature to 500 ℃) can be used for 2-10
It may be formed to a film thickness of 0 Å. In such a case Si ₃ N _4-x (0.
5 <X4), and a semi-insulating film was formed.

In the DIS-FET, the interface state density in which such an insulating film exists is 3 × 10 ¹⁰ cm ⁻² or less, particularly 1 × 10 ¹⁰ cm ⁻² or less, and the drift of V _TH due to the interface charge is 0.1 V or less. Particularly, it is extremely important that the voltage is 0.01 V or less.

When the interface state is large, the bending of the energy band generated in the substrate semiconductor by this level exceeds that of the electrode, and the C / DIS-FET (complementary DIS-F
ET) composition becomes difficult to make.

In the example of the DIS-FET, a semiconductor doped with 10 ¹⁸ cm ⁻³ or more of boron on the insulating or semi-insulating film (8) as a next step is subjected to a low pressure gas phase method or a plasma gas phase method in an amount of 0.03 to 0. An electrode (9) was obtained by forming the electrode (9) to a thickness of 0.3 μm, especially 0.1 μm.

In the example of the DIS-FET, since it is an N channel, the electrode (9) is of P type. Then, a depletion layer (11) (DEPLATION LAYER) is generated in the semiconductor region (2) immediately below the electrode without applying a voltage to the electrode (9). Since the lower surface of this depletion layer reaches the lower side (bottom surface of the semiconductor region), it is important to create a normally-off state.

Furthermore, in the example of the DIS-FET, since the insulating or semi-insulating film (8) is made of silicon nitride, the boron in the electrode is formed on the semiconductor region (8) due to the extremely rough masking action against the impurities. It has not reached the surface due to diffusion. Further, since this impurity does not enter the silicon nitride, the electric conduction in this film is only the leak current due to the tunnel current or the floor node Heim current due to its thin film thickness, and the current value does not fluctuate. There wasn't. 2 or more insulating or semi-insulating film (8)
Since it is as thin as 200 Å, especially 30 to 80 Å, the work function potential of the gate electrode could be directly applied to the semiconductor region for the first time.

In particular, this insulating film or semi-insulating film (8) is 2 to 200
Å, especially 30 to 80Å, is because of the relationship shown in FIG. In particular, the thickness of the gate insulating film is made variable, the semiconductor electrode is of P ⁺ type, and the N-channel type DIS-
In the FET, when the impurity concentration of the channel formation region of the substrate is 5 × 10 ¹⁵ cm ⁻³ of N ⁻ , there is a difference of 0.8 V between the Fermi level of the gate electrode and the Fermi level of the substrate. In order to eliminate this difference, the energy band on the surface of the semiconductor is bent, and they try to eliminate the difference between them. As a result, the difference between the inside of the semiconductor and the surface of the semiconductor is large.

However, if an insulating film is interposed between the gate electrode and the semiconductor surface, a potential drop occurs in this dielectric portion as the thickness increases, and as a result, the bending of the energy band on the semiconductor surface becomes smaller. . This relationship is shown in FIG.

In other words, from the relationship of this thickness, it is necessary to bend the energy band on the surface of the semiconductor within a range that cannot be practically used,
If it is set to Å or less, especially 80 Å or less, a difference of 0.3 V or more can be made. However, if the thickness is too thin, a tunnel current will flow too much between the gate electrode and the substrate, so it has been found that the tunnel current does not exceed 30 Å. It is obvious that this thickness can be achieved only when the interface state density is 3 × 10 ¹⁰ cm ⁻³ or less in the present invention and the influence of this level is sufficiently small.

In the example of the DIS-FET, when the insulating or semi-insulating film (8) has a pinhole, the impurity of the electrode diffuses through the pinhole to the upper part of the semiconductor region, where
Make a PN junction. In this case, a locally formed so-called junction type FET (JUNCTION TYPE FET or JFET) can be formed.
Therefore, locality is generated in the expansion of the depletion layer, and the frequency characteristic is deteriorated. However, this structure DIS-FET
In case of such pinhole, it is this DIS
-The feature is that it does not completely deny the operation of the FET.

In the DIS-FET, the source (5),
Electrode leads (15), (16) for the drain (6)
Was manufactured by making ohmic contact at the electrode part with a semiconductor or metal of the same conductivity type. 2 (B) and 2 (C)
Shows the energy band diagram for AA ′ in FIG. 2 (A).

FIG. 2 (B) shows that the semiconductor substrate (1) or (10) in FIG. 2 (A) corresponds to (10 ′) or the semiconductor region (2) corresponds to (2 ′). Alternatively, (8 ') corresponding to the semi-insulating film (8) and (9') corresponding to the electrode (9) are shown by energy band widths.

(11 ') is a depletion layer. Since the depletion layer (11 ') is present, the band becomes convex upward, and this DIS-FET has N
It is a channel and electrons cannot pass from the source (5) to the drain (6). However, as shown in FIG. 2 (C), the electrode (9) has a voltage of 0.1 to 2V, for example 0.3V, which is much lower than the voltage of 2 to 20V of the IG-FET (insulating gate type field effect transistor). By applying such a low positive voltage, the energy band of (2 ') is lowered to the lower side (12).
A current can flow through the part. That is, the depletion layer controls the electrical conduction normally.
Since it is an off-type MIS type device, the semiconductor device of the present invention can be used as a DIS-FET (DEPLETION LAYER CONTROLLED ME).
TAL (SEMICONDUCTOR) -INSULATION -SEMICONDUCTOR TYPE
FIELD EFFECT TRANSISTOR).

The electron is a bulk carrier, to IG-FET of the surface conduction as the mobility ^{_{μ e ≒ 300 ~500cm 2 / VS}} , have a μ _e ≒ 1300~1500cm ² / VS and 3-5 times the mobility . The fact that this bulk mobility is used in the DI
This is an extremely large feature of S-FET.

Another feature is that the P-type semiconductor region having a higher concentration than that of the P ⁻ type substrate is formed below the N type region forming the channel, so that short channel leakage can be prevented from occurring between the source and the drain. It was Therefore, the channel length can be reduced to 0.1 to 1 μm, which is 1 μm or less. The gate electrode is an N-channel type DIS-FET.
In, a P-type semiconductor electrode was used. This is platinum,
Tungsten, gold, molybdenum, tantalum, titanium, chromium, nickel or alloys or mixtures thereof (eg nichrome, molybdenum silicide, tungsten.
Similar effects can be expected even with (silicide).

Although the conventional MES-FET can use only platinum for the electrode, the DIS-FET conversely insulates a metal or an N ⁺ -type semiconductor having a small work function or a semi-insulating film is interposed between the electrode and the semiconductor region. Because it is done, it can be implemented.

In this case, a P-channel type DIS-FET can be formed.
In such a case, the metal is required to be a metal having a work function smaller than 4 eV, such as aluminum, magnesium, beryllium, or value. Table 1 summarizes these.

3A and 3B show examples of other DIS-FETs applicable to the nonvolatile semiconductor memory device of the present invention.

In FIG. 3 (A), a field insulator (7) is provided on the N-type semiconductor by a selective oxidation method or the like, and the semiconductor region (2) is changed to a P ⁻ type by the first ion implantation method. 50
Formed to a thickness of ~ 3000Å.

After that, a silicon nitride film having a thickness of 2 to 200 Å is formed on these surfaces in the same manner as in the first example, and then an opening is formed between the source (5) and the drain (6) to form the upper surface thereof. Amorphous or polycrystalline non-single crystal semiconductor silicon is formed on the entire surface. Further, this semiconductor film (0.03 to 0.3 μm) is selectively oxidized to form silicon oxide except the electrodes and leads.

This selective oxidation is performed even if oxygen is ion-implanted into a portion to be oxidized, or if a silicon nitride film having a masking action is formed on portions to be electrodes and leads and is oxidized by an oxidizing gas such as water vapor. Good.

Thus, the field insulator (14) is formed. Then, a P ⁺ -type impurity such as boron is added to the source (5), the drain (6) and the leads (15) and (16) at a concentration of 10 ¹⁷ to 10 ²¹ cm ⁻³ to obtain P ^+. Of the semiconductor, and phosphorus is selectively added to the electrode (9) 10 ¹⁸ ~
Add to a concentration of 10 ²² cm ^-3 . This impurity is 500-1000 ℃
Especially, the electrodes (9), leads (15) and (16) are thin enough to be diffused at a temperature of 600 to 700 ° C.
The thickness may be about μm. After that, in order to selectively increase the conductivity on these electrodes and leads, metals (19) and (19 ') were formed in a multiple structure to a thickness of 0.1 to 0.5 [mu] m. This metal may be a refractory metal such as tungsten or molybdenum, or a metal such as aluminum or titanium.

In order to perform multiple wiring on this upper surface, a polyamide-based organic film such as PIQ may be formed on this upper surface, and each electrode thereof, and further, a second wiring may be formed on the upper surface thereof.

An example of this DIS-FET is a P-channel type DIS-FE.
T, but the source (5), the drain (6) and the electrode (9) are formed by one mask, and the source (5) and the drain (6) and their respective electrodes and leads (1
5) and (16) are made of the same main component material and complete ohmic contact is achieved from the same material, the electrode,
The feature is that the leads are also selectively oxidized.

Needless to say, a material corresponding to the P-channel DIS-FET of Table 1 in the first example may be used instead of this electrode (9).

FIG. 3 (B) is a modification of part of the manufacturing process of FIG. 3 (A). FIG. 3 (B) shows an N-channel type DIS-FET, but at the same time as the semiconductor region (2) in FIG. 3 (A), the source (5), drain (6) and their electrodes in FIG. 3 (B) are also shown. The same impurities are added to the leads (15) and (16).

By doing so, the P-channel DIS-FET (Fig. 3A) and the N-channel DIS-FET (Fig. 3B) are integrated on the same substrate (1) as shown in Figs. You can make it by converting.

As described above, since the conventional MES-FET uses the Schottky structure electrode, only the N-channel type can be formed, but a complementary DIS-FET (C / DIS-FET or C / DIS) can be formed. It was This C / DIS-
The FETs may be connected in series or in parallel depending on the application of the circuit.

The other manufacturing method of FIG. 3 (B) is the same as that of FIG. 3 (A).

In the above semiconductor device, when V = 0.5, td of 0.1 to 0.5 nsec can be obtained, and extremely high speed operation is possible.

FIG. 4 shows a non-volatile semiconductor memory device using the first DIS-FET.

FIG. 4 (A) shows the structure of the non-volatile semiconductor memory device.
Figure (B) shows the equivalent circuit.

In FIG. 4B, the nonvolatile semiconductor memory device is provided with a floating electrode (49 ') and a control electrode (49). In both figures, the floating electrode (4
9 ') corresponds to the first electrode (9') of the nonvolatile semiconductor memory device, and the control electrode (49) corresponds to the second electrode (9).

The structure of the nonvolatile semiconductor memory device of the present invention will be described with reference to FIG.

In FIG. 4 (A), the first electrode (9 ') is of P ⁺ type and is surrounded by an insulating film (39) made of a silicon nitride film having a thickness of 20 to 200Å on the upper side surface thereof. A second control electrode (9) is provided on the upper surface of the insulating film (39).

The structure of this non-volatile semiconductor memory device is a further development of the non-volatile semiconductor memory device of the invention by the present inventor (Japanese Patent Publication No. 50-36955 / 8886343).

What is particularly important is that the floating electrode (9) which is the first control electrode is doped with impurities, and the Fermi level due to the doping forms a depletion layer in the semiconductor region (2) immediately below.

In order to control the thickness of the depletion layer, ON / OFF is controlled by further applying a positive or negative potential to the first electrode (9) by a tunnel current.

This non-volatile semiconductor memory device has a write voltage of 3 to
The read voltage is 10V, for example 5V, the read voltage is 0-2V, for example 0.5V, the write voltage of the conventionally known voltage is 20-50V, and the read voltage is 1/10 of 8-10V. Is. Further, since the write voltage is as low as 2 to 10 V, no local charge is generated in the film (8) under the second electrode (9 ') and it is not deteriorated as a result, so that it can be used as a nonvolatile RAM. it can.

Further, the second control electrode (9) and the drain (6) are separated from each other, and the deterioration of the nonvolatile semiconductor memory so far has a bad influence on the charges trapped in the insulating film near the drain. However, the nonvolatile semiconductor memory of the present invention is characterized in that such charges are not captured because the silicon nitride film is used as the insulating film and the drain is provided separately.

As is clear from the above description, the present invention has a known structure M
It is similar to IS-FETs or MES-FETs and may give the feeling of combining them. However, the DIS-FET used in the non-volatile semiconductor memory device of the present invention is intended to bring out only the respective advantages, and the gate electrode is the MIS-FET.
Similarly to the above, the channel region was formed in the same manner as the MES-FET. The thickness of the insulating film or semi-insulating film is extremely thin, 2 to 200 Å, especially 30 to 80 Å, so that the MIS-FET has leakage and low voltage below the threshold voltage (V _th ). Due to the use of voltage (3 to 1 V) and the lower limit of V _th being 0.8 to 1 V, it was not possible to make V _G and V _E below 2 V in reality.

However, in the present invention, such V _th can be substantially and inherently given by the material work function of the electrode or (electron affinity) + (Fermi level). For this reason, the operating voltage can be made extremely small as 0.1 to 2 V and scaling is possible accordingly, and since there is no short channel effect, the channel length can be shortened to 0.1 to 1 μm. became.

Therefore, it is a very industrially important semiconductor device that can make td≈0.01 to 0.5 ns. In the above description, even if the insulating or semi-insulating film is silicon nitride, it can be put to practical use. Needless to say, the semiconductor is not limited to silicon and may be a III-V compound semiconductor such as germanium, silicon carbide, GAAlAs, GaP or a II-VI compound semiconductor such as CdS.

It is preferable that the electrode is a semiconductor and has the same main component as that of the substrate because of ease of manufacturing. However, it goes without saying that another semiconductor or a semiconductor having a wide energy band width to which oxygen or nitrogen is added to further increase the depletion layer may be used.

In particular, the semiconductor region is a silicon single crystal, and the electrode has an energy band width of 5 to 50 mol% of oxygen or nitrogen or 0.01 to 3 mol% of P ⁺ or N ⁺ type impurities. Since the depletion layer becomes 1.5 to 2.0 eV instead of 1.0 eV, the depletion layer can be further widened, so that the practical use voltage can be increased to 0.5 to 4 V from 0.1 to 2 V.

[Brief description of drawings]

FIG. 1 is a vertical sectional view of a conventional MES-FET. FIG. 2 is a longitudinal sectional view (A) of the first DIS-FET used in the nonvolatile semiconductor memory device of the present invention, and energy band diagrams (B) and (C) showing the same. FIG. 3 is a vertical cross-sectional view of a DIS-FET having another structure used in the nonvolatile semiconductor memory device of the present invention. FIG. 4 shows a structure (A) of a nonvolatile semiconductor memory device of the present invention using a DIS-FET and a connection diagram (B) of its equivalent circuit. FIG. 5 is a diagram showing the difference in Fermi level between the substrate surface and the inside of the semiconductor with respect to the thickness of the gate insulating film.

Claims (2)

[Claims] 1. A pair of impurity regions on a semiconductor substrate, a channel forming region having the same conductivity type as the impurity region between the impurity regions, and a silicon nitride film having a thickness of 20 to 200 Å on the channel forming region. And a semiconductor floating gate doped with an impurity having a conductivity type opposite to that of the impurity region on the silicon nitride, and the floating gate is covered with an insulating film, and a control electrode is provided above the floating gate. Non-volatile semiconductor memory device. 2. The non-volatile semiconductor memory device according to claim 1, wherein the silicon nitride film is made of Si ₃ N ₄ or SiO _x N _y .