JPH063813B2 - Method of manufacturing thin film transistor - Google Patents
Method of manufacturing thin film transistorInfo
- Publication number
- JPH063813B2 JPH063813B2 JP59211104A JP21110484A JPH063813B2 JP H063813 B2 JPH063813 B2 JP H063813B2 JP 59211104 A JP59211104 A JP 59211104A JP 21110484 A JP21110484 A JP 21110484A JP H063813 B2 JPH063813 B2 JP H063813B2
- Authority
- JP
- Japan
- Prior art keywords
- photosensitive resin
- thin film
- resin film
- film pattern
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 51
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000010408 film Substances 0.000 claims description 108
- 239000011347 resin Substances 0.000 claims description 70
- 229920005989 resin Polymers 0.000 claims description 70
- 239000000758 substrate Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 7
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- YFNCATAIYKQPOO-UHFFFAOYSA-N thiophanate Chemical compound CCOC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OCC YFNCATAIYKQPOO-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 この発明は薄膜トランジスタの製造方法に関するもので
ある。TECHNICAL FIELD The present invention relates to a method for manufacturing a thin film transistor.
従来例の構成とその問題点 薄膜トランジスタの製造方法の従来例を第２図に示した
工程図に沿って説明する。第２図において、１は絶縁性
の透明基板、２は紫外線に不透明な第１の電極配線で一
般にクロム等が用いられる。３は絶縁膜（窒化シリコン
膜）、４は半導体薄膜（アモルファスシリコン膜）、５
は絶縁膜（窒化シリコン膜）、６は第１の感光性樹脂膜
パターン、７は前記感光性樹脂膜パターン６にできたピ
ンホール、８は薄膜層（４，５）にできたピンホール、
９は第２の感光性樹脂膜パターン、１０はピンホール８
と感光性樹脂膜パターン９の開口部との重なりでできる
ピンホール、１１は半導体薄膜４へ金属電極のコンタク
トをとるための開口、１２は絶縁膜３のピンホール、１
３は第２の電極配線、１４は第２の電極配線１３と第１
の電極配線２がショートしたところである。Configuration of Conventional Example and Problems Thereof A conventional example of a method of manufacturing a thin film transistor will be described with reference to the process chart shown in FIG. In FIG. 2, reference numeral 1 is an insulating transparent substrate, 2 is a first electrode wiring opaque to ultraviolet rays, and generally chromium or the like is used. 3 is an insulating film (silicon nitride film), 4 is a semiconductor thin film (amorphous silicon film), 5
Is an insulating film (silicon nitride film), 6 is a first photosensitive resin film pattern, 7 is a pinhole formed in the photosensitive resin film pattern 6, 8 is a pinhole formed in the thin film layers (4, 5),
9 is the second photosensitive resin film pattern, 10 is the pinhole 8
And the opening of the photosensitive resin film pattern 9 are overlapped with each other, 11 is an opening for making a metal electrode contact to the semiconductor thin film 4, 12 is a pinhole of the insulating film 3, 1
3 is the second electrode wiring, 14 is the second electrode wiring 13 and the first
The electrode wiring 2 is short-circuited.
まず、第２図（Ａ）に示すように、透明基板１上に電極
配線２を形成する。この電極配線２は通常はクロムの蒸
着およびホトエッチングにより形成される。First, as shown in FIG. 2A, the electrode wiring 2 is formed on the transparent substrate 1. The electrode wiring 2 is usually formed by vapor deposition of chromium and photoetching.
つぎに、第２図（Ｂ）に示すように、前記透明基板１上
に連続的にプラズマＣＶＤ法を用いて、窒化シリコン膜
３（ＳｉＮ膜と記す）、アモルファスシリコン膜４（α
−Ｓｉ膜と記す），ＳｉＮ膜５を順次形成する。Next, as shown in FIG. 2B, a silicon nitride film 3 (hereinafter referred to as SiN film) and an amorphous silicon film 4 (α) are continuously formed on the transparent substrate 1 by using a plasma CVD method.
-Si film) and the SiN film 5 are sequentially formed.
つぎに、薄膜トランジスタ領域を形成するために感光性
樹脂膜パターン６を形成するのであるが、第２図（Ｃ）
に示すように、ピンホール７が発生する。この状態で薄
膜をエッチングすると、第２図（Ｄ）に示すように、全
ての薄膜層（４，５）にピンホール８を生ずる。Next, a photosensitive resin film pattern 6 is formed in order to form a thin film transistor area. As shown in FIG.
As shown in, a pinhole 7 is generated. When the thin film is etched in this state, pinholes 8 are formed in all the thin film layers (4, 5) as shown in FIG. 2 (D).
ここで、感光性樹脂膜パターン６を除去し、α−Ｓｉ膜
４へのコンタクトをとるための開口１１を形成するため
の感光性樹脂膜パターン９を第２図（Ｅ）のように形成
するのであるが、第２図（Ｄ）に示すピンホール８と感
光性樹脂膜パターン９の開口とが重なってピンホール１
０を生ずる。この状態でＳｉＮ膜３をエッチングすれ
ば、第２図（Ｆ）の１２で示すように第１の電極配線２
の一部が露出する。Here, the photosensitive resin film pattern 6 is removed, and a photosensitive resin film pattern 9 for forming an opening 11 for making contact with the α-Si film 4 is formed as shown in FIG. 2 (E). However, the pinhole 1 and the opening of the photosensitive resin film pattern 9 shown in FIG.
Yields 0. If the SiN film 3 is etched in this state, as shown by 12 in FIG.
Part of is exposed.
したがって、第２の電極配線１３を形成したとき第２図
（Ｇ）に示すように符号１４で示す部分で第１の電極配
線２と第２の電極配線１３とがショートし、このトラン
ジスタは不良となる。Therefore, when the second electrode wiring 13 is formed, the first electrode wiring 2 and the second electrode wiring 13 are short-circuited at a portion indicated by reference numeral 14 as shown in FIG. 2 (G), and this transistor is defective. Becomes
薄膜トランジスタの不良は大部分が前述のようにホトエ
ッチングに起因しており、他には薄膜形成時のピンホー
ルもある。これらの不良を防止するため、感光性樹脂膜
を２回塗布する方法，薄膜層（４〜６）のエッチング時
膜毎にホト工程を入れる等の方法はあるが、工程が複雑
になり、効果はそれ程期待できない。Most of the defects of the thin film transistor are caused by the photoetching as described above, and there are other pinholes at the time of forming the thin film. In order to prevent these defects, there are methods such as coating the photosensitive resin film twice and adding a photo process to each film when etching the thin film layers (4 to 6), but the process becomes complicated and Can't expect that much.
発明の目的 この発明の目的は、マスクおよび高価なマスク合せ装置
を使用することなく薄膜トランジスタ上の主要領域にの
み選択的に感光性樹脂膜パターンを形成して著しくピン
ホール発生率を低減することができる薄膜トランジスタ
の製造方法を提供することである。OBJECT OF THE INVENTION It is an object of the present invention to selectively form a photosensitive resin film pattern only in a main region on a thin film transistor without using a mask and an expensive mask aligning device to significantly reduce the pinhole generation rate. It is to provide a method of manufacturing a thin film transistor which can be performed.
発明の構成 第１の発明は、絶縁性を有する透明基板上に第１の電極
配線が形成され、前記透明基板上にＳｉＮ膜，α−Ｓｉ
膜，ＳｉＮ膜を順次重ね、最上層のＳｉＮ膜に開口を形
成して第２の電極配線を形成することにより、薄膜トラ
ンジスタ、例えば薄膜電界効果型トランジスタを作るに
際し、素子領域を形成するための感光性樹脂膜パターン
形成後、全面にポジ型感光性樹脂膜を塗布し、透明基板
裏面より紫外線を照射し、第１の電極配線をマスクとし
て前記透明基板主面に感光性樹脂膜パターンを残すもの
である。According to a first aspect of the invention, a first electrode wiring is formed on a transparent substrate having an insulating property, and a SiN film and α-Si are formed on the transparent substrate.
A film and a SiN film are sequentially stacked, and an opening is formed in the uppermost SiN film to form a second electrode wiring, thereby forming a thin film transistor, for example, a thin film field effect transistor. After forming a photosensitive resin film pattern, a positive type photosensitive resin film is applied to the entire surface, ultraviolet rays are irradiated from the back surface of the transparent substrate, and the photosensitive resin film pattern is left on the main surface of the transparent substrate using the first electrode wiring as a mask. Is.
このようにすることにより、第１の電極配線上には感光
性樹脂膜パターンが二層に残ることになり、両方の膜を
貫通してピンホールが発生する率は各々のピンホール発
生率の積となり極めて低減されることになる。By doing so, two layers of the photosensitive resin film pattern remain on the first electrode wiring, and the rate of pinholes penetrating both films depends on the rate of occurrence of each pinhole. It will be a product and will be extremely reduced.
また、第２の発明は、例えば薄膜電界効果型トランジス
タを作るに際し、素子領域を形成するための感光性樹脂
膜パターン形成後、最上層のＳｉＮ膜を感光性樹脂膜パ
ターンをマスクにしてエッチングし、感光性樹脂膜パタ
ーンを除去した後全面にポジ型感光性樹脂膜を塗布し、
透明基板裏面より紫外線を照射し、第１の電極配線をマ
スクとして前記透明基板主面にポジ型の感光性樹脂膜パ
ターンを残すものである。A second invention is, for example, in forming a thin film field effect transistor, after forming a photosensitive resin film pattern for forming an element region, etching the uppermost SiN film using the photosensitive resin film pattern as a mask. After removing the photosensitive resin film pattern, apply a positive photosensitive resin film on the entire surface,
Ultraviolet rays are radiated from the back surface of the transparent substrate, and the positive type photosensitive resin film pattern is left on the main surface of the transparent substrate using the first electrode wiring as a mask.
このようにすることにより、第１の電極配線上には、素
子領域形成用の感光性樹脂膜パターンでエッチングされ
て最上層のＳｉＮ膜とポジ型の感光性樹脂膜パターンと
が重なることになり、最上層のＳｉＮ膜とポジ型の感光
性樹脂膜パターンをマスクとしてα−Ｓｉ膜をエッチン
グすることで、第１の発明と同様に両方の膜（この場
合、素子領域形成用の感光性樹脂膜パターンのピンホー
ルが転写された最上層のＳｉＮ膜とポジ型の感光性樹脂
膜パターン）を貫通してピンホールが発生する率が各々
のピンホール発生率の積となり極めて低減されることに
なる。By doing so, the uppermost SiN film and the positive photosensitive resin film pattern are overlapped with each other by etching with the photosensitive resin film pattern for forming the element region on the first electrode wiring. By etching the α-Si film using the uppermost SiN film and the positive photosensitive resin film pattern as a mask, both films (in this case, the photosensitive resin for forming the element region are formed). The rate of occurrence of pinholes penetrating the uppermost SiN film to which the pinholes of the film pattern are transferred and the positive type photosensitive resin film pattern) is a product of the respective pinhole occurrence rates and is extremely reduced. Become.
実施例の説明 以下図面を参照にさらに詳細にこの発明について説明す
る。第１図（Ａ）〜（Ｆ）の工程は第２図（Ｃ）の後に
続くものであり、第２図（Ａ）〜（Ｃ）の工程の説明は
省略する。第１図において、２１はポジ型感光性樹脂
膜、２２は紫外線、２３はポジ型感光性樹脂膜パター
ン、２４は感光性樹脂膜パターン、２５はコンタクト用
開口を形成するための開口、２６は最上層のＳｉＮ膜５
に形成されたコンタクト用開口、２７は第２の電極配線
である。Description of Embodiments The present invention will be described in more detail with reference to the drawings. The steps of FIGS. 1 (A) to (F) follow those of FIG. 2 (C), and the description of the steps of FIGS. 2 (A) to (C) is omitted. In FIG. 1, 21 is a positive photosensitive resin film, 22 is ultraviolet rays, 23 is a positive photosensitive resin film pattern, 24 is a photosensitive resin film pattern, 25 is an opening for forming a contact opening, and 26 is an opening. Top SiN film 5
The contact opening and 27 are second electrode wirings.
第２図（Ｃ）まで終了した透明基板１上にポジ型の第２
の感光性樹脂膜２１を全面塗布する。On the transparent substrate 1 finished up to FIG.
Then, the entire surface of the photosensitive resin film 21 is coated.
つぎに、紫外線２２を裏面より照射することにより、第
１の電極配線２でマスクされる領域はポジ型感光性樹脂
膜２１が分解されないので、現像すれば第１図（Ｂ）に
示すようにポジ型感光性樹脂膜パターン２３が残存す
る。この状態で第１の感光性樹脂膜パターン６のピンホ
ール７は完全に覆われる。Next, by irradiating the back surface with the ultraviolet rays 22, the positive type photosensitive resin film 21 is not decomposed in the region masked by the first electrode wiring 2, so that if the development is performed, as shown in FIG. 1 (B). The positive photosensitive resin film pattern 23 remains. In this state, the pinhole 7 of the first photosensitive resin film pattern 6 is completely covered.
つぎに、上記感光性樹脂膜パターン６およびポジ型感光
性樹脂膜パターン２３をマスクとして、ＳｉＮ膜５，α
−Ｓｉ膜４をエッチングし、感光性樹脂膜パターン６お
よびポジ型感光性樹脂膜パターン２３を除去して第１図
（Ｃ）の形状を得る。Next, using the photosensitive resin film pattern 6 and the positive type photosensitive resin film pattern 23 as a mask, the SiN film 5, α
The -Si film 4 is etched to remove the photosensitive resin film pattern 6 and the positive photosensitive resin film pattern 23 to obtain the shape shown in FIG. 1 (C).
つぎに、第３の感光性樹脂膜を塗布し、第１図（Ｄ）に
示すように感光性樹脂膜パターン２４を出し、開口２５
を形成する。つぎに、ＳｉＮ膜５をエッチングし、この
後感光性樹脂膜パターン２４を除去することにより第１
図（Ｅ）に示すようにコンタクト用開口２６が形成され
る。この状態で第１図（Ｆ）に示すように第２の電極配
線２７を形成して、トランジスタは完成する。Next, a third photosensitive resin film is applied, a photosensitive resin film pattern 24 is exposed as shown in FIG.
To form. Next, the SiN film 5 is etched, and then the photosensitive resin film pattern 24 is removed to remove the first
A contact opening 26 is formed as shown in FIG. In this state, the second electrode wiring 27 is formed as shown in FIG. 1 (F), and the transistor is completed.
この発明の工程では、第１図（Ｂ）に示すように第１の
感光性樹脂膜パターン６のピホール７を埋めたが、ポジ
型感光性樹脂膜を塗布して裏面より紫外線を照射する工
程は、薄膜層（３，４，５）のエッチング前のいずれか
に行なっても効果はある。すなわち、感光性樹脂膜パタ
ーン６で最上層の薄膜層（５）をエッチングしたのち、
感光性樹脂膜パターン６を除去し、ついでポジ型感光性
樹脂膜を透明基板１上の全面に塗布し、透明基板１の裏
面から紫外線を照射して第１の電極配線２に対応するポ
ジ型感光性樹脂膜を選択的に残し、ポジ型感光性樹脂膜
パターンおよび最上層の薄膜層（５）をマスクとして下
層の薄膜層（４）をエッチングし、この後ポジ型感光性
樹脂膜パターンを除去し、上記実施例と同様に第２の電
極配線を形成するようにしてもよい。In the process of the present invention, as shown in FIG. 1 (B), the pinholes 7 of the first photosensitive resin film pattern 6 are filled. Is effective even if it is performed before the thin film layers (3, 4, 5) are etched. That is, after etching the uppermost thin film layer (5) with the photosensitive resin film pattern 6,
The photosensitive resin film pattern 6 is removed, and then a positive photosensitive resin film is applied on the entire surface of the transparent substrate 1, and ultraviolet rays are radiated from the back surface of the transparent substrate 1 so as to correspond to the first electrode wiring 2. The positive photosensitive resin film pattern is selectively left, the lower thin film layer (4) is etched by using the positive photosensitive resin film pattern and the uppermost thin film layer (5) as a mask, and then the positive photosensitive resin film pattern is formed. Alternatively, the second electrode wiring may be formed similarly to the above embodiment.
発明の効果 第１の発明の薄膜トランジスタの製造方法によれば、感
光性樹脂膜パターンにポジ型感光性樹脂膜パターンが重
なるので、感光性樹脂膜パターンをマスクとした薄膜層
のエッチングを行う際に、第１の電極配線と重なる部位
上の薄膜層のピンホールは格段に減少し、 同様に、第２の発明の薄膜トランジスタの製造方法によ
れば、感光性樹脂膜パターンをマスクとしてエッチング
された最上層の薄膜層にポジ型感光性樹脂膜パターンが
重なるので、感光性樹脂膜パターンをマスクとして最上
層の薄膜層をエッチングし、さらに最上層の薄膜層をマ
スクとして下層の薄膜層のエッチングを行う際に、第１
の電極配線と重なる部位上の下層の薄膜層のピンホール
は格段に減少し、 したがって、第１および第２の発明の薄膜トランジスタ
の製造方法ともに、第２の電極配線が第１の電極配線と
ショートすることを回避するという格別の効果を発揮す
る。EFFECTS OF THE INVENTION According to the method of manufacturing a thin film transistor of the first invention, since the positive photosensitive resin film pattern overlaps the photosensitive resin film pattern, it is possible to perform etching of the thin film layer using the photosensitive resin film pattern as a mask. , The number of pinholes in the thin film layer on the portion overlapping with the first electrode wiring is significantly reduced, and similarly, according to the method of manufacturing a thin film transistor of the second invention, the pinholes etched by using the photosensitive resin film pattern as a mask Since the positive photosensitive resin film pattern overlaps the upper thin film layer, the photosensitive resin film pattern is used as a mask to etch the uppermost thin film layer, and the uppermost thin film layer is used as a mask to etch the lower thin film layer. When the first
The number of pinholes in the lower thin film layer on the portion overlapping with the electrode wiring is remarkably reduced. It has a special effect of avoiding doing.
しかも、ポジ型感光性樹脂膜パターンは第１の電極配線
をマスクとして、つまり新規マスクを追加することなく
センフアライメント方式で形成しているので、高価なア
ライメント装置およびアライメントのための手間を全く
必要とせずに、容易にポジ型感光性樹脂膜パターンを形
成することができる。したがって、新規設備および製造
コストを増やすことなく、ピンホール不良の発生確率を
格段に減少させることができる。Moreover, since the positive photosensitive resin film pattern is formed by the senf alignment method without using the first electrode wiring as a mask, that is, without adding a new mask, an expensive alignment device and alignment labor are completely eliminated. The positive photosensitive resin film pattern can be easily formed without the need. Therefore, the probability of occurrence of pinhole defects can be significantly reduced without increasing new equipment and manufacturing costs.
この発明の方法は特に多数個の薄膜トランジスタをスイ
ッチ素子としてマトリックス状に形成した液晶パネル用
薄膜トランジスタアレイ基板の製造に欠かすことのでき
ない技術である。The method of the present invention is a technique indispensable for manufacturing a thin film transistor array substrate for a liquid crystal panel in which a large number of thin film transistors are formed in a matrix as switch elements.
第１図はこの発明の一実施例の工程図、第２図は従来の
薄膜トランジスタの製造方法を説明するための工程図で
ある。 １…透明基板、２…第１の電極配線、３…絶縁膜（薄膜
層）、４…半導体薄膜（薄膜層）、５…絶縁膜（薄膜
層）、６…感光性樹脂膜パターン、２１…ポジ型感光性
樹脂膜、２２…紫外線、２３…ポジ型感光性樹脂膜パタ
ーン、２６…絶縁膜５に形成されたコンタクト用開口、
２７…第２の電極配線FIG. 1 is a process drawing of an embodiment of the present invention, and FIG. 2 is a process drawing for explaining a conventional method of manufacturing a thin film transistor. DESCRIPTION OF SYMBOLS 1 ... Transparent substrate, 2 ... 1st electrode wiring, 3 ... Insulating film (thin film layer), 4 ... Semiconductor thin film (thin film layer), 5 ... Insulating film (thin film layer), 6 ... Photosensitive resin film pattern, 21 ... Positive photosensitive resin film, 22 ... Ultraviolet, 23 ... Positive photosensitive resin film pattern, 26 ... Contact opening formed in the insulating film 5,
27 ... Second electrode wiring
フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/784 Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 29/784
Claims (2)
明な第１の電極配線を形成する工程と、前記透明基板上
全面に第１の絶縁膜，半導体薄膜および第２の絶縁膜か
らなる三層の薄膜層を形成する工程と、前記第１の電極
配線の上方に位置する前記薄膜層の少なくともトランジ
スタを形成すべき領域上にのみ選択的に感光性樹脂膜パ
ターンを形成する工程と、前記透明基板上全面にポジ型
感光性樹脂膜を塗布した後前記透明基板の裏面より紫外
線を照射して前記第１の電極配線に対応するポジ型感光
性樹脂膜パターンを選択的に残す工程と、前記薄膜層を
前記感光性樹脂膜パターンおよびポジ型感光性樹脂膜パ
ターンをマスクとしてエッチングした後前記感光性樹脂
膜パターンおよびポジ型感光性樹脂膜パターンを除去す
る工程と、前記第２の絶縁膜にコンタクト用開口を形成
する工程と、この後前記コンタクト用開口を通して前記
半導体薄膜に接触する第２の電極配線を形成する工程と
を含む薄膜トランジスタの製造方法。1. A step of forming a first electrode wiring opaque to ultraviolet rays on an insulating transparent substrate, and a first insulating film, a semiconductor thin film and a second insulating film on the entire surface of the transparent substrate. A step of forming three thin film layers, and a step of selectively forming a photosensitive resin film pattern only on at least a region of the thin film layer above the first electrode wiring where a transistor is to be formed, A step of applying a positive photosensitive resin film on the entire surface of the transparent substrate and then irradiating ultraviolet rays from the rear surface of the transparent substrate to selectively leave a positive photosensitive resin film pattern corresponding to the first electrode wiring. A step of etching the thin film layer using the photosensitive resin film pattern and the positive photosensitive resin film pattern as a mask and thereafter removing the photosensitive resin film pattern and the positive photosensitive resin film pattern; A step of forming an insulating film a contact opening, the method of manufacturing the thin film transistor and forming a second electrode wire in contact with the semiconductor thin film through the after the contact opening.
明な第１の電極配線を形成する工程と、前記透明基板上
全面に第１の絶縁膜，半導体薄膜および第２の絶縁膜か
らなる三層の薄膜層を形成する工程と、前記第１の電極
配線の上方に位置する前記薄膜層の少なくともトランジ
スタを形成すべき領域上にのみ選択的に感光性樹脂膜パ
ターンを形成する工程と、前記感光性樹脂膜パターンを
マスクとして最上層の薄膜層をエッチングする工程と、
前記感光性樹脂膜パターンを除去する工程と、この後前
記透明基板上全面にポジ型感光性樹脂膜を塗布した後前
記透明基板の裏面より紫外線を照射して前記第１の電極
配線に対応するポジ型感光性樹脂膜パターンを選択的に
残す工程と、前記ポジ型感光性樹脂膜パターンおよび前
記最上層の薄膜層をマスクとして下層の薄膜層をエッチ
ングする工程と、前記ポジ型感光性樹脂膜パターンを除
去する工程と、前記第２の絶縁膜にコンタクト用開口を
形成する工程と、この後前記コンタクト用開口を通して
前記半導体薄膜に接触する第２の電極配線を形成する工
程とを含む薄膜トランジスタの製造方法。2. A step of forming a first electrode wiring opaque to ultraviolet rays on an insulating transparent substrate, and a first insulating film, a semiconductor thin film and a second insulating film on the entire surface of the transparent substrate. A step of forming three thin film layers, and a step of selectively forming a photosensitive resin film pattern only on at least a region of the thin film layer above the first electrode wiring where a transistor is to be formed, Etching the uppermost thin film layer using the photosensitive resin film pattern as a mask,
A step of removing the photosensitive resin film pattern, and thereafter applying a positive photosensitive resin film on the entire surface of the transparent substrate and irradiating ultraviolet rays from the back surface of the transparent substrate to correspond to the first electrode wiring. A step of selectively leaving a positive photosensitive resin film pattern; a step of etching a lower thin film layer using the positive photosensitive resin film pattern and the uppermost thin film layer as a mask; and the positive photosensitive resin film A thin film transistor comprising: a step of removing a pattern; a step of forming a contact opening in the second insulating film; and a step of forming a second electrode wiring which comes into contact with the semiconductor thin film through the contact opening after that. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59211104A JPH063813B2 (en) | 1984-10-08 | 1984-10-08 | Method of manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59211104A JPH063813B2 (en) | 1984-10-08 | 1984-10-08 | Method of manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6189671A JPS6189671A (en) | 1986-05-07 |
| JPH063813B2 true JPH063813B2 (en) | 1994-01-12 |
Family
ID=16600471
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59211104A Expired - Lifetime JPH063813B2 (en) | 1984-10-08 | 1984-10-08 | Method of manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH063813B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL8800220A (en) * | 1988-01-29 | 1989-08-16 | Philips Nv | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE, IN WHICH A METAL CONDUCTOR TRACK IS APPLIED ON A SURFACE OF A SEMICONDUCTOR BODY. |
| JP2006100760A (en) * | 2004-09-02 | 2006-04-13 | Casio Comput Co Ltd | Thin-film transistor and its manufacturing method |
-
1984
- 1984-10-08 JP JP59211104A patent/JPH063813B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6189671A (en) | 1986-05-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100686228B1 (en) | apparatus and method for photolithography, and manufacturing method for a thin film transistor array panel of a liquid crystal display using the same | |
| US6670104B2 (en) | Pattern forming method and method of manufacturing thin film transistor | |
| US6650394B1 (en) | Identification mark portion in liquid crystal display panel and fabricating method thereof | |
| JP2002026333A (en) | Method of manufacturing active matrix board | |
| US3542551A (en) | Method of etching patterns into solid state devices | |
| JP2003195355A (en) | Contact portion of semiconductor device and method for manufacturing the same and thin film transistor array panel for displaying device including the contact portion and method for manufacturing the same | |
| CN100442539C (en) | A method of forming a metal pattern and a method of fabricating tft array panel by using the same | |
| KR100325072B1 (en) | Manufacturing method of high opening rate and high transmittance liquid crystal display device | |
| JPH063813B2 (en) | Method of manufacturing thin film transistor | |
| KR20010010117A (en) | Manufacturing method of a thin film transistor array panel for liquid crystal display | |
| KR100202236B1 (en) | Active matrix panel and its making method | |
| JPH08160457A (en) | Thin film transistor substrate and its production | |
| JP3071964B2 (en) | Manufacturing method of liquid crystal display device | |
| KR100601174B1 (en) | a manufacturing method of a photo-mask for thin film transistor panels | |
| JP3528388B2 (en) | Method for manufacturing transistor array | |
| JPH09113932A (en) | Wiring board and its production | |
| KR100670042B1 (en) | A manufacturing method of a thin film transistor array panel for a liquid crystal display | |
| KR100205867B1 (en) | Active matrix substrate and its fabrication method | |
| GB2574265A (en) | Transistor Arrays | |
| JPS61191035A (en) | Manufacture of semiconductor device | |
| KR100193650B1 (en) | Method of manufacturing thin film transistor of liquid crystal display device | |
| US20040157166A1 (en) | Lithographic process for multi-etching steps by using single reticle | |
| JPH07221316A (en) | Manufacture of thin film transistor | |
| KR100436009B1 (en) | Method of manufacturing tft substrate with self-aligned pixel electrode | |
| JPH02132831A (en) | Method of flattening substrate surface of wiring formation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |