JPH0637185A - Transistor reduction device - Google Patents

Abstract

PURPOSE:To completely perform transistor reduction even when an extremely large number of kinds of macro-cells are not prepared. CONSTITUTION:Before starting transistor reduction, a layout diagram 7 is prepared based on a network list 4 and a retrieving section 1 retrieves a macro-cell to be subjected to the reduction from the list 4. Then a reduction executing section 3 eliminates an unnecessary transistor in a circuit by directly changing the metallic wiring section in the diagram 7 by referring to the data on a data base 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention relates to a master slice LSI.
The present invention relates to a transistor reduction device that eliminates an unnecessary transistor circuit part in the function of an LSI.

[0002]

2. Description of the Related Art FIG. 10 is a functional block diagram of a conventional transistor reduction device. In the figure, reference numeral 4 denotes a storage means called a netlist for storing connection information between macro cells, which is a functional block composed of a plurality of transistors. Yes, and is actually realized by a memory or the like. Reference numeral 1 is a reduction target macro cell searching unit that searches the net list 4 for a reduction target macro cell, 2 is a branching unit that branches processing according to the presence or absence of reduction target macro cells in the searching unit 1, and 3 is a branching unit 2 A reduction execution unit that receives the output and performs reduction processing on the netlist 4 is a reduction database in which information used when the reduction execution unit 3 performs the reduction is stored, and 6 is an output of the branch unit 2. A layout unit that creates a layout diagram 7 based on the information of the netlist 4 at that time.

FIG. 12 shows an example of a circuit stored in the netlist 4 for reduction processing. In the figure, 8a, 8b and 8c are functional blocks composed of transistor circuits. Represents a macro cell. Further, FIG. 13 is a layout diagram obtained as a result of performing reduction processing on the netlist of FIG. 12 by the transistor reduction device.

Next, the method of reduction by the above-mentioned transistor reduction device will be explained based on the flow chart of FIG. Generally, in the netlist 4, a plurality of types of macrocells are prepared in advance in order to increase the efficiency of circuit design, and connection information for connecting these macrocells to obtain a desired logic circuit is stored. For example, in FIG.
A connection relation is stored in which one input of the three-input NAND circuit 8a is connected to a power source and used as a two-input NAND circuit. The reduction target macrocell searching unit 1 reads the connection information of the circuit from the netlist 4 as described above, and the macrocells whose input pins have a fixed potential among the macrocells 8a, 8b, and 8c or the output pins become empty pins. Search for macro cells that are In FIG. 12, the macro cells 8a and 8b are reduction target macro cells.
These macro cells realize desired logic functions by limiting some of the original circuit functions depending on the connection state, and when viewed as an LSI, they are disadvantageous in terms of power consumption and reliability. Is.

Since there is a reduction target macrocell in the branch unit 2, the subsequent processing is performed by the reduction execution unit 3
Move to. In the reduction execution unit 3, the macro cell 8
The information of the macro cell having the same function as the result of the reduction of a and 8b is obtained from the reduction database 5. For example, the macro cell 8a is judged to be equivalent to a 2-input NAND circuit, and the netlist 4 is changed based on this information. The resulting netlist is shown in FIG. That is, a macro cell required for replacement is searched from a plurality of types of macro cells stored in the netlist 4, and the 3-input NANDc (8a) whose input pin has a fixed potential is replaced with the 2-input NANDb (8d), Also, the DF whose data inversion output pin is an empty pin
Fa (8b) is a DFFb that does not have a data inversion output pin
Replace with (8e).

As a result of executing the reduction process as described above, a new reduction target macrocell may occur in the netlist 4, so that the reduction target macrocell searching unit 1 again applies the changed netlist 4 to the changed netlist 4. If a reduction target macrocell is not found in the branching unit 2 in the branching unit 2, layout is performed in the layout unit 6 using the changed netlist 4, the layout diagram 7 is obtained, and execution is terminated. On the other hand, when there is a new reduction target macro cell in the branching unit 2, the above processing is repeated until there is no reduction target macro cell. Even if there is a macro cell having a pin connected to a fixed potential or an empty pin, reduction cannot be performed if a replaceable macro cell having the same logical function is not prepared after reduction. It cannot be done, and the layout is performed in that state. Hereinafter, the reduction target macro cell refers to a macro cell capable of reduction.

[0007]

Since the conventional transistor reduction device is configured as described above, reduction cannot be performed unless a macro cell having the same function as the result after reduction is prepared. However, there is a problem in that it is disadvantageous in terms of power consumption and reliability of the LSI, and an extremely large number of types of macro cells must be prepared in order to perform complete reduction.

The present invention has been made to solve the above problems, and can eliminate unnecessary macro cells completely without preparing many kinds of macro cells, and is suitable for a master slice LSI. It is an object to obtain a transistor reduction device that can perform processing.

[0009]

SUMMARY OF THE INVENTION A transistor reduction device according to the present invention temporarily creates a layout diagram from a netlist, searches for a macrocell to be reduced in the netlist, and then executes the layout diagram based on the search result. The wiring connection inside is changed.

Further, in the layout diagram in which the wiring is deleted by the reduction process, the gate of the transistor which is in an unused state due to the deletion of the wiring is
A wiring for fixing the potential between the source and drain of the transistor to a non-conductive state is generated in the layout diagram.

[0011]

In the present invention, the output pin of the macro cell,
Alternatively, the reduction target macro cell is searched based on the information about the state of the input pin, and the reduction of the macro cell is performed by changing the wiring connection in the layout diagram based on the search result, that is, the reduction at the transistor level is performed. Therefore, complete reduction processing can be performed without preparing many types of macro cells.

Further, by stabilizing the gate potential of the unused transistor generated as a result of the reduction process by generating the wiring, it is possible to achieve a stable operation of the circuit after the reduction.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. Example 1. 1 is a functional block diagram of a transistor reduction device according to a first embodiment of the present invention.
In the present invention, the layout unit 6 once creates the layout diagram 7 from the netlist 4 and the reduction target macrocell searching unit 1 searches for the reduction target macrocell from the netlist 4 in the present invention. When there is a reduction target macro cell, the reduction execution unit 3 is configured to change the wiring connection in the layout diagram 7 created above.

In the above configuration, the netlist 4 is the first
Of the layout unit 6 and the layout diagram 7 constitute the second storage means M2, and the database 5 constitutes the third storage means M5. Further, the reduction target macro cell searching unit 1 uses the searching means M3.
And the branching unit 2 and the reduction executing unit 3 receive the output M3 of the search means and judge whether reduction is possible,
The reduction execution means M4 for changing the wiring connection information of the layout diagram stored in the second storage means M2 based on the output M5 of the third storage means.

FIG. 3 shows an example of a transistor circuit of a certain macro cell stored in the netlist 4. In the figure, 9a to 9f indicate transistors or transistor groups, and 10a, 10b, 10c indicate the connection between them. It is a connecting line.

FIG. 4 is a layout pattern diagram of a macro cell obtained from the net list shown in FIG. In the figure, 11 is a gate of a transistor, 12 is a metal wiring, 13 is a power supply potential supply wiring, and 14 is a ground potential supply wiring. Further, 15a, 15b, 15c, and 15d are shown in FIG.
In the transistor circuit diagram of the above, unnecessary wirings that are unnecessary when the output QC is an empty pin are shown as 16a and 16b.
Indicates an unnecessary transistor which becomes unnecessary when the output QC is an empty pin.

Further, FIG. 5 is a layout pattern diagram obtained as a result of reduction processing when the output QC is an empty pin. In the figure, 17a and 17b are additional wirings added in the reduction process.

Next, a reduction technique of the above-mentioned transistor reduction device will be described with reference to the flow chart of FIG. First, the layout unit 6 obtains a layout diagram 7 from the netlist 4. In the reduction target macrocell searching unit 1, the netlist 4 is paired as in the conventional example.
Search for a reduction target macro cell. Then, in the branching unit 2, if there is no reduction target macrocell, the process is terminated, and if there is, the process is transferred to the reduction executing unit 3.

The reduction execution unit 3 receives the output of the branching unit 2 and executes a predetermined reduction. Here, a case where the output pin QC of the macro cell of FIG. 3 is an empty pin will be described. From the transistor circuit diagram shown in FIG. 3, it can be seen that when the QC is an empty pin, a part of the transistor group 9a and the connection line 10b is unnecessary. This information is registered in advance in the reduction database 5, and the reduction execution unit 3 obtains this information from the reduction database 5.

In the layout diagram shown in FIG. 3, the reduction execution unit 3 has the QC pin corresponding to the wiring 15a and the transistor 9a corresponding to the transistors 16a and 16b.
In addition, the unnecessary portion of the connection line 10b is the wiring 15
Since they correspond to b, 15c, and 15d, unnecessary wirings 15a to 15d are deleted from the layout diagram.

As described above, the unnecessary transistor 16
The wirings to a and 16b are deleted, and the transistor group 9a is deleted from the circuit diagram. However, in the layout diagram 7 (see FIG. 4), the transistors 16a and 16b are removed.
Remains, and its gate potential is indefinite.
Although the operation is guaranteed in this state, the timing may become unstable. Therefore, the gate potentials of the transistors 16a and 16b are fixed to the power supply potential supply wiring 13 or the ground battery supply wiring 14 by using the additional wirings 17a and 17b. Then
Aim for stable operation. As described above, the layout diagram after reduction shown in FIG. 5 is obtained.

Thereafter, similar to the conventional example, the process is returned to the reduction target macro cell searching unit 1, and the above process is repeated until there is no reduction target macro cell detected by the reduction target macro cell searching unit 1.

Example 2. Next, a reduction method of the transistor reduction device according to the second embodiment of the present invention will be described with reference to FIGS. In this embodiment, the reduction process is performed when the input pin A of the reduction target macrocell is fixed to the ground potential. FIG. 6 is a transistor circuit diagram of a certain macrocell, and FIG.
FIG. 8 is a layout pattern diagram of the transistor circuit shown in FIG. 6, and FIG. 8 is a layout pattern diagram after reduction processing.

In the transistor circuit diagram shown in FIG.
When the input pin A is fixed to the ground potential, the transistor 9f is fixed in a conductive state in which a current can flow between its source and drain, so that the source and drain of the transistor 9f are short-circuited.
Is unnecessary. Further, the transistor 9k is fixed in a non-conducting state because the transistor 9i is always off. Therefore, it is equivalent to deleting the transistor 9i, and the transistor 9i is also unnecessary.

Since the transistors 16c and 16d are unnecessary in the layout diagram shown in FIG. 7 based on the above information, the wirings 15e, 15f and 15g are deleted accordingly.

The wiring for short-circuiting the connection line 10d connected to the drain of the transistor 9f and the power supply connected to the source of the transistor 9f, and the gate potentials of the unused transistors 16c and 16d are set. Wiring for fixing is generated. That is, FIG. 8 is a new layout diagram generated by the above-described processing, and the wiring 1
Reference numeral 7c is an additional wiring for short-circuiting the source and drain of the transistor 9f, and 17d and 17e are additional wiring for fixing the gate potential of the unused transistors 16c and 16d.

Example 3. Next, a reduction method of the transistor reduction device according to the second embodiment of the present invention will be described with reference to FIG. In this embodiment, the layout diagram shown in FIG. 8 is further reduced.
FIG. 6 is a new layout pattern diagram obtained by this reduction process. In the layout pattern diagram shown in FIG. 8, the transistor 16e (transistor 9e
In g), its drain and source are connected to the power supply 13, and they are always at the same potential, so their operation does not affect the logic and can be deleted. Also, the transistor 16f
The drain of the (transistor 9k) is open and is an unnecessary transistor.

Therefore, these unnecessary transistors 16e,
The wirings 15i and 15h are deleted to remove 16f, and the wirings 17f and 17g are added to fix the gate potentials of the unnecessary transistors 16e and 16f.
The layout diagram shown in is obtained.

As described above, according to the present embodiment, when a macrocell capable of reduction is searched for in the netlist 4 and the reduction target macrocell is detected, the layout diagram 7 previously created before reduction is Since unnecessary transistors in the circuit are deleted, the circuit can be changed at the transistor level compared to the conventional method of changing the circuit by replacing each macro cell, and many types of macro cells are not prepared in advance. Even
It is possible to completely reduce the reduction target macro cell.

Further, after the metal wiring of the macro cell in which the output pin is not connected or the input pin is fixed in potential is deleted, the gate potential of the unused transistor is generated and the potential is used as the source / drain. By fixing the gaps so that they are in a non-conducting state, it is possible to stabilize the circuit after the reduction process.

In the above embodiment, the first embodiment is to reduce the macro cell whose output pin is not connected, and the second embodiment is to reduce the macro cell whose input pin is fixed in potential. Although described as an example, these processes may be performed simultaneously.

When only the first embodiment is executed, unnecessary output pins and macro cells connected to them are only deleted, and the connection relationship of the macro cells from input to output does not change. Therefore, the simulation can be executed without changing the delay data of the macro cell.

[0033]

As described above, according to the transistor reduction device of the present invention, unnecessary transistors in a circuit are deleted by directly changing a layout diagram which is laid out in advance, so that an extremely large number of types of macrocells can be eliminated. It is possible to completely reduce the macro cell to be reduced, without the need for preparation, and to reduce power consumption and achieve high-speed operation.

Further, a stable operation of the circuit after reduction can be achieved by generating a wiring and setting the gate potential of the unused transistor generated by the reduction process to a fixed potential.

Further, since the present invention changes only the metal wiring portion of the layout diagram, the master slice LS
I is suitable and has an effect that it can be easily applied to the process flow.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a transistor reduction device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a reduction process of the transistor reduction device.

FIG. 3 is a diagram showing a part of a transistor circuit including a reduction-target macro cell whose output pin is an empty pin.

FIG. 4 is a layout diagram corresponding to the transistor circuit.

FIG. 5 is a new layout pattern diagram obtained by modifying the layout diagram according to the method of the first embodiment.

FIG. 6 is a diagram showing a part of a transistor circuit including a reduction-target macro cell in which an input pin has a fixed potential.

FIG. 7 is a layout diagram corresponding to the transistor circuit.

FIG. 8 is a new layout pattern diagram obtained by changing the layout diagram according to the method of the second embodiment.

FIG. 9 is a new layout pattern diagram obtained by modifying the layout diagram of FIG. 7 by the method of the third embodiment.

FIG. 10 is a block configuration diagram of a conventional transistor reduction device.

FIG. 11 is a flowchart showing reduction processing of the conventional transistor reduction device.

FIG. 12 is a diagram showing an example of a netlist in which reduction is performed using a conventional transistor reduction device.

FIG. 13 is a diagram showing a new netlist obtained by reduction of the netlist.

[Explanation of Codes] 1 Reduction target macrocell search unit 2 Branching unit 3 Reduction execution unit 4 Netlist 5 Reduction database 6 Layout unit 7 Layout diagram 8 Macrocell 9 Transistor (group) 10 Connection line 11 Transistor gate 12 Metal wiring 13 Power supply potential Supply wiring 14 Ground potential supply wiring 15 Unnecessary wiring 16 Unnecessary transistor 17 Additional wiring M1 First storage means M2 Second storage means M3 Search means M4 Reduction execution means M5 Third storage means

Claims (6)

[Claims] 1. A transistor reduction device for reducing unnecessary functional blocks composed of transistor elements at the design stage when manufacturing a master slice type LSI in which a transistor element is formed in a master step and wiring is performed in a slice step. In a first storage means for storing connection information between macro cells, which is a functional block composed of a plurality of transistors, as a netlist, and wiring connection information at a transistor level corresponding to the netlist as a layout diagram. A second storage means, a search means for searching the reduction target macro cell from the net list of the first storage means, and a macro cell having the same function as the reduction target macro cell. 3 storage means and the search means output described above are received. Reduction execution means for determining the presence or absence of the reduction target macro cell and changing the wiring connection information of the layout diagram stored in the second storage means based on the output of the third storage means. Characteristic transistor reduction device. 2. The transistor reduction device according to claim 1, wherein the search means searches a macro cell in the netlist for which the output pin is not connected, and the reduction execution means is the layout diagram. From the above, determine the transistor used only to configure the logic of the output pin of the macro cell in which the searched output pin is not connected, and arrange the wiring used only for connecting the transistor in the layout A transistor reduction device characterized by being deleted from the figure. 3. The transistor reduction device according to claim 1, wherein the search means searches a macro cell in the netlist for which the input pin has a fixed potential, and the reduction execution means uses the layout diagram. , Determining the transistor connected to the searched input pin, and if the transistor is in a conducting state by fixing the potential, short-circuit between the source and drain of the transistor with an additional wiring, and Delete the wiring that is used only for connecting to the gate, or if the transistor is non-conducting due to the above potential fixing, replace the wiring that is used only for connecting to the gate of the transistor. A transistor reduction device characterized by being removed. 4. The transistor reduction device according to claim 3, wherein the reduction execution means removes the wiring from the layout diagram by the reduction process, and as a result, the potential between the source and the drain is always the same potential. In the case where a transistor or a transistor in which at least one of a source and a drain is opened is formed, a wiring used only for connecting the transistor is deleted from the layout pattern diagram. Transistor reduction device to do. 5. The transistor reduction device according to claim 3, wherein the wiring in the layout diagram is processed so that the source-drain potential of the transistors in the corresponding macrocell is always the same. A transistor reduction device having a function of deleting a wiring used only for connection of the transistor from the layout pattern diagram when a transistor having at least one of the source and the drain opened is formed. . 6. The transistor reduction device according to claim 2, wherein the wiring is deleted in the reduction process,
A transistor reduction characterized in that an additional wiring for fixing the gate of an unused transistor to a potential at which the source-drain of the transistor becomes non-conductive is generated in the layout diagram. apparatus.