JPH0637160A - Method and apparatus for evaluating reliability of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To delete a cost and a time to be consumed for mounting by executing reliability tests of screening, destructive test in a wafer state. CONSTITUTION:A voltage from a power source 6 is applied to a tester head 5 in response to an output of a pattern generator 4 to a wafer 3 placed on a wafer stage of an LSI tester 2, the wafer 3 is heated by a heat source 7 added to the tester 2 to conduct a reliability test while expediting deterioration of the wafer 3, thereby detecting a defective chip.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit reliability evaluation method and evaluation apparatus.

[0002]

2. Description of the Related Art Conventionally, in order to evaluate the reliability of a semiconductor integrated circuit (hereinafter referred to as an LSI), non-defective products are selected in a wafer state, dicing chips are mounted, and then a certain period of time at high temperature ( Within a week) Screening for applying electrical stress to eliminate defective products before shipping, and destructive testing for assessing reliability by applying electrical stress at high temperature for one week or more (usually 1000 hours). It was done.

[0003]

Conventionally, since the reliability test was carried out after the LSI was mounted in the package, the L
Screening was carried out without testing the reliability of the SI chip itself, and it was unavoidable to mount even a low reliability one. Therefore, there is a problem in that the cost and time required for mounting and testing, which should be eliminated before the test, are completely wasted.

Therefore, an object of the present invention is to perform a reliability test such as a screening test or a destructive test in a wafer state, and to reduce the cost and time spent for mounting. Is to provide.

[0005]

According to the reliability evaluation method of a semiconductor integrated circuit of the present invention, at least one wafer deterioration promoting process of voltage application, heating and light irradiation is applied to a wafer before dicing the wafer. It is applied for screening or destructive testing. The semiconductor integrated circuit reliability evaluation apparatus of the present invention includes at least one of a power source for applying a voltage for promoting the deterioration of the wafer, a heat source for heating, and a light source for irradiating light.

[0006]

According to the structure of the present invention, before the wafer is diced, the wafer is subjected to at least one deterioration accelerating treatment of voltage application, heating and light irradiation, so that the wafer is electrically, thermally and
Since the screening or the destructive test is performed after applying the optical stress to the chip, it is possible to perform the test in the wafer state in which the deterioration is accelerated as compared with the actual use state. In this way, the defective chip can be detected in a state where the deterioration is accelerated, so that waste of mounting the defective product can be omitted.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit reliability evaluation apparatus 1 according to a first embodiment of the present invention. In the drawing, 2 is an LSI tester and 3 is a wafer stage. A wafer placed on the wafer 4 is a pattern generator for outputting a pattern voltage of a test program for causing the LSI to perform a predetermined operation, 5 is a tester head for applying the pattern voltage of the pattern generator 4 to the LSI by a probe, and 6 is a tester. A power source for supplying a voltage to the head and a heat source 7 for heating the wafer 3 placed on the wafer stage.

To test the wafer 3, first the heat source 7
Thus, the temperature of the surface of the wafer 3 is controlled to be uniform. The surface temperature is set within 100 to 200 degrees Celsius. Next, a test program that causes most of the transistors on the LSI to operate is repeatedly passed from the tester head 5 through the probe from the pattern generator 4 of the LSI tester 2. The voltage of the pattern of the test program at this time is set higher than the actual use condition.

In this way, the test is carried out in the state where the electric stress and the thermal stress are applied to the wafer 3,
If a deterioration phenomenon due to hot carriers or a disconnection of wiring occurs, the LSI chip can be detected as a defect, so that the test program is stopped. As described above, since the deterioration is accelerated by applying the electrical stress and the thermal stress, the defective chip can be detected in a short time. Since the defective chip detected can be eliminated and only the non-defective one needs to be mounted, wasteful cost and time for mounting can be reduced.

As a means for heating the wafer 3, a thermo streamer (hot air radiating device) may directly irradiate the chip with hot air. [Second Embodiment] FIG. 2 shows the configuration of the second embodiment. In the figure, the same reference numerals as those in FIG. 1 indicate the same elements. In this embodiment, a light source 8 is added to the LSI tester 2 instead of the heat source 7, and electrical stress by a test program is applied through the probe of the tester head 5, and at the same time, light of short wavelength (500 nm or less) is emitted from the tester head 5. Irradiate the wafer 3.

Since the wafer 3 is irradiated with high-energy light as optical stress, hot carriers are easily generated and deterioration is accelerated. The defective chip detection is the same as in the first embodiment. The means for irradiating the wafer 3 is not limited to light, but may be radiation, ions, or any other accelerating means. [Third Embodiment] FIG. 3 shows the configuration of the third embodiment. In this embodiment, the heat source 7 in the first and second embodiments is used.
A light source 8 and a light source 8 are added to the LSI tester 2, and electrical stress by a test program is applied through the probe of the tester head 5, and at the same time, light of short wavelength (500 nm or less) is emitted from the tester head 5 and further heated by the heat source 7. . In this way, by simultaneously applying the electrical stress, the thermal stress, and the optical stress, the acceleration of the deterioration of the wafer 3 is enhanced, and the evaluation time is further shortened.

As described above, in any of the embodiments, a reliability evaluation test can be performed in a wafer state in a short time to detect a defective chip, and only a good product needs to be mounted. Cost and time can be reduced.

[0013]

According to the reliability evaluation method and evaluation apparatus for semiconductor integrated circuits of the present invention, reliability tests such as screening and destructive tests can be performed in a wafer state in a short time, and defective chips can be eliminated. Since only good products can be mounted,
The cost and time required for implementation can be greatly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment.

FIG. 2 is a block diagram showing a configuration of a second exemplary embodiment.

FIG. 3 is a block diagram showing a configuration of a third exemplary embodiment.

[Explanation of symbols]

 1 Reliability Evaluation Device 2 LSI Tester 3 Wafer 4 Pattern Generator 5 Tester Head 6 Power Supply 7 Heat Source 8 Light Source

Claims (2)

[Claims] 1. The reliability of a semiconductor integrated circuit, characterized in that, before dicing a wafer, at least one deterioration promoting treatment of voltage application, heating, and light irradiation is performed on the wafer to perform a screening or destructive test. Sex evaluation method. 2. A reliability evaluation apparatus for a semiconductor integrated circuit, comprising at least one of a power source for applying a voltage for promoting deterioration of a wafer, a heat source for heating, and a light source for light irradiation.