JP2006080405A - Device and method for wafer level burn-in - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wafer level burn-in device and a wafer level burn-in method for preventing a probe from being exhausted and burned, by reducing an electric load applied to a wafer simultaneously and suppressing the transitional rise of the temperature of the wafer. <P>SOLUTION: The wafer level burn-in device and the wafer level burn-in method have an electric load application apparatus 105 for distributing each chip on the semiconductor wafer 101 into at least two groups, and giving an electric load to the chip of each group asynchronously, thus screening the semiconductor chip. With this configuration, the electric load applied to the semiconductor wafer 101 simultaneously is reduced and the transitional rise of the temperature of the semiconductor wafer is suppressed, thus preventing the probe from being exhausted and burned. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a wafer level burn-in apparatus and a wafer level burn-in method for screening defective products by applying an electrical load and a temperature load to a semiconductor wafer.

  Conventionally, a screening test apparatus called a burn-in apparatus performs an energization test in a thermal atmosphere at a predetermined temperature (for example, 125 ° C.) after packaging an IC chip obtained by individualizing a semiconductor wafer, Latent defects are revealed and defective products are screened.

  Such a conventional device requires a large thermostatic device and generates a large amount of heat, so it needs to be separated from other production lines and performed in a separate room, such as transporting semiconductor devices, mounting to and removing from the devices, etc. In addition, since a defective product is found after packaging, defective chips are also packaged, resulting in wasteful packaging. Furthermore, quality assurance in a so-called bare chip state in which an IC chip is not packaged has been required. Under such circumstances, it is desired to perform a burn-in test at the stage of a semiconductor wafer before being formed into chips.

  A burn-in apparatus for meeting such a demand is required to maintain the semiconductor wafer at a uniform temperature when a thermal load is applied to the semiconductor wafer. As a temperature control plate for a semiconductor wafer used for this purpose, a series of refrigerant flow paths and a heater are incorporated in a plate-like body made of a heat conductive material such as copper, aluminum, or an alloy thereof, and the refrigerant flow A coolant for cooling the semiconductor wafer to a temperature lower than the target temperature is allowed to flow through the path, and the temperature of the plate body is adjusted by causing the heater to generate heat so that the semiconductor wafer brought into contact with the plate body has a predetermined target. There has been proposed a wafer level burn-in apparatus having a temperature control function that maintains the temperature (see, for example, Patent Document 1).

Also, in order to improve cooling response, the wafer level burn-in is configured such that the cooling channel portion is separated from the heater portion which is a heating body as a cooling body and is in contact with the portion where the semiconductor wafer is held only for the time required for cooling. An apparatus has also been proposed (see, for example, Patent Document 2).
JP-A-8-34003 JP 2002-43381A

  However, in the conventional wafer level burn-in apparatus and wafer level burn-in method, as the IC chip size is reduced and the applied current is increased, a transient temperature when an electrical load is applied while the semiconductor wafer is maintained at a constant temperature. As a result of the increase, there is a problem that the probe for applying an electrical load to the semiconductor wafer becomes exhausted or burnt.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a wafer level burn-in apparatus and a wafer level burn-in method for preventing the probe from being consumed and burned.

  In order to achieve the above object, a wafer level burn-in apparatus according to claim 1 of the present invention uses a probe that collectively contacts all chips on a semiconductor wafer, and applies an electrical load and a temperature load. A wafer level burn-in apparatus for screening non-defective products, wherein an electrical load applying apparatus applies an electrical load at an arbitrary timing to each of at least two or more groups in which chips on the semiconductor wafer are divided in advance, and The semiconductor wafer has a thermal load application device that applies a thermal load to the semiconductor wafer and an inspection device that performs screening for defective products, and controls the timing of applying an electrical load to the chip on the semiconductor wafer. It is characterized by suppressing a rapid temperature rise of the wafer.

  The wafer level burn-in apparatus according to claim 2 is characterized in that, in the wafer level burn-in apparatus according to claim 1, the chips of each group are divided so as to be even on the semiconductor wafer.

  The wafer level burn-in apparatus according to claim 3 is the wafer level burn-in apparatus according to claim 1 or 2, wherein each chip is divided so as to contact chips of different groups on each side. And

  A wafer level burn-in apparatus according to claim 4 is the wafer level burn-in apparatus according to claim 1 or 2, wherein each area constituted by a plurality of chips is set as the group.

  The wafer level burn-in apparatus according to claim 5 is the wafer level burn-in apparatus according to claim 1, claim 2, claim 3, or claim 4, wherein the electrical load application device is independent for each group. The electrical load is applied in order.

  The wafer level burn-in apparatus according to claim 6 is the wafer level burn-in apparatus according to claim 1, claim 2, claim 3, or claim 4, wherein the electrical load application device sets timing to each group. It is characterized by applying an electrical load by shifting.

  The wafer level burn-in method according to claim 7 is a wafer level burn-in method in which defective probes are screened by applying an electrical load and a thermal load using a probe that contacts all chips on a semiconductor wafer at once. A step of dividing chips on a semiconductor wafer to be inspected into two or more groups, a step of applying an electrical load to each of the groups at an arbitrary timing, a step of applying a thermal load, and a screening inspection And a rapid temperature rise of the semiconductor wafer is suppressed by controlling the timing of applying an electrical load to the chip on the semiconductor wafer.

  A wafer level burn-in method according to an eighth aspect of the present invention is the wafer level burn-in method according to the seventh aspect, wherein the chips of each group are divided so as to be even on the semiconductor wafer.

  The wafer level burn-in method according to claim 9 is the wafer level burn-in method according to claim 7 or 8, wherein each chip is divided so as to be in contact with a different group of chips on each side. And

  A wafer level burn-in method according to claim 10 is characterized in that, in the wafer level burn-in method according to claim 7 or 8, each area constituted by a plurality of chips is set as the group.

  The wafer level burn-in method according to claim 11 is the wafer level burn-in method according to claim 7, claim 8, claim 9, or claim 10, wherein the electrical load application device is independent for each group. The electrical load is applied in order.

  The wafer level burn-in method according to claim 12 is the wafer level burn-in method according to claim 7, claim 8, claim 9, or claim 10, wherein the electrical load application device sets timing to each group. It is characterized by applying an electrical load by shifting.

  With this configuration, the electrical load applied to the semiconductor wafer at the same time is reduced, and a transient rise in the semiconductor wafer temperature is suppressed, so that the probe can be prevented from being consumed or burnt.

  The wafer level burn-in apparatus and the wafer level burn-in method of the present invention can increase the temperature of the entire semiconductor wafer by grouping chips on the semiconductor wafer and applying an electrical load in groups for each wafer level burn-in. Since the temperature is moderated, the temperature adjustment of the semiconductor wafer works effectively, and the transient temperature rise can be suppressed, so that the probe can be prevented from being consumed or burnt.

  The wafer level burn-in apparatus and the wafer level burn-in method according to the present invention divide each chip on a semiconductor wafer into at least two groups and apply an electrical load to each group of chips individually at an arbitrary timing. A defective semiconductor chip is screened using a load application device and a thermal load application device that applies a thermal load to the semiconductor wafer. At this time, since an electrical load is not applied to all the chips on the semiconductor wafer at the same time, the rapid temperature rise of the semiconductor wafer can be suppressed, and the temperature adjustment of the semiconductor wafer works effectively. Can be suppressed, and probe wear and burn can be prevented.

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings.
(Embodiment 1)
First, an outline of a wafer level burn-in apparatus and a temperature adjustment mechanism will be described with reference to FIG.

FIG. 1 is a schematic diagram of a wafer level burn-in apparatus according to Embodiment 1 of the present invention.
In FIG. 1, a semiconductor wafer 101 is held on a wafer holding tray 102, and is connected to a substrate 104 to which an electrical load is applied by a probe 103 capable of collectively contacting the semiconductor wafer. Applied. Here, the electrical load application device 105 can apply the electrical load asynchronously for each group to the chip on the semiconductor wafer. The temperature load is applied by controlling the temperature of the temperature adjustment plate 106 to 125 ° C. with a heater 108 disposed in the temperature adjustment plate 106, a coolant such as water or alcohol flowing through the coolant flow path 107. The The temperature control of the temperature adjustment plate 106 is based on the temperature measured by the temperature sensor 109 to control the amount of heat generated by the heater 108 from the temperature regulator 110 and the temperature and flow rate of the refrigerant flowing through the refrigerant flow path 107. Is done by.

Next, the wafer level burn-in method will be described with reference to FIGS.
FIG. 2 is a diagram illustrating group division of chips on a semiconductor wafer, FIG. 3 is a schematic diagram for explaining an electrical load application device in the first embodiment, and FIG. 4 shows application timings of electrical signals in the first embodiment. FIG. 5 and FIG. 5 are diagrams showing a change in wafer temperature during wafer level burn-in in the first embodiment.

  First, as shown in FIG. 2, in this example, the chips on the semiconductor wafer 101 are divided into a shaded portion group 201a in FIG. 2 (a) and a shaded portion group 201b in FIG. 2 (b). The electrical load applied to the two groups of chips is asynchronously applied. The division method is arbitrary, but it may be divided so that the chips of each group are equal on the semiconductor wafer. As shown in FIG. 2, the chips of the same group are divided so that they do not touch each other. May be. Furthermore, it can also be divided into a plurality of areas composed of a plurality of chips.

  Next, as shown in FIG. 3, in the electrical load application device, the groups 201a and 201b of the divided chips are connected to the wirings 301a and 301b, respectively. An electrical signal, which is an electrical load generated by the electrical signal generator 302 of the electrical load application device 105, is applied to each of the divided chip groups 201a and 201b by switching at the switch 303 at different timing. .

  As shown in the shaded portion in FIG. 4, the application timing of the electrical signal applied at this time is such that electrical signals are alternately applied to the group 201a and the group 201b in FIG. 2 from the electrical signal application start time Ts. The In the first embodiment, an example of dividing into two groups has been described. Therefore, the application timing is controlled so as not to alternately overlap two groups, but in the case of dividing into three or more groups, Then, an electrical load is applied by switching control of electrical signals so as not to overlap each group in turn. Here, by increasing the number of groups to be divided and reducing the electrical load applied at one time, a rapid increase in the semiconductor wafer temperature can be further mitigated.

  By applying the electrical signal at such timing, as shown in FIG. 5, the temperature change of the semiconductor wafer becomes more stable than in the prior art. A solid line indicates a temperature change when the chips are group-divided according to the present invention, and a broken line indicates a temperature change when the conventional group-division is not performed. When the group division is not performed, all the electrical loads are simultaneously applied to the semiconductor wafer, so that the temperature of the semiconductor wafer rapidly increases and the semiconductor wafer temperature exceeds 130 ° C., but when the group division is performed, Since the chips to which the electrical load is applied are dispersed, the temperature rise of the entire semiconductor wafer is moderated, the temperature adjustment of the semiconductor wafer works effectively, and the transient temperature rise can be suppressed.

  According to such a configuration, it is possible to prevent the probe from being consumed and burned by suppressing a transient increase in the temperature of the semiconductor wafer by reducing the electrical load simultaneously applied to the semiconductor wafer. Furthermore, since the chips to which the electrical load is applied are dispersed even when the electrical load to be applied is increased, the rapid increase in the semiconductor wafer temperature can be suppressed.

In the first embodiment, the group to which the electrical load is applied is switched by the switch 303 and the wirings 301a and 301b of each group. However, this may be configured by software such as a program. The temperature adjustment plate 106 is cooled by using the refrigerant flowing through the refrigerant flow path 107. However, the heat adjustment fin 106 is disposed on the temperature adjustment plate 106, and the air is cooled by circulating a gas such as air with a fan. It is good also as a structure which performs. Furthermore, in the above description, the example in which the chip on the semiconductor wafer is divided into two groups has been described, but it is also possible to divide the chip into two groups or more to distribute the respective electric load application timing.
(Embodiment 2)
In the second embodiment of the present invention, the same apparatus configuration as that of the first embodiment shown in FIG. 1 and the group division shown in FIG. 2 are used.

Next, the wafer level burn-in method will be described with reference to FIGS.
FIG. 6 is a schematic diagram for explaining an electrical load application device according to the second embodiment, and FIG. 7 is a diagram showing the application timing of the electrical signal in the second embodiment. The application timing of the electrical signal according to the configuration of FIG. Is illustrated. FIG. 8 is a diagram showing a change in the semiconductor wafer temperature during wafer level burn-in in the second embodiment.

  First, as shown in FIG. 6, in the electrical load application device, the groups 201a and 201b of the divided chips are connected to wirings 601a and 601b, respectively. The electrical signals generated by the electrical signal generator 602 of the electrical load application device 105 are divided by the switches 603a and 603b, respectively, and applied to the chips 201a and 201b at an arbitrary timing.

  As shown in the hatched portion in FIG. 7, the application timing of the electrical signal applied at this time starts application of the electrical signal to the group 201a at time Ts1, and applies to the group 201b at Ts2 shifted in time from Ts1. Start applying the electrical signal. When divided into three or more groups, the rapid increase in temperature of the semiconductor wafer can be further mitigated by reducing the number of groups to which an electrical load is applied simultaneously.

  By applying the electrical signal at such timing, as shown in FIG. 8, the semiconductor wafer temperature change becomes more stable than the conventional one. A solid line indicates a temperature change when the chips are group-divided according to the present invention, and a broken line indicates a temperature change when the conventional group-division is not performed. When the group division is not performed, all the electrical loads are simultaneously applied to the semiconductor wafer, so that the temperature of the semiconductor wafer rapidly increases and the semiconductor wafer temperature exceeds 130 ° C., but when the group division is performed, Since the chips to which the electrical load is applied are dispersed, the temperature rise of the entire semiconductor wafer is moderated, the temperature adjustment of the semiconductor wafer works effectively, and the transient temperature rise can be suppressed.

  According to such a configuration, it is possible to prevent the probe from being consumed and burned by suppressing a transient increase in the temperature of the semiconductor wafer by reducing the electrical load simultaneously applied to the semiconductor wafer. Furthermore, since the chips to which the electrical load is applied are dispersed even when the electrical load to be applied is increased, the rapid increase in the semiconductor wafer temperature can be suppressed.

In the second embodiment, the group to which the electrical load is applied is switched by the switches 603a and 603b and the wirings 601a and 601b of each group, but this may be configured by software such as a program. . The temperature adjustment plate 106 is cooled by using the refrigerant flowing through the refrigerant flow path 107. However, the heat adjustment fin 106 is disposed on the temperature adjustment plate 106, and the air is cooled by circulating a gas such as air with a fan. It is good also as a structure which performs. Furthermore, in the above description, the example in which the chip on the semiconductor wafer is divided into two groups has been described, but it is also possible to divide the chip into two groups or more to distribute the respective electric load application timing.
(Embodiment 3)
In the third embodiment of the present invention, the same apparatus configuration as that of the first embodiment shown in FIG. 1 is used.

Next, the wafer level burn-in method will be described with reference to FIGS. 9, 10, 11, and 12. FIG.
FIG. 9 is a diagram illustrating an area division of a chip on a semiconductor wafer in the third embodiment, FIG. 10 is a schematic diagram for explaining an electrical load applying device in the third embodiment, and FIG. 11 is an electrical diagram in the third embodiment. FIG. 12 is a diagram showing a signal application timing, and FIG. 12 is a diagram showing a change in wafer temperature during wafer level burn-in in the third embodiment.

  First, as shown in FIG. 9, in this example, chips on the semiconductor wafer 101 are divided into a group 901a according to the shaded area in FIG. 9A, a group 901b according to the shaded area in FIG. It is divided into groups 901c by the shaded area of c). The electric load applied to these three groups of chips is asynchronously applied. The method of division is arbitrary, but heat is more likely to dissipate at the outer periphery of the wafer than at the center of the wafer, so dividing it into concentric circles as shown in FIG. Can respond. Furthermore, it can be divided into further subdivided groups corresponding to the difference in heat transfer.

  Next, in the electrical load application apparatus as shown in FIG. 10, the groups 901a, 901b, and 901c of the divided chips are connected to the wirings 1001a, 1001b, and 1001c, respectively. The electrical signals generated by the electrical signal generator 1002 of the electrical load application device 105 are divided by the switches 1003a, 1003b, and 1003c, respectively, and applied to the chip groups 901a, 901b, and 901c at an arbitrary timing.

  As shown in the shaded area in FIG. 11, the application timing of the electrical signal applied at this time starts the electrical signal for the group 901a at time Ts1, and the electrical signal for the group 901b at Ts2 shifted in time from Ts1. The application of the electrical signal is started, and the application of the electrical signal to the group 901c is started at Ts3 where the time is further shifted. Even when divided into four or more groups, the rapid increase in temperature of the semiconductor wafer can be further alleviated by reducing the number of groups to which an electrical load is applied simultaneously.

  By applying the electrical signal at such timing, as shown in FIG. 12, the semiconductor wafer temperature change becomes more stable than in the prior art. A solid line indicates a temperature change when the chips are group-divided according to the present invention, and a broken line indicates a temperature change when the conventional group-division is not performed. When the group division is not performed, all the electrical loads are simultaneously applied to the semiconductor wafer, so that the temperature of the semiconductor wafer rapidly increases and the semiconductor wafer temperature exceeds 130 ° C., but when the group division is performed, Since the chips to which the electrical load is applied are dispersed, the temperature rise of the entire semiconductor wafer is moderated, the temperature adjustment of the semiconductor wafer works effectively, and the transient temperature rise can be suppressed.

  According to such a configuration, it is possible to prevent the probe from being consumed and burned by suppressing a transient increase in the temperature of the semiconductor wafer by reducing the electrical load simultaneously applied to the semiconductor wafer. Furthermore, since the chips to which the electrical load is applied are dispersed even when the electrical load to be applied is increased, the rapid increase in the semiconductor wafer temperature can be suppressed.

  In the third embodiment, the group to which the electrical load is applied is switched by the switches 1003a, 1003b, and 1003c and the wirings 1001a, 1001b, and 1001c of each group, but this is performed by software such as a program. It is good also as a structure. In addition, although the refrigerant flowing through the refrigerant flow path 107 is used for cooling the temperature adjustment plate 106, a heat radiating fin is disposed on the temperature adjustment plate 106, and a gas such as air is circulated by a fan. It is good also as a structure which cools. Further, in the above description, the example in which the chip on the semiconductor wafer is divided into three groups has been described, but it is also possible to divide the chips into three groups or more to distribute the respective electric load application timings.

  The wafer level burn-in apparatus and wafer level burn-in method of the present invention can prevent the probe from being consumed and burned, and perform wafer level burn-in for screening defective products by applying an electrical load and a thermal load to the semiconductor wafer. It is useful for an apparatus and a wafer level burn-in method.

Schematic of wafer level burn-in apparatus in Embodiment 1 of the present invention Diagram illustrating group division of chips on semiconductor wafer Schematic explaining the electrical load application device in the first embodiment The figure which shows the application timing of the electrical signal in Embodiment 1 The figure which shows the wafer temperature change at the time of wafer level burn-in in this Embodiment 1. Schematic explaining the electrical load application apparatus in Embodiment 2 The figure which shows the application timing of the electrical signal in Embodiment 2 The figure which shows the wafer temperature change at the time of wafer level burn-in in this Embodiment 2. The figure which illustrated the area division of the chip on the semiconductor wafer in Embodiment 3 Schematic explaining the electrical load application apparatus in Embodiment 3 The figure which shows the application timing of the electrical signal in Embodiment 3 The figure which shows the wafer temperature change at the time of wafer level burn-in in this Embodiment 3.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Semiconductor wafer 102 Wafer holding tray 103 Probe 104 Substrate 105 Electrical load application device 106 Temperature adjustment plate 107 Refrigerant flow path 108 Heater 109 Temperature sensor 110 Temperature regulator 201a Group 201b Group 301a Wiring 301b Wiring 302 Electric signal generation Section 303 Switch 601a Wiring 601b Wiring 602 Electrical signal generator 603a Switch 603b Switch 901a Group 901b Group 901c Group 1001a Wiring 1001b Wiring 1001c Wiring 1002 Electrical signal generating section 1003a Switch 1003b Switch 1003c Switch

Claims (12)

A wafer level burn-in apparatus that performs screening of defective products by applying an electrical load and a thermal load using a probe that contacts all chips on a semiconductor wafer at the same time.
An electrical load applying device that applies an electrical load at an arbitrary timing to each of at least two or more groups in which chips on the semiconductor wafer are divided in advance;
A thermal load applying device for applying a thermal load to the semiconductor wafer;
An inspection apparatus for screening defective products, and controlling a timing of applying an electrical load to a chip on the semiconductor wafer to suppress a rapid temperature rise of the semiconductor wafer. Level burn-in device.   2. The wafer level burn-in apparatus according to claim 1, wherein the chips of each group are divided so as to be even on the semiconductor wafer.   3. The wafer level burn-in apparatus according to claim 1, wherein each chip is divided so as to be in contact with a chip in a different group on each side.   3. The wafer level burn-in apparatus according to claim 1, wherein each area composed of a plurality of chips is set as the group.   5. The wafer level burn-in according to claim 1, wherein the electrical load application device applies an electrical load to each group in order independently. 6. apparatus.   5. The wafer level burn-in device according to claim 1, wherein the electrical load application device applies an electrical load to each group at different timings. . A wafer level burn-in method for screening defective products by applying an electrical load and a temperature load using a probe that contacts all chips on a semiconductor wafer at once.
Dividing the chips on the semiconductor wafer to be inspected into two or more groups;
Applying an electrical load to each of the groups at an arbitrary timing;
Providing a temperature load; and
A wafer level burn-in method comprising: controlling a timing of applying an electrical load to a chip on the semiconductor wafer by controlling a timing at which an electrical load is applied to the chip on the semiconductor wafer. .   8. The wafer level burn-in method according to claim 7, wherein the chips of each group are divided so as to be even on the semiconductor wafer.   9. The wafer level burn-in method according to claim 7, wherein each chip is divided so as to be in contact with a different group of chips on each side.   9. The wafer level burn-in method according to claim 7, wherein each area constituted by a plurality of chips is set as the group.   11. The wafer level burn-in according to claim 7, wherein the electrical load application device applies an electrical load to each group in order independently. 11. Method.   11. The wafer level burn-in method according to claim 7, wherein the electrical load application device applies an electrical load to each group at different timings. .

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