JPH0636424B2 - Protection circuit - Google Patents

Description

The present invention relates to a protection circuit in a MOS integrated circuit, the purpose of which is to improve performance.

1 will be described in detail with reference to the drawings. FIG. 1 is a plan view showing a structure of a conventional protection circuit, FIG. 2 is a sectional view showing a structure of a conventional protection circuit, and FIG. 3 is a structure showing the structure of FIG. It is sectional drawing shown typically.

In FIGS. 1 and 2, the first contact portion 2 of the external terminal 1 is connected to the P-type diffusion resistance layer 3 provided in the N-type substrate 11. The second contact portion 4 at the other end of the P-type diffusion resistance layer 3 is connected to the wiring material 5, and the third contact portion 6 of the wiring material 5 is an N-type diffusion layer provided in the P-type diffusion layer 7. 8
And a circuit portion (not shown) outside the protection circuit.

An N-type diffusion layer 9 for maintaining a potential is provided around the P-type diffusion resistance layer 3 and the P-type diffusion layer 7, and the N-type diffusion layer 9 is connected to the high potential side Vdd of the power supply.

A P-type diffusion layer 10 for maintaining a potential is provided around the N-type diffusion layer 8 so as to be connected to the P-type diffusion layer 7.
The P-type diffusion layer 10 is connected to the low potential side Vss of the power supply. Reference numeral 16 is an oxide insulating film made of SiO ₂ .

In the above protection circuit, the high potential Vdd is applied to the external terminal 1.
When a higher voltage is applied, carriers are injected from the P-type diffusion resistance layer 3 into the N-type substrate 11 as shown by the arrow in FIG. This carrier must be absorbed by the N-type diffusion layer 9. However, if the number of injected carriers is large, a part of the carrier will be absorbed by the N-type diffusion layer 9.
It flows out to the outside of the mold diffusion layer 9. Some of the carriers flowing out of the N-type diffusion layer 9 are captured by the P-type diffusion layer 7, but the other carriers flow out of the protection circuit to form another circuit such as a non-volatile memory. Reach the part that is. If there is a P-type diffusion layer whose potential is not firmly fixed, the potential of the P-type diffusion layer rises due to the carriers flowing into the P-type diffusion layer, and the N-type diffusion layer connected to a low potential is further present in the P-type diffusion layer. If there is a diffusion layer, a current will flow in the PN junction between the P-type diffusion layer and the N-type diffusion layer, which will cause a latch-up phenomenon.

Therefore, the present invention provides a protection circuit for preventing the above-mentioned drawbacks. FIG. 4 is a cross-sectional view showing a schematic structure for understanding the present invention, showing a structure for preventing carrier divergence by providing a P-type diffusion layer 12 outside the N-type diffusion layer 9. Is. That is, the P-type diffusion layer 12 provided outside the high-concentration N-type diffusion layer 9 is connected to any power source as described later and is not captured by the N-type diffusion layer 9. It effectively captures the carriers that diverge further outside 9 and prevents the carriers from straying. In this case, it is clear that the P-type diffusion layer 3, the N-type substrate 11, and the P-type diffusion layer 12 form a lateral PNP transistor. That is, the P-type diffusion layer 3 acts as an emitter, the N-type substrate 11 acts as a base, and the P-type diffusion layer 12 acts as a collector, so that the carrier trapping ability of the diffusion layer 12 becomes extremely strong.

In order to allow the P-type diffusion layer 3, the N-type substrate 11, and the P-type diffusion layer 12 to efficiently act as a lateral PNP transistor, the P-type diffusion layer 3 and the P-type diffusion layer are formed in the N-type substrate 11. It is necessary to form a passage portion between the layer 12 and the high-concentration N-type diffusion layer 9, and this passage portion is formed below the N-type diffusion layer 9 in FIG. Has been done.

FIG. 4 shows the case where the process of forming the P-type diffusion layer 12 is the same as that of the P-type diffusion layer 7. In this case, the P-type diffusion layer 12 can be a part of the P-type diffusion layer 7, and an example thereof is shown in FIG. Further, the P-type diffusion layer 12 is formed by a process different from that of the P-type diffusion layer 7.
The type diffusion layer 12a may be used, and this embodiment is shown in FIG. When the P-type diffusion layer 12 is not a part of the P-type diffusion layer 7, the potential of the P-type diffusion layer 12 can be different from that of the P-type diffusion layer 7. Sixth
It is also shown in the figure.

FIG. 5 is a plan view showing the structure of a protection circuit according to an embodiment of the present invention, in which a part of the N-type diffusion layer 9 connected to the high potential side Vdd in FIG. 1 is cut off, Using the opening, an extended portion 7a is formed by extending the P-type diffusion layer 7,
Further, the extending portion 7a is configured to guard the outside of the N-type diffusion layer 9 surrounding the P-type diffusion resistance layer 3 as shown in FIG.

FIG. 6 is a plan view showing a structure of a protection circuit according to another embodiment of the present invention, in which the P-type diffusion layer 12 is formed by a process different from that of the P-type diffusion layer 7. age,
And is provided separately from the P-type diffusion layer 7,
The outside of the N type diffusion layer 9 surrounding the outside of the P type diffusion layer 3 is P
The structure is surrounded by the type diffusion layer 12a. In this case the P
The type diffusion layer 12a is connected to either the low potential Vss or the high potential Vdd.

By the way, there is a problem in FIG. 6 whether the potential of the P-type diffusion layer 12a (or 12, the same applies hereinafter) should be Vdd or Vss. In general, it should be concluded that the lower the potential, the higher the trapping ability of the stray carrier is (albeit slightly), so Vss should be set. However, when the strong protection circuit according to the present invention is required, the noise voltage applied from the outside may have extremely large energy. For example, an electromotive force generated when the piezoelectric buzzer is subjected to a mechanical shock is applied to the output terminal of the integrated circuit connected to the piezoelectric buzzer, and this energy melts the normal aluminum wiring of the integrated circuit. Big enough.

If such a large energy is applied in the direction in which the external terminal 1 is positive, an extremely large current will flow into the P-type diffusion layer 12a by the function of the protection circuit according to the present invention. As is well known, the resistance of the power supply line in the integrated circuit is not zero, so this large current is generated by the P-type diffusion layer 12
The potential of the power supply line connected to a is changed in the positive direction. In this case, when the power supply line is Vss, Vss in the local area near the P-type diffusion layer 12a instantaneously rises, and the power applied to the circuit in the vicinity is short-circuited.

In the complementary MOS integrated circuit, there is a minute input capacitance at the input end of each logic gate, and even if the power is cut off (open) by the charge holding function of this capacitance, it is in the open state if it is a period of several ms. Is stored, and normal operation can be continued when the power is restored. However, the situation is different when the power supply is short-circuited. That is, since the diode is always present between the drain of the MOS transistor connected to the input end of the logic gate and the power supply line, the charge stored in the input capacitance is discharged to the power supply through the diode when the power supply is short-circuited. The memory of the state is lost in an instant. Therefore, the continuity of the operation of the circuit is lost even if the power source returns to the normal state, and the continuous operation such as the clock circuit causes a fatal failure in the important circuit.

On the other hand, the power line connected to the P-type diffusion layer 12a is Vdd
In this case, Vdd in the vicinity of the P-type diffusion layer 12a rises momentarily, but in this case, the state memorizing action due to the input capacitance is not lost. Therefore, if the power is restored to normal, the continuity of the circuit operation is continued. Is maintained.

That is, the power supply line connected to the P-type diffusion layer 12a must be determined in consideration of not only the function of the protection circuit but also the operation of the entire circuit when the protection circuit operates.

If the power supply line connected to the P-type diffusion layer 12a should be Vdd, the protection circuit of the present invention has the structure shown in FIG. 6, that is, the new guard P-type diffusion layer 12a is at least the P-type diffusion layer. The structure must be provided independently of 7.

On the other hand, if the power supply line connected to the new P-type diffusion layer for guard should be Vss, the protection circuit of the present invention is shown in FIG.
The structure shown in FIG. 2, that is, the P-type diffusion layer 7 for a new card
Either a structure in which a is at least shared with the P-type diffusion layer 7 or the structure shown in FIG. 6 is acceptable. However, the structure shown in FIG. 6 has a new P-type diffusion layer 12a and P
Since it needs to be separated from the type diffusion layer 7, a large extra area is inevitably required including the wiring area, and the degree of integration is reduced.

From this viewpoint, if the power supply line connected to the new guard P-type diffusion layer is Vss, the structure of FIG. 5, that is, the structure of providing the N-type diffusion layer 8 in the new P-type diffusion layer 7a should be adopted. Is.

In FIGS. 5 and 6, the P-type diffusion layer 3 is a typical example of a conventional protection circuit and has a diode function,
It is described as having a resistance function. However, since the protection circuit according to the present invention has a strong protection capability which has not been available in the past, the resistance function of the P-type diffusion layer 3 may be omitted and the diode function may be performed only in some cases by making the resistance function only the wiring resistance or the like. It is possible to satisfy the protection function.
As apparent from the above description, the present invention relates to the supplement of carriers flowing out to the N-type substrate 11 by the diode function of the P-type diffusion layer 3, and the resistance function of the P-type diffusion layer 3 It is needless to say that the protection function is improved by implementing the present invention even when the P-type diffusion layer 3 does not have a resistance function, since it is not directly related to. That is, for example, in FIG. 5, even if the first contact portion 2 and the second contact portion 4 are common, the operation by the practice of the present invention does not change, and it is necessary to change the above description. It's clear that nothing is.

As described above, according to the present invention, the circuit does not latch up even if a high voltage is applied to the external terminal 1, and the reliability is significantly improved. In the above description, for convenience of description, the substrate 11 and each diffusion layer provided on the substrate 11 are described as P-type or N-type, respectively, but can be easily understood by those skilled in the art. According to the present invention, if the phrase is corrected (for example, the high potential and the low potential of the power source are replaced), the present invention will be replaced with “N” for “P” and “P” for “N”. It is clear that it will hold even if replaced with. Therefore, in the claims, one of the P type and the N type is referred to as a first conductive type and the other is referred to as a second conductive type, and in the embodiment shown in FIG. The symbol 7a and the symbol 12a in FIG. 6 are
Both of them correspond to the symbol 12 in FIG. 4 and merely show that the mode of the diffusion layer 12 is different from that in FIG. 4, and accordingly, in the claims, FIG. In addition to the symbol 12 in FIG. 5, it is expressed as the diffusion layer 12 including aspects such as the symbol 7a in FIG. 5 and the symbol 12a in FIG.

[Brief description of drawings]

FIG. 1 is a plan view showing the structure of a conventional protection circuit, FIG. 2 is a cross-sectional view showing the structure of a conventional protection circuit, and FIG. 3 is a schematic view for explaining the defects of the conventional protection circuit. FIG. FIG. 4 is a sectional view schematically showing the structure of a protection circuit for explaining the gist of the present invention, FIG. 5 is a plan view showing the structure of the protection circuit which is one embodiment of the present invention, and FIG. It is a top view which shows the structure of the protection circuit which is another Example of this invention. 1 ... External terminal, 3,7,12,12a ... P type diffusion layer, 7a ... extension part, 9 ... N type diffusion layer, 11 ... N type substrate,

Claims (2)

[Claims] 1. An external terminal 1 is connected to a second conductive type diffusion layer 3 provided on a first conductive type substrate 11, and the diffusion layer 3 is further provided on the substrate 11 as a second conductive type. Connected to the first conductive type diffusion layer 8 provided in the diffusion layer 7, and a high-concentration first conductive type diffusion layer 9 is provided on at least a part of the periphery of the side surface of the diffusion layer 3. The second conductive type diffusion layer 12 is connected to the first power source, the diffusion layer 7 is in contact with the second power source, and the side surface of the diffusion layer 9 is at least partially separated from the diffusion layer 7. A protection circuit for a MOS integrated circuit, wherein the diffusion layer 12 is connected to the first power supply line. 2. An external terminal 1 is connected to a second conductive type diffusion layer 3 provided on a first conductive type substrate 11, and the diffusion layer 3 is further provided on the substrate 11 as a second conductive type. Connected to the first conductive type diffusion layer 8 provided in the diffusion layer 7, and a high-concentration first conductive type diffusion layer 9 is provided on at least a part of the periphery of the side surface of the diffusion layer 3. 1 is connected to a power source, the diffusion layer 7 is connected to a second power source, and a second conductive type diffusion layer 12 is further provided on at least a part of the side surface of the diffusion layer 9. A protection circuit for a circuit, wherein the diffusion layer 12 is a part of the diffusion layer 7.