JPH0636390U - Switching power supply - Google Patents

Abstract

(57) [Abstract] [Purpose] Each switching element is driven directly by a control pulse signal. [Configuration] A differentiating circuit 34 is branched and connected from control pulse signal VA and VC lines. In addition, F is applied to the differentiating circuit 34.
Connect the ET37. When the control pulse signals VA and VC rise, the FET 37 turns on for a fixed time. As a result, the pulse delay circuits 31 and 32 obtain output signals VB and VD having a predetermined delay period. [Effect] Control FET signals VA and VC for FETs 3 and 4
Can be directly driven by.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a resonance type switching power supply device capable of achieving zero voltage switching.

[0002]

[Prior art]

 Generally, in this type of resonance type switching power supply device, as shown in FIG. 3, 1 is a transformer that insulates the primary side and the secondary side from each other. A series circuit is connected to the MOS type FET 3 which is the first switching element. Further, 4 is a MOS type FET which is a second switching element connected in series with the MOS type FET 3, and between the drain and source of the FETs 3 and 4, capacitors 5 and 6 and diodes 7 and 8 are provided. Each parallel circuit is connected. By alternately switching these FETs 3 and 4, the DC input voltage VIN from the DC power supply 9 is intermittently applied to the primary winding of the transformer 1. At this time, the voltage induced in the secondary winding of the transformer 1 is full-wave rectified by the rectifying diodes 10 and 10A, and then smoothed by the capacitor 11 to the output terminals + V and -V as the DC output voltage VOUT. It is being supplied.

On the other hand, as a feedback loop for stabilizing the DC output voltage VOUT, a voltage detecting circuit 12 is connected between the output terminals + V and −V. The voltage detection circuit 12 changes the amount of light emitted from the light emitting diode 13 of the photocoupler based on the amount of change in the DC output voltage VOUT. This is controlled as a change in the output voltage of the phototransistor 14, which is a pulse width control circuit. The detection by the circuit 15 causes the pulse width control circuit 15 to output a control pulse signal having a pulse width corresponding to the change in the DC output voltage VOUT. An integration circuit 19 consisting of a resistor 17 and a capacitor 18 is inserted and connected between the pulse width control circuit 15 and the waveform shaping circuit 16, and the control pulse signal is an integration signal having a predetermined rise time and fall time. The waveform is supplied to the waveform shaping circuit 16. The waveform shaping circuit 16 compares the integrated waveform with a predetermined voltage level in each of the ON and OFF states of the integrated waveform, and when the integrated waveform exceeds this voltage level, it is connected to each FE T3,4. The H level signal is alternately supplied to the buffer circuits 20 and 21. These buffer circuits 20 and 21 are composed of driver ICs or elements, and although not shown, the buffer circuit 20 connected to the FET 3 is equipped with a drive transformer for high voltage output. Based on the output signal from the shaping circuit 16, the buffer circuits 20 and 21 supply sufficient drive signals to drive the FETs 3 and 4.

In this way, the drive signals having the pulse conduction widths according to the voltage fluctuations of the DC output voltage VOUT are output from the buffer circuits 20 and 21, respectively, so that the FETs 3 and 4 are turned on and off, and the transformer 1 is turned on. A stable DC output voltage VOUT can be obtained from the secondary side. Further, the pulse delay circuit including the waveform shaping circuit 16 and the integrating circuit 19 outputs an output signal having a predetermined delay time when the control pulse signal from the pulse width control circuit 15 is turned on and off. It is supplied to the buffer circuits 20 and 21. At this time, before the FETs 3 and 4 are turned on, the energy stored in the temporary winding of the transformer 1 is used to discharge the capacitors 5 and 6 connected to the FETs 3 and 4, respectively, so that the integration circuit 19 By setting the time constant of, the switching loss of the FETs 3 and 4 is minimized, and so-called zero voltage switching can be achieved.

[0005]

[Problems to be solved by the device]

 In the above-mentioned conventional switching power supply device, since the resistor 17 for setting the delay time is inserted and connected to the control pulse signal line between the pulse width control circuit 15 and the waveform shaping circuit 16, the FETs 3 and 4 are connected. The rapid charge / discharge of the gate-source capacitance during switching is limited, and it is impossible to directly drive the FETs 3 and 4 with the control pulse signal without providing the buffer circuits 20 and 21. In other words, the conventional circuit configuration requires separate buffer circuits 20 and 21 for driving the FETs 3 and 4, even with a small-capacity switching power supply device, reducing the number of parts and reducing cost. Was a significant hindrance.

Therefore, an object of the present invention is to solve the above problems and provide a switching power supply device capable of directly driving each switching element by a control pulse signal.

[0007]

[Means for Solving the Problems]

 The present invention has a transformer that insulates the primary side and the secondary side from each other, and a first and a second switching element connected in series. The first and second switching elements are alternately provided by a control circuit. A stable DC output voltage is obtained from the secondary side of the transformer by supplying a control pulse signal, and a pulse delay circuit is connected between the control circuit and the first and second switching elements. In a switching power supply device that achieves zero voltage switching by providing a predetermined delay period when the control pulse signal is turned on and off, the pulse delay circuit is a differentiation circuit that sets the predetermined delay period. Is branched and connected from the control pulse signal line, and a control pulse signal having the delay period is obtained based on the output of the differentiating circuit. Than it is.

[0008]

[Action]

 With the above configuration, since the differentiating circuit is connected by branching from the control pulse signal line between the control circuit and the first and second switching elements, the first and second switching elements are directly driven by the control pulse signal. it can.

[0009]

【Example】

 An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. The same parts as those in FIG. 3 in the conventional example are designated by the same reference numerals, and detailed description of the common parts will be omitted.

FIG. 1 is a circuit diagram of a switching power supply device according to the present invention. In FIG. 1, 31 and 32 are pulse delay circuits having the same circuit configuration, and one pulse delay circuit 32 is provided. Is directly supplied with the control pulse signal VA from the pulse width control circuit 15, and the other pulse delay circuit 31 is provided with a control pulse signal VA obtained by inverting the control pulse signal VA by the NOT circuit 33. VC is supplied. In each of the pulse delay circuits 31 and 32, 34 is a differentiating circuit in which a capacitor 35 and a resistor 36 are connected in series to set predetermined delay periods td1 and td2. The gate of the MOS type FET 37 is connected to the connection point with 36. A resistor 38 is inserted and connected to each of the control pulse signals VA and VC lines, and a diode 39 is connected across the resistor 38. Then, one end of the differentiating circuit 34 and the drain of the FET 37 are branched and connected from the control pulse signals VA and VC lines, respectively, and the other end of the differentiating circuit 34 and the source of the FET 37 are connected to the ground line. As a result, the pulse delay circuits 31 and 32 are configured.

Further, the output signal VB from the pulse delay circuit 32 is directly supplied to the gate of the FET 4 as a driving signal, while the output signal VD from the pulse delay circuit 31 is passed through the buffer circuit 40. It is supplied to the gate of FET3. However, the buffer circuit 40 merely boosts the output signal VD by the drive transformer, and is different from the buffer circuit 20 in the conventional example in that it has no driver IC or element. Is different.

Next, the operation of the above configuration will be described. When the FETs 3 and 4 are alternately turned on and off by the control pulse signals VA and VC output from the pulse width control circuit 15 to the pulse delay circuits 31 and 32, the voltage induced by the secondary winding of the transformer 1 Is rectified and smoothed by the rectifying diodes 10 and 10A and the capacitor 11, and is supplied to the output terminals + V and -V as the DC output voltage V OUT. Further, the pulse width control circuit 15 changes the pulse conduction time of the control pulse signals VA and VC based on the amount of change of the DC output voltage VOUT detected by the current detection circuit 12, and thereby the DC output voltage VOUT. Is controlled to be constant.

During this series of operations, the control pulse signals VA and VC shown in FIG. 3 are alternately supplied to the pulse delay circuits 31 and 32. In the pulse delay circuits 31 and 32, when the control pulse signals VA and VC rise to H level, a predetermined differential current flows through the capacitor 35 until the capacitor 35 is charged up. The gate potential of the FET37, which is the connection point of, rises, and the FET37 turns on. During this time, the output signals VB and VD lines of the pulse delay circuits 31 and 32 and the ground line are in a conductive state, and the potentials of the output signals VB and VD remain L level. After that, when the capacitor 35 is charged up and the differential current stops flowing through the capacitor 35, the gate potential of the FET 37 gradually drops and the FET 37 is turned off. At this time, since the control pulse signals VA and VC flow to the output signals VB and VD through the resistor 38, the potentials of the output signals VB and VD immediately switch to the H level, but the control pulse signals VA and VC rise. Predetermined delay periods td1 and td2 occur from time to the rise of the output signals VB and VD. On the other hand, when the control pulse signals VA and VC fall to the L level, the currents on the output signal VB and VD line sides directly flow to the control pulse signals VA and VC line sides via the diode 39, so that the output signal The potentials of VB and VD follow the control pulse signals VA and VC and immediately switch to L level. At this time, the delay periods td1 and td2 can be arbitrarily set by appropriately changing the time constants of the capacitor 35 and the resistor 36 that configure the differentiating circuit 34.

The pulse delay circuits 31 and 32 supply output signals VB and VD having predetermined delay periods td1 and td2 to the control pulse signals VA and VC to the gates of the FETs 3 and 4 as drive signals. At this time, during the delay periods td1 and td2, the energy stored in the temporary winding of the transformer 1 is used to discharge the capacitors 5 and 6 connected to the FETs 3 and 4, respectively. It is possible to achieve zero voltage switching similar to the conventional example.

As described above, according to the above embodiment, when the control pulse signals VA and VC rise, the FET 37 is turned on for a certain period of time based on the output of the differentiating circuit 34, so that the control pulse signals VA and VC are turned on. It is possible to obtain output signals VB and VD having predetermined delay periods td1 and td2. At this time, the differentiating circuit 34 for setting the delay periods td1 and td2 is branched and connected from the control pulse signal VA and VC lines, and the resistance value of the resistor 38 is small, so that the gate and source are switched when the FETs 3 and 4 are switched. Since the rapid charge / discharge during the period is not limited by the resistor 38, the FET 4 can be directly driven by the output signal VB from the pulse delay circuit 32, and the buffer circuit 40 simply drives the pulse delay circuit 32 from the pulse delay circuit 32. It is possible to drive the FET 3 simply by boosting the output signal VD of, and it is possible to easily reduce the number of parts in the power supply device and reduce the cost.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. For example, the first and second switching elements are not limited to MOS type FETs, and switching transistors can be used. Further, the present invention can be applied to various types of resonance type switching power supply devices.

[0017]

[Effect of device]

 The present invention has a transformer that insulates the primary side and the secondary side from each other, and a first and a second switching element connected in series. The first and second switching elements are alternately provided by a control circuit. A stable DC output voltage is obtained from the secondary side of the transformer by supplying a control pulse signal, and a pulse delay circuit is connected between the control circuit and the first and second switching elements. In a switching power supply device that achieves zero voltage switching by providing a predetermined delay period when the control pulse signal is turned on and off, the pulse delay circuit is a differentiation circuit that sets the predetermined delay period. Is branched and connected from the control pulse signal line, and a control pulse signal having the delay period is obtained based on the output of the differentiating circuit. And than can provide a possible switching power supply to drive the respective switching elements directly by the control pulse signal.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a switching power supply device according to an embodiment of the present invention.

FIG. 2 is a waveform diagram showing an operating state of each unit of the above.

FIG. 3 is a circuit diagram of a switching power supply device showing a conventional example.

[Explanation of symbols]

 1 transformer 3 FET (first switching element) 4 FET (second switching element) 15 pulse width control circuit (control circuit) 31, 32 pulse delay circuit 34 differentiating circuit

Claims (1)

[Scope of utility model registration request] 1. A transformer for insulating the primary side and the secondary side from each other, and first and second switching elements connected in series, wherein the control circuit alternates between the first and second switching elements. Is supplied with a control pulse signal to obtain a stable DC output voltage from the secondary side of the transformer, and a pulse delay circuit is connected between the control circuit and the first and second switching elements. In the switching power supply device, which has a predetermined delay period when the control pulse signal is turned on and off to achieve zero voltage switching, the pulse delay circuit sets the predetermined delay period. Is branched from the control pulse signal line and connected, and a control pulse signal having the delay period is obtained based on the output of the differentiating circuit. A switching power supply device characterized in that