JPH0635879A - Program loading system - Google Patents

Abstract

PURPOSE:To easily load plural programs in the program loading system of an information processor constituted of a higher rank panel and plural lower rank panels. CONSTITUTION:A monitoring CPU 11 and a memory 12 are provided in the higher rank panel 1 and a main CPU 23, a sub CPU 26, the memories 22, 25 and dual port memories 21, 24 are provided in the lower rank panel 2. Two kinds of the programs are simultaneously performed from the memory 12 to the main CPU 23 and one kind of the program between them is loaded between the main CPU 23 and the sub CPU 26 by resetting the sub CPU 26 by the main CPU 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program loading system, and more particularly to a program loading system for an information processing apparatus having a plurality of types of programs to be loaded.

[0002]

2. Description of the Related Art The conventional program loading method is based on an upper panel 3 and lower panels 4a, 4 shown in FIG.
In the information processing apparatus composed of b and 4c, a monitoring CP for monitoring the entire information processing apparatus is provided in the upper panel 3.
U31 and memory 32 accessible by the monitoring CPU 31
And a sub CPU 43 and a memory 4 accessible by the sub CPU 43 in each of the lower panels 4a, 4b, 4c.
2 and a dual port memory 41 accessible by the sub CPU 43, and the monitoring CPU 31 of the upper panel 3
Can access, for example, the dual port memory 41 of the lower panel 4a, and the supervisory CPU 31 and the sub CPU 43 communicate with each other via the dual port memory 41, so that the program in the memory 32 of the upper panel 1 can be stored in the lower layer. It was loaded in the memory 42 of the panel 2a.

[0003]

In this conventional loading method, the supervisory CPU which can access the load source memory in the upper panel communicates directly with the sub CPU which can access the load destination memory in the lower panel. , Monitoring CPU when there are two types of loaded programs
Select the program to load, and then load C
It is necessary to select the PU, and monitor C on the upper panel
There is a problem that the operation of the PU becomes complicated.

[0004]

The program loading method of the present invention is a program loading method for an information processing apparatus comprising an upper panel and a plurality of lower panels, wherein the upper panel monitors the entire information processing apparatus. And a first memory accessible by the monitoring CPU, wherein the lower panel has the monitoring C
A first dual-port memory accessible by a PU, a main CPU accessible by the first dual-port memory, a second memory accessible by the main CPU, and an access by the main CPU Second dual-port memory that can be used and a secondary CPU that can access the second dual-port memory
And a third memory accessible by the sub CPU.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an information processing apparatus to which an embodiment of the present invention is applied.

In FIG. 1, this application example is an upper panel 1.
And a lower panel 2a, 2b, 2c, and the upper panel 1 has a monitoring CPU 11 that monitors the entire information processing apparatus of this application example, and a load source memory 12 that the monitoring CPU 11 can access. Lower panels 2a, 2b, 2c
Each is a dual port memory 21, a main CPU 23 that can communicate with the monitoring CPU 11 via the dual port memory 21, a memory 22 that the main CPU 23 can access, and a dual CPU that the main CPU 23 can access.
Port memory 24 and dual port memory 24
It comprises a sub CPU 26 capable of communicating with the main CPU 23 via a memory and a memory 25 accessible by the sub CPU 26. The monitoring CPU 11 resets the main CPU 23 via, for example, a bus, and the main CPU 23 resets the sub CPU 26. For example, via a bus.

FIG. 2 shows the monitoring CPU 11 in this application example.
6 is a flowchart showing an operation procedure of each of the main CPU 23 and the sub CPU 26.

Next, the program loading in this application example will be described with reference to FIGS.

In this application example, the program for the main CPU 23 is called program 5, and the program for the sub CPU 26 is called program 6.

Further, in this application example, the program 5 is the memory 1
2 is loaded in the memory 22, the program 6 is loaded in the memory 12 from the memory 25, the flag 7 is in the dual port memory 21, and is a flag indicating the completion of loading of the programs 6 and 7, and the flag 8 is dual.・
This flag exists in the port memory 24 and indicates the completion of loading the program 6.

The program 6 of the program 5 is held in the memory 12, and the monitoring CPU 11 reads the program 5 and the program 6 from the memory 12 and the lower panel 2-a.
Write to the dual port memory 21 inside (S
1), the flag 7 is reset (S2), and the reset of the main CPU 23 is released (S3).

After releasing the reset, the main CPU 23 reads the programs 5 and 6 from the dual port memory 21, the program 6 writes the dual port memory 24 (S4), and resets the flag 8 (S4).
5) The reset of the sub CPU 26 is released (S6).

The program 5 is written in the memory 22 (S
7) After the reset is released, the sub CPU 26 reads the program 6 from the dual port memory 24, writes the program 6 in the memory 25 (S8), and sets the flag 8 (S9).

After confirming the setting of the flag 8 (S10), the main CPU 23 sets the flag 7 (S11), and the monitoring CP
After confirming the setting of the flag 7 (S12), U11 determines that the loading is completed.

[0016]

As described above, according to the present invention, in the program loading method of the information processing apparatus including the upper panel and the plurality of lower panels, the upper panel includes the monitoring CPU for monitoring the entire information processing apparatus, Monitoring CPU
Has a first memory accessible to the monitor, and the lower panel has a first dual-port accessible to the supervisory CPU.
A memory, a main CPU capable of accessing the first dual port memory, a second memory accessible by the main CPU, a second dual port memory accessible by the main CPU, and a second Dual port
Secondary CPU that can access memory and secondary CP
U has a third memory that can be accessed, and when the main CPU resets the sub CPU to load the program, the supervisory CPU of the upper panel and the lower panel when there are two types of programs to be loaded Two types of programs are loaded at the same time between the main CPUs of the
Main CP for loading one type of program between PUs
Since the U performs the resetting of the sub CPU, the operation of the monitoring CPU of the upper panel is simplified, and it is not necessary to allocate the memory space of the sub CPU to the memory space of the monitoring CPU. It has the effect that can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an information processing apparatus to which an embodiment of the present invention is applied.

FIG. 2 is a monitoring CPU 11 and a main CPU 2 in this embodiment.
3 is a flowchart showing an operation procedure of each of the sub CPUs 26.

FIG. 3 is a block diagram showing an example of a conventional information processing apparatus.

[Explanation of symbols]

 1 Upper Panel 3 Upper Panel 4a, 4b, 4c Lower Panel 11 Monitoring CPU 12 Memory 2a, 2b, 2c Lower Panel 21 Dual Port Memory 22 Memory 23 Main CPU 24 Dual Port Memory 25 Memory 26 Sub CPU 31 Monitoring CPU 32 memory 41 dual port memory 42 memory 43 sub CPU

Claims (1)

[Claims] 1. A program loading method for an information processing apparatus comprising an upper panel and a plurality of lower panels, wherein the upper panel monitors a CPU for monitoring the entire information processing apparatus and a first CPU accessible by the monitoring CPU. And the lower panel is the monitoring CPU.
First dual-port memory accessible by
A main CPU capable of accessing the first dual port memory, a second memory accessible by the main CPU, a second dual port memory accessible by the main CPU, and the second Secondary CPU that can access the dual port memory of
A third memory accessible by the sub-CPU,
A program loading method, wherein a program is loaded by the main CPU resetting the sub CPU.