JPH0635871A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To easily expand and change a system by connecting one or more processors whose processing functions are the same with at least one bus, providing plural buses whose processing functions are different and distributing processings to the buses by the processing functions of the respective buses. CONSTITUTION:This system is provided with a system management processor 100, the plural processors provided with the respective distributed functions, the plural buses provided for the respective distributed functions and a processor connection bus controller 102 for controlling the buses by connecting the respective buses. Since the buses are provided for the respective distributed functions, one or more processors provided with the same function are connected to one bus. Then, the processors respond to enquiry from the system management processor with the load information of the own processors or the feasibility of execution added. The system management processor selects the processor wish less loads from the processors with responses and instructs the processor of the execution of the processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system configuration and transaction processing used in a multiprocessor system in which functions are distributed.

[0002]

2. Description of the Related Art A conventional communication processing system uses a single interprocessor bus as described in "Examination of Redundant Configuration of Distributed Processing Processors" (Switching System Research Group of IEICE, SE86-17). Various processors are connected. The functions of the respective processors are distributed and processing is performed according to the deployed functions. A typical example of the function of this processor is a processing system function (exchange control processor, processor) for processing a processing request input to the system.
There are a communication control processor, a file control processor, a line control processor) and a system management system function (management processor) for managing the entire system. A plurality of processors having processing system functions are connected and added according to the traffic volume. Moreover, it is general that one processor having a system management function is connected. The system management information required for transmitting information between the processors is processed by the functions of the respective processors. The management processor is preset with station information data indicating the system configuration and system information data such as the function of each processor in order to manage the system.

The control method for transmitting and receiving information (inter-processor communication) between the processors having the above-mentioned functions is described in "Revised Digital Exchange Method" (August 10, 1989, electronic information Pp. 131-135 of the Institute of Communications. The related art is managed and controlled by a special device such as an inter-processor communication controller (IPC). The IPC periodically monitors each processor. When an access request to another processor occurs, the IPC gives the bus right to the processors on the sending side and the receiving side, and waits for the bus use request from the other processor. There is. Since the IPC performs such monitoring, station information data indicating the system configuration and system information data such as the function of each processor are preset.

Further, as described in "Interprocessor communication control method" of Japanese Patent Laid-Open No. 3-087962, a processor for registering a congestion level and a state for each processor is provided to distribute the load on the processors. There is.

[0005]

The above-mentioned prior art has the following problems because it does not sufficiently consider expansion or alteration such as addition or reduction of processors or system change when a new functional processor is added.

When the number of processors is changed due to an increase or decrease in the number of processors, a failure, or the like, or when the processor state changes, the management processor and the management target in each processor change, so software work is performed to show the system configuration. The information data is being changed. Also, the system information data managed by the system configuration management software on the management processor is changed. The data to be changed that is affected by these processor states is data related to the transmission and reception of information between processors (interprocessor communication) that is indispensable for providing services, and is scattered in each processor. It takes a long time to change the data to match the system state, and also has a great influence on the service during that time (temporary service stop, etc.).

Further, in the system using the IPC or the register as a device for controlling the inter-processor communication including the load balancing control, when the number of processors or the processor state changes, the hardware such as the register is newly added. Have been added to. For this reason, there is a problem that the hardware cost increases, and especially when the network is constructed by connecting a plurality of systems, the network cost increases.

Further, although global communication (broadcast communication) is effective for file loading and data transfer to a processor group having a specific function, bus management available as a general-purpose product notifies all processors at once. It is considered to do. However, in the case where the functions are distributed among a plurality of processors, the general-purpose bus does not give sufficient consideration to the case where the broadcast communication is performed only to the plurality of processors having the same function. In such a case, hardware and software are affected in constructing a distributed multiprocessor system, and there are problems in terms of expandability and cost.

An object of the present invention is to solve the above problems.
An object of the present invention is to provide a multiprocessor system that allows easy expansion and modification of the system.

[0010]

In order to achieve the above object, in a processor system having a plurality of processors whose functions are distributed, one or more processors having the same processing function are connected by at least one bus to perform processing. The system management processor includes a plurality of buses having different functions, and allocates processing to the buses according to the processing function of each bus.

The plurality of processors send a processing request to the system management processor, and the system management processor includes a scenario table in which a process and a bus corresponding to the processing request from the processor are recorded in advance. The processing can be distributed to the corresponding buses by referring to the scenario table.

Further, the system management processor inquires of a processor connected to a bus corresponding to the processing whether or not the processing can be executed, and the processor responds to the inquiry from the system management processor about whether or not the processing can be executed. Then, the system management processor selects a processor that executes the process from among the executable processors, and instructs the processor to execute the process. Further, instead of the inquiry about the executability, the load of each processor is inquired, the processor responds to the inquiry from the system management processor by adding the load information of its own processor, and the system management processor responds. It is also possible to select a processor with a lighter load from among the processors having the above-mentioned problems and instruct the processor to execute the processing. In this case, by providing a field for storing data representing load information on the signal used during inter-processor communication, and by synergizing with data transfer, the number of signals for inquiring about the feasibility of execution is reduced and the load between devices is reduced. Can be leveled.

The system management processor can make a broadcast inquiry to a processor connected to the bus corresponding to the processing.

[0014]

Each processor sends a processing request to the system management processor. The system management processor
A scenario table in which a process corresponding to a processing request from the processor and a bus are recorded in advance is provided, and the load or executability of each processor is broadcast to the bus corresponding to the processing request by referring to the scenario table. Contact us. The processor responds to the inquiry from the system management processor by adding load information of the own processor or executability. The system management processor selects a processor having a smaller load from among the responding processors and instructs the processor to execute the process.

Thus, by collecting the system configuration information data as a scenario table in the system management processor, if there is a change in the processor state in the system, the data change closed in the system management processor is sufficient. There is no information to be changed on this processor. Furthermore, by making the system management processor involved in interprocessor communication performed by the processing system processor, whether the processing system processor responds to the system management processor or sends it to the outgoing line from its own processor. Can be determined for each function, and the influence on the processing system processor can be eliminated in a situation where the processor state changes such as increase or decrease. Further, since the processing system processor does not need the function of checking the status of the partner device and the partner device selection function, it is possible to reduce the amount of software and the number of dynamic steps required for interprocessor communication.

Further, the system management system processor inquires of the processor group corresponding to the next stage whether or not it can be executed, and the processor to be processed is selected based on the result.
The system management system processor can determine the partner processor without knowing the processor status of each processing system by assuming that the processor that has returned a response is normal.

Furthermore, since the system management system processor uses the broadcast communication to select the processing system processor, the processing system processor can be selected without considering the system configuration.

Further, since only the system management processor determines the processor of the processing system for performing the processing of the next stage, the load on each processor can be leveled, and the throughput of the entire system can be maximized. There is also the effect that you can make the most of it.

Further, by introducing a field for storing data for expressing load information on the signals of the system management system processor and the processing system processor, the load information can be selected from the signals of the processing system processor which has made a response. Since it is possible to see the data representing, the system management processor can reduce the number of signals for inquiries.

Further, since a plurality of processor buses are provided and the processor of the processing system connected to each bus is fixed for each processing function, the processor bus is selected by the software processing to perform the broadcast communication. If this is done, the broadcast control signal detected by the own processor must be fetched by the own processor for hardware control, so it is necessary to verify the broadcast communication address during the broadcast communication. Therefore, it is possible to eliminate the need to newly add a mechanism for identifying the processor group corresponding to each function.

[0021]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an example of a system configuration of a multiprocessor system according to this embodiment. Figure 2
FIG. 3 is a diagram showing a format of a signal used for communication between processors. FIG. 3 is a diagram showing the configuration of the communication processing scenario information table arranged in the system management processor. FIG. 4 is a diagram showing a network configuration example when the present embodiment is used in a switching system. FIG. 5 is a diagram showing a packet format used in the network in FIG.

In FIG. 1, a multiprocessor system is a system management processor device 1 for system management.
00, a plurality of processors having distributed functions, a plurality of buses provided for each distributed function, and a processor connection bus control device 102 for connecting the buses to control the buses. There is. A bus is provided for each distributed function, and therefore one or more processors having the same function are connected to one bus. In FIG. 1, the ACT bus 103 has three slave processors 108A, 108B, ...
108C is connected. In addition, the ACT bus 104
11 slave processors having the same function
0A, 110B and 110C are connected. Similarly,
A slave processor is also connected to the ACT bus 105. ACT to distribute functions for each bus
The processors of the system bus 103 and the ACT system bus 104 are
The processors may have different functions, or may have the same processor when the load increases.
For example, the functions can be distributed to a switching control processor, a communication control processor, a file control processor, a line control processor and the like. In FIG. 1, slave processors 108A, 108B, and 108C are line control processors, which respectively connect intersystem connection lines 111 which connect to other systems, and transmit / receive data to / from other systems. Further, the bus may have a dual configuration by providing a bus for a spare system in addition to a bus for each function. Each processor includes a connection control unit 107 for connecting to the bus. The connection control unit 107, when receiving the data, decodes the destination added to the data,
It is determined whether the data is addressed to its own processor. The bus is time-division multiplexed, and a time slot is assigned to each processor. The connection control unit 107 sends a signal to the time slot allocated when sending a signal on the bus. Since a predetermined processor identification number is assigned to each processor, the connection control unit 1
07 determines whether or not it is addressed to itself by determining whether or not it matches the identification number of its own processor. The system management processor device 100 refers to the communication processing scenario information table 300 shown in FIG. 3 to manage this system. The processor connection bus control device 102 distributes data to each bus based on the destination.

Data transmission / reception between processors is performed in a data format as shown in FIG. Information indicating a predetermined signal type such as a processing request is added to the signal type information 202. The connection destination processor bus system number information 203 indicates the bus number of the processor that performs the processing, and at the time of broadcasting, information indicating that it is broadcasting is added. The slave processor number 204 indicates a slave processor number. The processor load information 205 indicates the usage rate of each processor. The transmission / reception data section 206 stores data.

The communication processing scenario information table 300 shown in FIG. 3 is provided for each processor bus system number and has a plurality of scenario information 301 for each processor bus system. The scenario information includes a destination processor connection bus system number 302, a transmission signal type 303, and a reception signal type 3
04 is included. For each received signal type 304 of the received signal type, the transmitted signal type 303 to be transmitted next
And a destination processor connection bus system number 302. For example, in the communication processing scenario information table 300, as the scenario information of the ACT bus 103, a signal type of data reception indicating that data has been received from another system is shown as a reception signal type 304, and a transmission signal type 303 is shown. A data exchange signal type indicating that data should be exchanged is indicated, and the destination processor bus system number information 302
ACT bus 1 which is the bus system of the switching control processor
04 is shown. A scenario table as shown in FIG. 3 is defined in the system management processor device 100 in advance as management information. If there is a bus system having the same function, a plurality of numbers are indicated in the destination processor bus system number information 302, or the same bus identification number is given.

Next, the operation of the communication process in FIG. 1 will be described.

In FIG. 1, an intersystem connection line 111
When a communication processing request is sent to this communication system from another system via the AC, the AC for performing the first line control processing.
It is accepted by the T-system 1-bus connection slave processor 108. When the processor 108 completes the communication processing in its own processor, the processor 108 executes inter-processor communication with the system management processor device and requests the next communication processing. The request for communication processing uses a signal according to the format shown in FIG. A processing request is set in the signal type information 202 on the inter-processor signal format 201, the connection destination processor bus system number information 203 is the identification number of the bus system to which the processor of the own device is connected, and the slave processor number 204 is , The number of the processor 108 of its own device is set, sent to the ACT system 1 bus 103 via the connection control unit 107, and received by the system management processor device 100. In addition, the transmission / reception data section 20
In 6 is stored the data to be transferred to the next communication processing phase which is processed by the communication processing performed by the processor 108. The connection control unit 107 sends data to the assigned time slot.

Upon receiving the request signal, the system management processor unit 100 analyzes the signal 201 and analyzes the signal type information 2
The received signal type is taken out from No. 02, and the processor bus system number to which the slave processor which issued the signal is connected is taken out from the connection destination processor bus system number information 203. The contents of the transmission / reception data section 206 are temporarily stored in the storage means. Then, the communication processing scenario information table is referred to by the two pieces of information of the signal type and the processor bus system number. Communication processing scenario information table 3
00 is indexed by the processor bus system number, the corresponding scenario information is viewed, and the scenario information having the received signal type 304 that matches the received processing request is searched for. Then, the corresponding transmission signal type 303 extracted from the scenario information is written in the signal type information 202 of the signal format 201, and the destination processor connection bus system number 302 extracted from the scenario information and the information indicating the broadcast are connected. The destination processor bus system number information 203 is set and a signal is sent to the processor connection bus control device 102. At the same time, the system management processor device 100 activates a timer to monitor the response time. The processor connection bus control device 102 refers to the connection destination processor bus system number information 203 to detect the bus system number to be connected. The data from the system management processor device 100 is sent to the bus having the detected bus system number. In the corresponding bus, the destination is a bus system number and broadcast information is added to the broadcast communication.

Broadcast communication is performed by slave processor A110A and slave processor B connected to the corresponding bus.
When the signal reaches 110B and the slave processor C110C, a signal is taken in by the connection control unit 107, it is determined that the bus system of the own processor is broadcast by referring to the connection destination processor bus system number information 203, and the data is received. To do. Also, the connection control unit 107 generates a response signal. The response signal is the signal type information 20 of the signal format 201.
2, the slave processor number 204 is set to the processor number of its own device, the processor load information 205 is set to the collected information such as the own processor usage rate, and the response is sent to the system management processor device 100. Will be returned. When the system management processor device 100 receives the response, it compares the processor load information 205 on the signal with the minimum value in the responses that have already arrived, and if it is smaller, extracts the processor number from the slave processor number 204 and uses it as load information. Store together in storage means. This process is repeated for the response received while the timer that started the time-out, and the processor number stored at the time-out is selected as the processor for the next process. As a result, it is possible to select the processor with the smallest load information from among the responses that have arrived for a certain period of time and allow the smallest processor to perform processing without managing all the processor numbers.

Upon completion of the selection, the system management processor unit 100 causes the communication processing scenario information table 300
By the processor bus system number and looking at the corresponding scenario information, the scenario information having the reception signal type 304 that matches the response of the signal type information 202 on the received signal is searched for, and the transmission signal type 30 extracted from the scenario information is searched.
3 is written in the signal type information 202 of the signal format 201, the content of the transmission / reception data section 206 that is temporarily received and received from the slave processor that has performed the communication process is added, and the selected processor number is added to the slave processor. It is added to the number 204 and transmitted by individual communication.

The processor connection bus control device that has received the transmission request specifies the communication destination processor by the connection destination processor bus system number information 203 and the slave processor number 204 on the signal and transmits the signal.

Next, with reference to FIG. 4, a case where the present embodiment is applied to the exchange system will be described. In FIG. 4, the exchange is equipped with the above-mentioned multiprocessor system, and is connected to another network through an intersystem connection line. Other networks include public networks and A company networks, and terminals that are subscribers may be connected to the exchange. In the network shown in FIG. 4, for transmitting / receiving data, for example, the packet format as shown in FIG. 5 is used. In FIG. 4, the case where a packet is transmitted from the subscriber terminal to the terminal of the company A network is taken as an example. The packet originated from the subscriber terminal is accepted by the ACT system 1 bus connection slave processor 108 via the inter-system connection line in the exchange. When the processor 108 completes the communication processing in its own processor, it executes inter-processor communication with the system management processor device, adds a signal type indicating data reception to the system management processor device, and adds it to the data section 206. Store the received packet data and request communication processing. System management processor device 1
00 refers to the communication processing scenario information table 300 in which the ACT bus 103 is stored, and the received signal type 30
The area where data reception is shown in 4 is searched. After searching, the corresponding transmission signal type 303 data exchange transmission type and the destination processor bus system number information 302 ACT
System bus 104 connected processor bus system number information 204
To generate and send a signal format. AC
When the slave processor A110A, the slave processor B110B, and the slave processor C110C on the T bus 104 receive the data from the system management processor device, the load information in the device itself, the signal type indicating the response, and the slave processor number. Is added and sent. The system management processor device selects the processor with the smallest load information (for example, the slave processor C110C) from the responses that have reached a certain time, generates the signal format for the exchange processing, and stores it in the storage means. Information of the data part is added and transmitted. The slave processor C110C analyzes the destination address of the packet, which is the data of the transmission / reception data section of the received signal format, and performs the exchange operation. Next, a communication processing request is sent to the system management processor unit so as to be sent from the inter-system connection line of the sending destination. Similarly, the system management processor device transmits a signal to the ACT bus of the processor having the inter-system connection line of the transmission destination by referring to the scenario information.

In this way, the slave processor unit makes a processing request to the system management processor unit 100, and the system management processor unit broadcasts to the processor bus having the processor function group based on the communication processing scenario information table. The communication processing is performed by repeating the communication and determining the slave processor to be processed, and the processor having the communication processing function sends the processed data to the outgoing line from the communication processing system. , A series of communication processing is completed.

According to this embodiment, the processor of the system management system can inquire of the processor group corresponding to the next stage whether or not the processor can be executed, and the result can be used to select the processor of the processing system. As a result, the system management processor does not need to know the device state of each processor, so there is no effect due to a failure or the addition or removal of processors. In addition, since the processor of the processing system does not need to know the system configuration of the entire system and the state of the partner processor, such data can be reduced, and the device state and system configuration change due to failure or increase / decrease. However, there is no effect on the processor of the processing system because no data change is required. Therefore, the serviceability and maintainability are improved.

Further, only the system management processor is
The processor of the processing system can be selected and determined by using the broadcast communication, and the load given to each processor can be leveled, and the throughput of the entire system can be maximized. In addition, the function to select the partner processing system processor is integrated into the system management system processor, the system management system processor inquires whether it can be executed, and the response is used to select the partner processing system processor for leveling. it can.

Further, according to the present embodiment, by separating the processor buses to be connected for each processor function group,
By selecting a destination bus and uniformly performing broadcast communication on the bus, broadcast communication can be realized in subgroup units (function group units). As a result, the broadcast communication signal arriving at the own processor must be taken in by the own processor without fail, so that the partial broadcast communication function in sub-group units can be executed.
Further, even if the construction is carried out, it can be performed without affecting other processor groups, so that the serviceability is improved.

[0037]

According to the present invention, expansion and modification can be easily performed in a multiprocessor system.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram of a multiprocessor communication processing system showing an embodiment of the present invention.

FIG. 2 is a format of a signal used for communication between a master device and a slave device.

FIG. 3 is a configuration diagram of a scenario table in which information used for communication processing control performed by a master processor device is set.

FIG. 4 is a network configuration diagram when this embodiment is used for a switching system.

FIG. 5 is a packet format.

[Explanation of symbols]

100 ... System management processor device, 101 ... System management processor connection bus, 102 ... Processor connection bus control device, 103 ... Processor connection bus ACT system 1, 104 ... Processor connection bus ACT system 2 , 105 ... Processor connection bus ACT system 3, 106 ... Standby system processor connection bus, 107 ...
..Connection control unit, 108 ... ACT system 1 bus connection slave processor, 109 ... ACT system 3 bus connection slave processor, 110A ... ACT system 2 bus connection slave processor A, 110B ... ACT system 2 Bus connection slave processor B, 110C ... ACT system 2 bus connection slave processor C, 111 ... System connection line, 201 ... Processor signal format, 202 ... Signal type information, 203 ... Connection Destination processor bus system number information, 204 ... Own processor number information, 205 ... Processor load information, 206 ... Transmission / reception data section, 300 ... Communication processing scenario information table, 301 ... Scenario information, 302 ... Destination processor connection bus system number, 30
3 ... Transmission signal type, 304 ... Reception signal type.

Claims (6)

[Claims] 1. A processor system having a plurality of processors whose functions are distributed, wherein one or more processors having the same processing function are connected by at least one bus, and a plurality of buses having different processing functions are provided. On the other hand, a multiprocessor system having a system management processor that distributes processing to each processing function of each bus. 2. The processor according to claim 1, wherein the plurality of processors send a processing request to the system management processor, and the system management processor records in advance a processing and a bus corresponding to the processing request from the processor. A multiprocessor system comprising a scenario table to be stored, and processing is distributed to a corresponding bus by referring to the scenario table. 3. The system management processor according to claim 1, wherein the system management processor inquires of a processor connected to a bus corresponding to the processing whether or not the processing can be executed, and the processor responds to an inquiry from the system management processor. A multiprocessor system, wherein the system management processor selects a processor that executes a process from among the executable processors and gives an instruction to execute the process to the processor in response to execution propriety. 4. The system management processor according to claim 1, wherein the processor connected to the bus corresponding to the processing inquires the load of each processor, and the processor responds to an inquiry from the system management processor. The system management processor selects a processor with a smaller load from among the responding processors and instructs the processor to execute processing by adding the load information of its own processor. Multiprocessor system to do. 5. The multiprocessor system according to claim 3 or 4, wherein the system management processor broadcasts an inquiry to a processor connected to a bus corresponding to the processing. 6. A processor management method for a multiprocessor system in which one or more processors having the same processing function are connected by at least one bus and a plurality of buses having different processing functions are provided, wherein a processing request from each processor is provided. In advance, a process and a bus corresponding to the above are defined, the load of each processor is inquired to the bus corresponding to the processing request by broadcast, and a processor with a smaller load is selected from the response of loads from each processor, A processor management method characterized by instructing a processor to execute processing corresponding to a processing request.