JPH0635805A - Microcomputer having p-rom built-in - Google Patents

Abstract

PURPOSE:To facilitate the analysis of the P-ROM data against the occurrence of a fault while keeping the security of secret to the outsiders for a microcomputer which contains a P-ROM having its verifying inhibition protection mode. CONSTITUTION:A microcomputer contains a protection information memory cell 2 consisting of a P-ROM cell, a protection decoder 20 which inputs and decodes the data on the cell 2, and an address modifying circuit 4 which modifies the address information on a P-ROM in a verifying mode of the P-ROM with the output signal of the decoder 20. The decoder 20 consists of a logic circuit which excludes the combination of two different types of data and becomes active only when the data except those combined data are inputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a P-ROM (programmable ROM) built-in microcomputer, and more particularly to a P-ROM.
-It relates to a microcomputer having a verify prohibition protection mode for protecting the confidentiality of ROM data.

[0002]

2. Description of the Related Art Normally, a microcomputer having a built-in P-ROM enables program data to be written and verified by a P-ROM writer.
Program data input / output port for storing or storing stored program data in M, and P-
It has a P-ROM mode setting port for setting the ROM program mode.

FIG. 6 shows a P-ROM mounted in a conventional P-ROM built-in microcomputer having the above-mentioned functions.
It is a block diagram which shows typically the basic composition of ROM and its peripheral circuit. In FIG. 6, the P-ROM 1 includes a read circuit 17, a write circuit 18, and an address decoder 3.
The program data addressed by the address decoder 3 is connected to the program data input / output port 9 from the read circuit 17 via the bus changeover switch 10 and the instruction decoder 6 and the gate circuit 40. The output of the program counter 5 that generates address information is input to the address decoder 3. In addition, the P-ROM mode setting port 8
The P-ROM mode decoder 7 is connected to the -ROM mode decoder 7 and generates a P-ROM control signal such as a write signal PGM or a program verify signal VER.

In the P-ROM 1 built in such a microcomputer, the P-ROM mode setting port 8
By inputting data to the gate circuit 40, the gate circuit 40 is switched and P- via the program data input / output port 9 is input.
It is configured so that data can be input to or output from the ROM.

As described above, in this type of microcomputer, the P-R
It is possible to easily input and output the data stored in the OM. However, for the convenience of handling as described above, by setting the operation mode to the verify mode by using the P-ROM writer, the third party can make the P-R
The program data stored in the OM can be easily read. Therefore, there is a problem that the security protection for the data stored in the P-ROM is incomplete. In order to avoid this problem, there is a method of incorporating a protection circuit in the microcomputer itself. FIG. 7 shows a typical example thereof.

In FIG. 7, a protect information memory cell 2 is provided at a specific address of the P-ROM 1 and data is written in the protect information memory cell 2 after the completion of programming and verification of program data. This data is analyzed by the call protect decoder 20 at the start of verification, and the gate circuit 40 is controlled according to the result.
Reading of program data via the input / output port 9 is prohibited.

[0007]

As described above, the conventional microcomputer of this type has the function of inhibiting the reading of the program data stored in the P-ROM by providing the protect circuit. However, in the case of such a protect circuit, once the data is written in the protect information memory cell, it becomes impossible to confirm the program data thereafter.
There is a drawback that the ROM data analysis becomes difficult.

[0008] Therefore, the technical problem of the present invention is to solve the above-mentioned drawbacks of the prior art and to provide a P-R with a built-in microcomputer.
It is an object of the present invention to provide a novel microcomputer with a built-in P-ROM provided with means for facilitating the analysis of P-ROM data when a failure occurs while maintaining the security function for the third party of OM data.

[0009]

A microcomputer with a built-in P-ROM according to the present invention is a protect information memory cell composed of a plurality of P-ROM cells, and a protect for inputting and decoding data of the protect information memory cell. It is characterized by having a data decoder and an address modification circuit for modifying the address information of the P-ROM only in the verify mode of the P-ROM by the output signal of the protected data decoder.

Further, in the microcomputer with a built-in P-ROM of the present invention, the protect data decoder has a logic circuit which eliminates two different data combinations and generates an active signal only when data other than the data combinations is input. Is characterized by.

[0011]

In the present invention, the protect information memory cell is composed of a plurality of P-ROM cells. The data of the protect information memory cell is decoded by the protect data decoder, and the address information of the P-ROM is modified by the address modification circuit.

[0012]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a concrete configuration example of a P-ROM and its peripheral circuits in a P-ROM built-in microcomputer according to the present invention. FIG. 2 is a diagram showing a circuit configuration example of the protect control circuit of FIG.

First, the configuration of a P-ROM built-in microcomputer according to an embodiment of the present invention will be described.

In FIG. 1, a P-ROM 1 has a protect information memory cell 2 assigned to a specific address, and program data addressed by the address decoder 3 is input to a protect mode decoder 20 via a read circuit 17. At the same time, it is input to the instruction decoder 6 or the program data input / output port 9 via the bus changeover switch 10.

The output of the program counter 5 which generates the address information of the P-ROM is input to the address modification circuit 4, and the output of the address modification circuit 4 is the address decoder 3.
Entered in. Also, the P-ROM mode setting port 8 for setting the program mode of the P-ROM is
The P-ROM mode decoder 7 is connected to the M mode decoder 7, and the P-ROM mode decoder 7 receives a program mode signal PGM, a program verify mode signal VER, a zero clear mode signal CLR for clearing the program counter to zero, and an inhibit mode signal INH for switching between the modes.
, Each P-ROM control signal is generated.

As shown in FIG. 2, the protect control circuit 1
9 is a first delay circuit 37 for inputting the CLR signal,
Inverter 3 connected to this first delay circuit 37
1. An AND gate 24 that performs a logical product operation of the output signal of the inverter 31 and the CLR signal is provided. Furthermore, the output signal of the AND gate 24 is input to the set terminal, and the output signal of the logical sum operation result of the VER signal and the PGM signal by the OR circuit 22 is input to the reset terminal.
An RS flip-flop circuit 34 and a second RS flip-flop circuit 35 for inputting the INH signal to the set terminal and inputting the output signal of the AND gate 24 to the reset terminal are provided. Further, it has an AND gate 25 connected to the output terminals of these RS flip-flop circuits 34, 35, a second delay circuit 38 and an inverter 32 connected in series to this AND gate 25. Also, an AND gate 26 that performs a logical product operation of the output signal of the inverter 32, the output signal of the AND gate 25, and the signal of the CLR signal that has passed through the inverter 33, and the output signal of the AND gate 26 is input to the set terminal. A 3RS flip-flop circuit 36 is provided. On the other hand, the VER signal passes through the third delay circuit 39 and is connected to an OR gate that performs a logical product operation of the PGM signal and the CLR signal.
The output signal of the gate is the third RS flip-flop circuit 36.
Input to the reset terminal of. The third RS flip-flop circuit 36 outputs the signal a based on the signals input to the R and S terminals. Therefore, each P-ROM control signal is input to the protection control circuit 19 and outputs the output signal a.

Next, the operation of writing data to the P-ROM 1 built in the microcomputer by the P-ROM writer will be described.

FIG. 3 shows a timing chart during programming. First, the P-ROM mode setting port 8 sets the zero clear mode to initialize the program counter 5. At this time, the CLR signal is generated. After that, the inhibit mode is set before shifting to the program mode in order to prevent the P-ROM mode signal from being erroneously generated. At this time, the protect control circuit 19 generates a signal a and enters the address modification circuit to select the address of the protect information memory cell 2 mapped to a specific address. However, reading is not executed in this mode. After that, the program mode is entered and the PGM signal is generated. This PGM signal resets the RS flip-flop at the final stage of the protect control circuit 19, and the signal a becomes low level. Therefore, the data input from the input / output port 9 is written into the cell of the P-ROM address corresponding to the value of the program counter 5 by the write circuit 18. After that, the written data is confirmed by switching to the verify mode via the inhibit mode. At this time, since the signal a is already at the low level, the RS flip-flop 11 is not set and the signal c remains at the low level. Therefore, even if the VER signal is generated in the verify mode, the signal d becomes the low level and the address is modified. Absent. Therefore, the data of the written address can be read normally.

Next, the operation of reading data from the P-ROM 1 built in the microcomputer by the P-ROM writer will be described.

FIG. 4 shows a timing chart of each control signal at the time of verification of the microcomputer shown in FIG.

First, the operation at the time of normal verification before protection setting will be described.

In FIG. 4, (1) shows the timing before the protect setting.

First, the zero clear mode is set by the P-ROM mode setting port in order to initialize the program counter 5. At this time, the CLR signal is generated. Then P
-Inhibit mode is set before shifting to verify mode to prevent erroneous generation of ROM mode signal. At this time, the protect control circuit 19 generates a signal a and enters the address modification circuit to select the address of the protect information memory cell 2 mapped to a specific address. After that, the mode is shifted to the verify mode and the VER signal is generated. This VER signal resets the RS flip-flop at the final stage of the protection control circuit 19 via the delay circuit 39, but the signal a holds the high level for the time corresponding to the delay time of the delay circuit C. Therefore, during this period, the information in the protect information memory cell 2 is read by the read circuit 17 and input to the protect data decoder 20. Further, since the signal a is at high level, the output value of the protect data decoder 20 is transmitted to the set input of the RS flip-flop 11 by the AND circuit 13.

Here, the structure of the protect data decoder 20 is a logic circuit as shown in FIG. The logic circuit shown in FIG. 5 inputs an 8-bit data composed of bit 0 (b0) to bit (b7) and outputs a high level to the output signal b when the input data is other than FFH or 05H.

Generally, since the P-ROM cell in the erased state is in the high level state, it becomes FFH in the case of the 8-bit structure. Therefore, the protect information memory cell 2 is FFH in the initial state, and in this case, the output of the protect data decoder 20 becomes low level. Therefore, the RS flip-flop 11 is not set and the signals c and d are kept at low level. Therefore, since the output of the program counter 5 is not affected by the address modification circuit 4, the P-ROM
The address is incremented by one from the zero address,
Performs a normal read operation.

The protect mode is set by writing data to the protect information memory cell 2 when the program contents have been checked through the series of operations described above. Here, the protect information memory cell 2
In order to write the data to, the program counter 5 is overflowed and the carry signal Ca is generated. At this time, since the address points to the protect information memory cell 2, any data can be written in the program mode. Here, it is permitted to write arbitrary data only in the upper 4 bits. As an example, assume that AH is written in the upper 4 bits. In this case, the protect information memory cell 2 becomes AFH.

Next, the operation in the case where the verify is attempted after the protection is set by the above-mentioned means will be described.

FIG. 4 shows a timing chart at the time of verification after protection is set in (2).

First, the zero clear mode is set in order to initialize the program counter 5 through the P-ROM mode setting port. At this time, the CLR signal is generated. Then P
-Inhibit mode is set before shifting to verify mode to prevent erroneous generation of ROM mode signal. At this time, the protect control circuit 19 generates a signal a and enters the address modification circuit to select the address of the protect information memory cell 2 mapped to a specific address. After that, the mode is shifted to the verify mode and the VER signal is generated. This VER signal resets the RS flip-flop at the final stage of the protection control circuit 19 via the delay circuit 39, but the signal a holds the high level for the time corresponding to the delay time of the delay circuit 39. Therefore, during this period, the information in the protect information memory cell 2 is read by the read circuit 17 and input to the protect data decoder 20. Further, since the signal a is at high level, the AND circuit 13 causes the protect data decoder 20 to
Is transmitted to the set input of the RS flip-flop 11. Here, from the protect information memory cell 2, A
FH is read and the output signal b of the protect data decoder 20 becomes high level. During this period, since the signal a is kept at high level, the RS flip-flop 11 is set and the signal c becomes high level. Therefore, the signal d maintains the high level while the VER signal is generated, and the output value of the program counter 5 is modified by the OR circuits 14 to 16 in the address modification circuit 4 and the address is fixed to a constant value. . Therefore, thereafter, reading of data corresponding to each address of the P-ROM is substantially prohibited.

The above-described series of operations makes it impossible for a third party to read P-ROM data.

Next, a procedure for canceling this mode after setting the protect mode will be described.

First, the protect information memory cell 2 is addressed by setting the program mode and generating the carry signal Ca of the program counter 5. In this state, additional writing is performed. At this time, 05H is written as additional write data. Due to the characteristics of the P-ROM cell, AND logic is taken for each bit, and as a result, 05H is set in the protect information memory cell 2. When the data of 05H is input to the protect decoder 20, the output becomes low level and the RS flip-flop 11 is not set. Therefore, when the verify mode is set thereafter, the P-ROM data can be read by the normal procedure.

The P-ROM data can be analyzed by releasing the protect mode by the series of operations described above.

[0035]

As described above, the P according to the present invention
-In a microcomputer with built-in ROM, P-select is selectively performed by the protect data stored in a specific memory cell.
The ROM verify function can be prohibited, and the protection can be released by the additional write means to the specific bit of the specific memory cell. Therefore,
The program data stored in the P-ROM can be protected, the confidentiality of the software can be maintained for a third party, and at the same time, the P-ROM data can be analyzed when the microcomputer itself fails. Can be facilitated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a specific configuration example of a P-ROM and its peripheral circuits in a P-ROM built-in microcomputer according to the present invention.

FIG. 2 is a block diagram of a protection control circuit of FIG.

FIG. 3 is a timing chart showing an operation during programming of the P-ROM built-in microcomputer shown in FIG.

FIG. 4 is a timing chart showing an operation at the time of verification of the P-ROM built-in microcomputer shown in FIG.

5 is a diagram showing a logic circuit of the protect data decoder of FIG. 1. FIG.

FIG. 6 is a block diagram showing a specific configuration example of a P-ROM and its peripheral circuits in a conventional microcomputer with a built-in P-ROM.

FIG. 7 shows a P- having a conventional P-ROM protect function.
FIG. 11 is a block diagram showing another specific configuration example of the P-ROM of the microcomputer with a built-in ROM and its peripheral circuits.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P-ROM 2 Protect information memory cell 3 Address decoder 4 Address modification circuit 5 Program counter 6 Instruction decoder 7 P-ROM mode decoder 8 P-ROM mode setting port 9 Program data input / output port 10 Bus switch 11 RS type flip-flop 34 1st RS type flip-flop circuit 35 2nd RS type flip-flop circuit 36 3rd RS type flip-flop circuit 12, 13, 24, 25, 26, 27, 28 AND
Circuit 14, 15, 16, 21, 22, 23 OR circuit 17 Read circuit 18 Write circuit 19 Protect control circuit 20 Protect data decoder 29, 30 NOR circuit 31, 32, 33 INV circuit 37, 38, 39 Third delay circuit 40 gate circuit

Claims (3)

[Claims] 1. A protect information memory cell composed of a plurality of P-ROM cells and data of the protect information memory cell are input to a P-ROM built-in microcomputer having a P-ROM verify prohibition protect mode. A P-ROM built-in microcomputer having a protected data decoder for performing decoding and an address modification circuit for modifying the address information of the P-ROM by an output signal of the protected data decoder. 2. The microcomputer with a built-in P-ROM according to claim 1, wherein the protect data decoder excludes two different data combinations and outputs an active signal only when data other than the data combinations is input,
A microcomputer with a built-in P-ROM, characterized in that a protect mode for prohibiting verification of the P-ROM is set. 3. The microcomputer with built-in P-ROM according to claim 1, wherein the protect mode is P-
It is characterized in that it is valid only in the verify mode for confirming the continuous reading of the address data of the ROM.
Microcomputer with built-in P-ROM.