JPH06350072A - Photoelectric converter - Google Patents

Abstract

PURPOSE:To enable high-speed readout for a row of photoelectric converting elements for an image sensor. CONSTITUTION:A photodiode 12 is formed between the source region of an FET 14 and an Si substrate. The base region of a bipolar transistor 13 using the Si substrate as a collector is connected to the drain region of the FET 14. A bias power source 15 for making the FET 14 operate in a saturated condition is connected to the gate electrode. And a photoelectrically converted signal is taken out from the emitter electrode of a BPT 13. Accordingly, it becomes possible to shorten recharging time to the BPT 13 and perform high- speed reading without producing an after image, since the junction capacitance of the photoelectric converting part is divided into two, Cd and Cbc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device suitable for a photoelectric conversion element array of an image sensor and capable of high-speed reading.

[0002]

2. Description of the Related Art CC is used in fields such as image processing and image communication.
D image sensors and MOS image sensors are used. Such an image sensor is a solid-state imaging device made of a silicon (Si) single crystal substrate as a material, and has a configuration in which optical signal charges are accumulated in each pixel arranged in a mosaic pattern and changes in the amount of the charges are sequentially read out. ing.

The CCD image sensor has a structure in which optical signal charges photoelectrically converted and accumulated by a photoelectric conversion element array composed of photodiodes are sequentially transferred by a charge coupled device (CCD). The MOS image sensor is a self-scanning type in which a scanning shift register is arranged in parallel with a photoelectric conversion element array formed of a photodiode or a phototransistor.

FIG. 5A shows a plan view of a portion corresponding to one pixel of a phototransistor forming a photoelectric conversion element array.
5B, and its AA cross-sectional shape is shown in FIG. n
A base region 2 is formed by diffusion on a conductive Si substrate 1, and an emitter region 3 is formed by diffusion on the surface side of the base region 2. The base region 2 is wider than that of a normal bipolar transistor (BPT), and the photoelectric conversion portion is formed therein. Therefore, the junction capacitance between the base and the collector is larger than that of an ordinary transistor. The diffusion region 4 for the collector electrode is formed at the same time as the emitter region 3. 5 shows an oxide film.

As shown in the equivalent circuit of FIG. 6, the image sensor comprises a phototransistor 6, an access field effect transistor (FET) 7, a reset FET 8 and a scanning shift register 9. The phototransistor 6 has the structure shown in FIG.
For easy understanding, the photocurrent source Ip, the base-collector junction capacitance Cbc, and the transistor function portion 10 are shown separately.

When the photocurrent Ip generated by the light irradiation discharges the electric charge accumulated in the base-collector junction capacitance Cbc, an amount of electric charge equal to the lost electric charge is generated in the next accumulation period, that is, When FET7 turns on, it is recharged from an external power source. Since the amount of electric charge at this time is proportional to the amount of light irradiation, the FET 7 is turned on and off at regular time intervals to output the output line 11
The image signal can be taken out. FET for reset
Each time 8 is turned on, the emitter of phototransistor 6 is reset to ground potential.

[0007]

The image sensor described above operates with high sensitivity with a relatively simple circuit structure, but since the time constant for recharging the phototransistor 6 is large, high-speed reading is possible. There was a problem of difficulty. That is, of the amount of electric charge stored in the base-collector junction capacitance Cbc of the phototransistor 6, the reduced amount discharged by the photocurrent Ip is detected by recharging the phototransistor 6, and the amplified photoelectric conversion signal is obtained. Although taken out from the emitter electrode, the base region of the phototransistor 6 is large as described above, and thus the junction capacitance Cbc between the base and collector is large. Further, since the base-emitter diode acts as a non-linear resistance in the charging circuit during recharging, the charging time constant becomes large. Since the charging time cannot be lengthened by high-speed scanning, if the base-collector junction capacitance Cbc is large, recharging becomes incomplete, especially in the low-exposure region, and afterimages are likely to occur, and thin lines of image information and pattern edge reading Function deteriorates.

Therefore, an object of the present invention is to provide a photoelectric conversion device which can be read at high speed without causing an afterimage.

[0009]

In order to achieve the above-mentioned object, the present invention has a source region and a drain region formed in a Si substrate having an oxide film, and a gate electrode provided on the oxide film. , An insulated gate field effect transistor forming a photodiode between the Si substrate and the source region, and the Si substrate as a collector,
The drain region comprises a bipolar transistor having a base region and an emitter region formed in the Si substrate, and a bias power source for applying a constant bias potential to its gate electrode for operating the field effect transistor in a saturated state. A photoelectric conversion device is provided which is electrically connected to the base region and takes out a photoelectric conversion signal from an emitter electrode provided in the emitter region.

[0010]

According to the present invention, since the equivalent circuit configuration shown in FIG. 1 is obtained, the junction capacitance of the photoelectric conversion portion is circuit-wise composed of the junction capacitance Cd of the photodiode and the junction capacitance Cbc between the base and collector of the bipolar transistor. To be separated. Cd>
Since Cbc can be used, the speed of recharging the bipolar transistor is increased, and high-speed reading is possible without causing an afterimage. Moreover, since the connection between the photodiode and the source region and the connection between the base region and the drain region are achieved in the Si substrate, the increase in the required area of the photoelectric conversion device can be minimized.

[0011]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an equivalent circuit diagram showing a photoelectric conversion device and its peripheral circuits. The photoelectric conversion device is a photodiode 12.
A bipolar transistor (BPT) 13, a p-channel type insulated gate field effect transistor (FET) 14 in which the source is connected to one end of the photodiode 12 and the drain is connected to the base of the BPT 13;
The bias power source 15 applies a bias potential to the gate electrode of the reference numeral 14. Photodiode 12
Are shown separately for the photocurrent source Ip and the junction capacitance Cd. 16 is a positive power supply, 7 is an access FET, and 11 is an output line.

The planar shape of the photoelectric conversion device is shown in FIG. 2 (a), and its sectional shape is shown in FIG. 2 (b). A p-conductivity type source region 18 and a drain region 19 of the FET 14 are formed in the n-conductivity type Si substrate 17 by diffusion. A gate electrode 21 is provided on the thin oxide film 20 on the Si substrate 17. A p-conductivity type base region 22 of the BPT 13 having the Si substrate 17 as a collector;
An n-conductivity type emitter region 23 is formed in the Si substrate 17 by diffusion.

The source region 18 forms a photodiode 12 with the Si substrate 17, and the photodiode 12 acts as a light receiving portion for generating a photocurrent Ip.
The p-conductivity type drain region 19 and the base region 22 of the BPT 13 partially overlap with each other and are electrically connected.

The source region 12 and the drain region 19 in the structure shown in FIG. 2 exist in a form that the base region 2 of the conventional structure shown in FIG. 5 is divided into two parts, and the gate electrode 21 is provided between the regions 12 and 19. Exists. The combined area of the drain region 19 and the base region 22 is made as small as possible than the area of the source region 18. Therefore, the base-collector junction capacitance Cbc of the BPT 13 is sufficiently smaller than the junction capacitance Cd of the photodiode 12.

The p-channel type FET 14 operates in a saturated state when a constant bias potential Vg is applied to the gate electrode 21, and the source potential, that is, the anode potential of the photodiode 12 is set to a constant value of about Vg + Vt. It Here, Vt is the absolute value of the threshold voltage of the FET 14. Therefore, the voltage between the terminals of the photodiode 12 is always fixed to a substantially constant value regardless of the magnitude of the exposure amount. Since the FET 14 operates in a saturated state, the signal current output from its drain serves as a current source that does not depend on the drain potential, that is, the base potential of the BPT 13, and is stored in the base-collector junction capacitance Cbc.

Anode of photodiode 12 and BPT
The FET 14 is inserted and connected between the base of the photodiode 13 and the junction capacitance Cd of the photodiode 12 and BPT1.
The base-collector junction capacitance Cbc of 3 is separated, and the capacitance required for recharging to obtain a signal output can be reduced. Therefore, when the area of the base region including the light receiving portion is 3000 μm, the base-collector junction capacitance Cbc in the conventional phototransistor is about 1.
While it was pF, the base-collector junction capacitance Cbc in the photoelectric conversion device according to the present invention can be about 0.2 pF.

When the base-emitter junction capacitance of the BPT 13 is Cbe, the afterimage rate is the capacitance C seen from the base terminal.
It increases with the increase of bc + Cbe. Since Cbc> Cbe in a general transistor, afterimage performance is improved by reducing Cbc.

FIG. 3 illustrates an output signal waveform when a stripe image in which light and dark are repeatedly arranged every four lines is read. Output signal A immediately after changing from light to dark
Is higher than the true dark level. Further, the output signal C immediately after changing from dark to bright is lower than the true bright level. Here, (A−B) / (D−B) is defined as a trailing afterimage, and (D−C) / (D−B) is defined as a trailing afterimage. Exposure amount 0.05 lx. s, charging time 0.
In the conventional phototransistor at 5 μs (2 MHz), the falling and rising afterimage ratios are about 10 and 10%, respectively.
% And 25%. On the other hand, the falling and rising afterimage ratios under the same conditions in the photoelectric conversion device of the present invention were about 5% and 11%, respectively. In particular, there was a great improvement in the afterimage rise rate.

FIG. 4 shows an equivalent circuit of a linear image sensor using the photoelectric conversion device of the present invention in a photoelectric conversion element array. In the figure, elements having the same functions as those shown in FIG. 1 are designated by the same reference numerals. Reference numeral 8 is a reset FET, 9 is a scanning shift register, ST and CK are signal input terminals for the start and shift clocks, and Ext is an output signal terminal for an expansion signal required to expand the number of pixels in a multi-chip configuration. . Parallel output terminals Y1 and Y2 of the scanning shift register 9
, ~ Yn, Yn + 1 are sequentially connected to the gate electrode of the access FET 7 and the gate electrode of the reset FET 8. Access FE attached to each photoelectric conversion device
When T7 turns on, the signal current from the photoelectric conversion device is taken out to the output line 11. When the reset FET 8 is turned on, the emitter of the photoelectric conversion device is reset.

The output signal of the shift register 9 sequentially operates from the photoelectric conversion element in the preceding stage to the photoelectric conversion element in the subsequent stage, whereby the image signal current is taken out from the output line 11 in time series. The BPT 13 is for amplifying the accumulated signal charge, and is required to have a small leakage current and a uniform current amplification factor between the elements. Therefore, the acceptor concentration of the base region 22 shown in FIG. 2 is set smaller than that of an ordinary transistor, and the base width is set large.

[0022]

As described above, according to the present invention, the recharging speed can be increased. Therefore, the present invention can be applied to an image sensor mounted in a facsimile, a scanner or the like to read image information at high speed without causing an afterimage. You can

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of a photoelectric conversion device according to an embodiment of the present invention.

FIG. 2 is an electrode configuration diagram of a photoelectric conversion device according to an embodiment of the present invention.

FIG. 3 is an output signal waveform diagram when a stripe image is read.

FIG. 4 is an equivalent circuit diagram of an image sensor using the photoelectric conversion device of the present invention.

FIG. 5 is an electrode configuration diagram of a conventional photoelectric conversion device.

FIG. 6 is an equivalent circuit diagram of a conventional image sensor.

[Explanation of symbols]

 12 Photodiode 13 Bipolar Transistor 14 Field Effect Transistor 15 Bias Power Supply 17 Si Substrate 18 Source Region 19 Drain Region 20 Oxide Film 21 Gate Electrode 22 Base Region 23 Emitter Region 24 Emitter Electrode

Claims (3)

[Claims] 1. An insulation having a source region and a drain region built into an Si substrate having an oxide film and a gate electrode provided on the oxide film, and forming a photodiode between the Si substrate and the source region. A gate type field effect transistor, a bipolar transistor having the Si substrate as a collector and having a base region and an emitter region formed in the Si substrate, and a constant gate electrode for operating the field effect transistor in a saturated state. And a bias power supply for applying a bias potential, the drain region is electrically connected to the base region, and a photoelectric conversion signal is taken out from an emitter electrode provided in the emitter region. 2. The photoelectric conversion device according to claim 1, wherein the combined area of the drain region and the base region is sufficiently smaller than the area of the source region. 3. The photoelectric conversion device according to claim 1, wherein the Si substrate has n conductivity type, the source region, the drain region and the base region have p conductivity type, and the emitter region has n conductivity type.