JPH06350053A - Memory cell of static ram - Google Patents

Abstract

PURPOSE:To improve reliability of a SRAM with the bit line width and the bit line interval secured sufficiently and to scale down a memory cell by varying a forming position of a gate contact. CONSTITUTION:A SRAM where first and second word lines 11, 12 are arranged almost in parallel within a memory cell 1 with first and second driver transistors 5, 6 interposed between them has gate contacts 15, 16 of the first and second driver transistors 5, 6 piled up via an insulating film (unillustrated) on the first and second word lines 11, 12 or the first and second word transistors 7, 8. A Vss contact 18 is arranged almost at the center of the memory cell 1, and with respect to the Vss contact 18, either or both of the first and second gate electrodes 13, 14 or the first and second word lines 11, 12 are arranged in point symmetry.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static RAM memory cell.

[0002]

2. Description of the Related Art In a static RAM (hereinafter referred to as SRAM) having a memory capacity of 256 kilobits or more and 4 megabits or less, two driver transistors are arranged on one side of one word line forming a word transistor. . However, in SRAMs having a memory capacity of 16 megabits or more, memory cells using a thin film transistor (TFT) as a load are mainstream, and a pattern suitable for this is required.

Therefore, a memory cell of a CMOS type static RAM (hereinafter referred to as SRAM) having a pattern structure as shown in FIG. 6 has been proposed. In the figure, as an example, one of the components of the memory cell 101 of the SRAM is
A word line 111 formed of a polycrystalline silicon film of a layer,
112 and the gate electrodes 115 and 116 of the driver transistors 113 and 114 are shown.

As shown in the figure, one memory cell 101
Inside, two word lines 111 and 112 are arranged in parallel. The gate electrodes 115 and 116 of the driver transistors 113 and 114 are provided between the two word lines 111 and 112, respectively.
1, 112 are arranged substantially parallel to each other.

The driver transistors 113 and 114
Vss contact 1 connected to the source region 117 between
18 is provided. A node contact 119 is provided between the gate electrode 115 of the one driver transistor 113 and the one word line 111, and between the gate electrode 116 of the other driver transistor 114 and the other word line 112. Node contact 12
0 is provided. In addition, the gate electrodes 115 and 116
Gate contacts 121 and 122 are provided above each of the above.

Further, the upper side of the word lines 111 and 112 and the gate electrodes 115 and 1 of the driver transistors.
A load element (not shown) is formed on the upper side of the 16 side. Then, each word line 111, 1
Bit contacts 123 and 124 are provided on the side opposite to the gate electrodes 115 and 116 side with respect to 12. Further, bit lines 125 and 126 (portions indicated by chain double-dashed lines) are arranged in a state of being connected to the bit contacts 123 and 124 and substantially at right angles to the word lines 111 and 112.

[0007]

However, in the memory cell of the SRAM having the above structure, the memory cell has a rectangular shape which is long in the vertical direction. The bit line is arranged in the longitudinal direction of the memory cell. Therefore, when attempting to arrange a bit line in a memory cell, the bit line width and the bit line interval must be narrowed to form the bit line.
Since this bit line is often formed of aluminum, stress migration or electromigration of the bit line reduces the reliability of the entire SRAM. In addition, the area of the memory cell is increased, which prevents the chip size from being reduced.

Further, since the word lines which should originally be driven in the same phase are formed by being divided into two, if the line width of the word lines is not formed uniformly due to manufacturing factors or the like, a signal line It causes a phase difference in transmission. Therefore, SR
It interferes with AM drive.

The present invention has been made to solve the above problems, and an object thereof is to provide a static RAM memory cell in which the area of the memory cell is reduced.

[0010]

SUMMARY OF THE INVENTION The present invention is an SRAM memory cell made to achieve the above object. That is, in a memory cell of a static RAM in which two word lines are arranged in parallel in the memory cell and a driver transistor is arranged between the word lines, the gate contact of the gate electrode of each driver transistor is formed. The insulating film is laminated on the word line or on the word transistor formed by the word line.

In the SRAM memory cell having the above-described structure, the Vss contact in the source region of the driver transistor is arranged substantially at the center of the memory cell, and the gate electrode of the driver transistor or the word line is connected to the Vss contact. , At least one or both of which are arranged in point symmetry.

Further, each word line is connected at least in a memory cell array region including a plurality of the memory cells. Alternatively, each word line is connected to both ends or one side of the memory cell.

Further, in the SRAM memory cell having the above structure, a power supply line is arranged in the central portion of the memory cell so as to cross each word line, and the upper side of each word line and the upper side of the gate electrode of the driver transistor are arranged. The load element is formed in a laminated state.

[0014]

In the memory cell of the SRAM described above, two word lines are arranged substantially in parallel within the memory cell, a driver transistor is arranged between the word lines, and the gate contact of the gate electrode of each driver transistor is arranged. By stacking on the word line or on the word transistor formed by the word line, the memory cell area is reduced. Further, since the memory cells are formed horizontally long, the bit line intervals can be sufficiently secured.

Further, the Vss contact of the source region of the driver transistor is arranged at substantially the center of the memory cell, and at least one or both of the gate electrode of the driver transistor and the word line is point-symmetrical with respect to the Vss contact. By arranging the memory cell in the memory cell, the design of the memory cell becomes easy.

Further, each word line is connected at least in a memory cell array region including a plurality of the memory cells, or each word line is connected at both ends or one side of the memory cell. , The signals transmitted by the word lines are transmitted in the same phase.

Further, a power supply line is provided in the central portion of the memory cell so as to cross each word line, and load elements are laminated on both sides of the power supply line above the word line and above the gate electrode of the driver transistor. By forming the memory cell in the state, high integration of the memory cell can be achieved.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the layout diagram of FIG. In the figure, a memory cell 1 of a so-called split word line type static RAM (hereinafter referred to as SRAM) is shown. It should be noted that the illustration of the load elements of the SRAM and various insulating films (for example, insulating films for element isolation, gate insulating films, etc.) are omitted in the figure.

That is, as shown in FIG. 1, an element isolation region 4 is formed on a substrate 2 in the memory cell 1 so as to surround a side portion of a substantially S-shaped active region 3 (a region shown by a dashed diagonal line). Has been done.

The two first and second word lines 11 and 12 are arranged so as to cross the active region 3 in the left-right direction in the drawing.
(Hatched areas) are arranged substantially in parallel. Between the first and second word lines 11 and 12, there are provided first and second driver transistors 5 and 6 using the active region 3 as source and drain regions. First, above
The first and second gate electrodes 13 and 14 of the second driver transistors 5 and 6 are substantially parallel to each other with respect to the first and second word lines 11 and 12, for example, at an angle of about 45 °. It is provided in the state.

The first gate contact 15 of the first gate electrode 13 is provided in a state of being laminated on the first word line 11. Alternatively, the first word line 11
It may also be provided on the first word transistor 7 formed in. The second gate contact 16 of the second gate electrode 14 is provided in a state of being stacked on the second word line 12. Alternatively, it may be provided on the second word transistor 8 formed by the second word line 12.

Further, the first and second gate electrodes 13,
Between 14 are the first and second driver transistors 5, 6
A source region 17 composed of the active region 3 is provided. A Vss contact 18 is provided on the source region 17.

The Vss contact 18 is arranged substantially in the center of the memory cell 1, and the first and second gate electrodes 13 of the first and second driver transistors 5 and 6 are provided.
14 and the first and second word lines 11 and 12 are preferably provided point-symmetrically with respect to the Vss contact 18.
In this way, by arranging the first and second word lines 11 and 12 and the first and second gate electrodes 13 and 14 in point symmetry, the design of the memory cell 1 is simplified and facilitated.

Further, the Vss contact 1 is connected to the first gate electrode 13 between the first and second word lines 11 and 12.
The first drain region 19 of the first driver transistor 5 is provided on the side opposite to the side 8. The first drain region 19 is composed of the active region 3 and also serves as the active region of the first word transistor 7. Further, a first node contact 20 connected to the first drain region 19 is provided on the first drain region 19. Similarly, the second drain region 21 of the second driver transistor 6 is provided between the first and second word lines 11 and 12 on the side opposite to the Vss contact 18 with respect to the second gate electrode 14. ing. This second drain region 21
Consists of the active region 3 and also serves as the active region of the second word transistor 8. A second node contact 22 connected to the second drain region 21 is provided on the second drain region 21.

On the active region 3 on the opposite side of the first and second driver transistors 5 and 6 with respect to the first and second word lines 11 and 12, the first connection is made. , Second bit contacts 23, 24 are provided.

In the structure of the memory cell 1 described with reference to FIG. 1 above, the two first and second word lines 11,
12 is provided, and the first and second driver transistors 5 and 6 are provided between them, and the first and second gate electrodes 13 and 14 of the first and second driver transistors 5 and 6 are provided.
The gate contacts 15 and 16 are connected to the first and second word lines 1
1, 12 or the first and second word transistors 7,
By providing the first and second gate contacts 15 and 16 in a stacked state, at least the area of the memory cell 1 is reduced by the area where the first and second gate contacts 15 and 16 are stacked. For example, the memory cell area is reduced by about 10%.

Further, as shown in FIG. 2, the first and second
The first and second bit lines 25 and 26 are arranged in a state of being connected to the bit contacts 23 and 24 and substantially at right angles to the first and second word lines 11 and 12, respectively.

In the structure of the memory cell 1 described with reference to FIG. 1, as shown in FIG. 3, the first and second word lines 11 and 12 (hatched regions) are the memory cell 1 concerned.
A plurality of memory cells may be connected at least at one place in the memory cell array region 51 by the connecting portion 41. The connecting portion 41 is usually formed integrally with the first and second word lines 11 and 12.

Alternatively, as shown in FIG. 4, the first and second
The word lines 11 and 12 (hatched areas) may be connected by the connection portions 41 formed on both ends of the memory cell 1. This connecting portion 42 is usually the first and second word lines 1
1 and 12 are formed integrally. Alternatively, the connecting portion 42 may be formed only on one side of the memory cell 1.

As described above, each of the first and second word lines 1
In the case where 1 and 12 are connected, the signals transmitted by the first and second word lines 11 and 12 are transmitted in the same phase.

Next, the layout of the load element formed in the SRAM memory cell 1 will be described with reference to the layout diagram of FIG. In the figure, a thin film transistor (TF
An example using T) is shown. Various insulating films (for example, insulating films for element isolation, gate insulating films, etc.) are not shown.

As shown in the figure, the first and second TFTs 9 and 10 serving as load elements are substantially parallel to the first and second word lines 11 and 12 (regions indicated by alternate long and short dash lines), respectively.
The first and second TFT gate electrodes 31 and 32 (hatched areas) are formed so as to be laminated on a part of the first and second word lines 11 and 12. One side of the first TFT gate electrode 31 is connected to the second gate contact 16, and the other side is connected to the first node contact 20. One side of the second TFT gate electrode 32 is connected to the first gate contact 15, and the other side is the second
It is connected to the node contact 22. Although not shown, a gate insulating film is formed on the surface of each of the first and second TFT gate electrodes 31 and 32.

Further, in the central portion of the memory cell 1, a power supply line 3 having an opening 34 formed on the Vss contact 18 so as to cross the first and second TFT gate electrodes 31 and 32.
3 is formed. On both sides of this power supply line 33, approximately L
The V-shaped first and second channel regions 35 and 36 are formed above the first and second TFT gate electrodes 31 and 32 via a gate insulating film (not shown). This first
The second channel regions 35 and 36 have the above-mentioned second and second regions, respectively.
It is connected to the first node contacts 22 and 20.

Further, each of the first and second channel regions 35, 3
6, first and second active regions 37 and 38 connected to each are formed. The power supply line 33 is
It also serves as the other active region of the first and second TFTs 9 and 10. The first and second active regions 37 and 38 are connected to the first and second gate contacts 15 and 16. Usually, the power supply line 33 and the first and second channel regions 3
5, 36 and the first and second active regions 37, 38 are formed of an integrated film (for example, polysilicon), and the power line 33 and the first and second channel regions 35, 36 have the first and second regions.
It is formed by introducing impurities into the second active regions 37 and 38 at a higher concentration.

As shown, the TFTs 9 and 10 are
It is preferable that the Vss contact 18 is provided point-symmetrically. By arranging the TFTs 9 and 10 in point symmetry, the design of the memory cell 1 is simplified and facilitated.

As described above, the first and second gate electrodes (on the first and second word lines 11 and 12 and on the first and second driver transistors (5) and (6) (see FIG. 1). 13), (14) [see FIG. 1] and the first and second T
By forming the FTs 9 and 10 in a stacked state, the memory cell 1 can be highly integrated.

[0037]

As described above, according to the present invention,
A driver transistor is arranged between two word lines arranged substantially parallel to each other in the memory cell, and the gate contact of each driver transistor is laminated above the word line or above the word transistor formed by the word line. Since it is arranged in such a state that the memory cells can be formed in a horizontally long shape. Therefore, the bit lines can be arranged with sufficient line width and spacing, so that the bit lines will not be damaged by stress migration or electromigration of the aluminum wiring forming the bit lines. Therefore, the reliability of the entire SRAM can be improved. Further, since the gate contacts are arranged in a stacked state, the memory cell area can be reduced. Therefore, the chip size can be reduced.

Further, in the case where at least one or both of the gate electrode of the driver transistor and the word line are arranged point-symmetrically with respect to the Vss contact arranged in the substantially central portion of the memory cell, the memory cell is designed. Since it can be simplified, the design becomes easy and the design time can be shortened. In addition, since the electric characteristics of the components arranged in point symmetry are almost the same in the memory cell, the symmetry of the electric characteristics of the memory cell is improved. The retention characteristic of stored data against data destruction can be improved.

In a memory cell array region having a plurality of the memory cells, at least two word lines are connected, or two word lines are connected at both ends or one side of the memory cells. The signals to be transmitted are transmitted in the same phase. Therefore, the signal can be transmitted accurately, and the reliability of the SRAM can be improved.

A state in which a power supply line is provided in a central portion of the memory cell so as to cross each word line, and load elements are stacked on both sides of the power supply line above the word line and above the gate electrode of the driver transistor. In the one formed in S,
High integration of the RAM can be achieved.

[Brief description of drawings]

FIG. 1 is a layout diagram of an example.

FIG. 2 is a layout diagram of bit lines.

FIG. 3 is a layout diagram of word lines.

FIG. 4 is another layout diagram of word lines.

FIG. 5 is a layout diagram of a load element.

FIG. 6 is a layout diagram of a conventional example.

[Explanation of symbols]

 1 Memory Cell 5 First Driver Transistor 6 Second Driver Transistor 7 First Word Transistor 8 Second Word Transistor 9 First TFT 10 Second TFT 11 First Word Line 12 Second Word Line 13 First Gate Electrode 14 Second Gate Electrode 15 First gate contact 16 Second gate contact 17 Source region 18 Vss contact 33 Power line

Claims (5)

[Claims] 1. A static RAM memory cell in which two word lines are arranged substantially parallel to each other in a memory cell and a driver transistor is arranged between the word lines, wherein a gate electrode of each driver transistor is provided. A memory cell of a static RAM, wherein the gate contact is laminated on the word line or a word transistor formed by the word line via an insulating film. 2. The memory cell of the static RAM according to claim 1, wherein the Vss contact on the source region of the driver transistor is arranged substantially in the center of the memory cell, and the Vss contact is provided.
A memory cell of a static RAM, wherein at least one or both of the gate electrode of the driver transistor and the word line are arranged point-symmetrically with respect to the contact. 3. The memory cell of the static RAM according to claim 1, wherein each word line is connected at least in a memory cell array region including a plurality of the memory cells. And a static RAM memory cell. 4. The memory cell of the static RAM according to claim 1, wherein the word lines are connected at both ends or one side of the memory cell. Characteristic static RA
M memory cells. 5. The static RAM memory cell according to claim 1, wherein a power supply line is provided in a central portion of the memory cell so as to cross the word lines. A memory cell of a static RAM, characterized in that a load element is formed on both sides of the power supply line above the word line and above the gate electrode of the driver transistor.