JPH06349398A - Excess current tripping circuit for circuit breaker - Google Patents

Abstract

PURPOSE:To activate a second constant circuit of capacity and resistance to carry out excess current tripping well, even when an excess current signal is intermittent and charging/discharging is carried out frequently by resetting a first constant circuit by means of the capacity and the resistance of an integrating circuit to an initial value when the excess current signal or power source voltage is zero. CONSTITUTION:When an excess current signal or power source voltage becomes zero, a first constant circuit 2 by means of the C1R1 of a integrating circuit 1 is reset to an initial value by a reset circuit 3. Only a time-limit output voltage due to excess current is output by the circuit 1 to an adding circuit 4. The voltage, for which the time-limit output voltage of the circuit 1 is added to the difference between the time- limit output voltage of a second constant circuit 8 and the time-limit output voltage of the circuit 1, by means of C2R2, is output by the adding circuit 4, and an excess current signal input by the degree of charging of a capacitor C2 of the second constant circuit 8 by means of the C2R2 is not reduced. The linear property of charging voltage is not ruined. A correct excess current signal is output according to excess current by separating the circuit 2 from the circuit 8, and excess current tripping of a circuit breaker is thus carried out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an overcurrent trip circuit for a circuit breaker, which trips by detecting an overcurrent in a power line.

[0002]

2. Description of the Related Art Conventionally, an overcurrent trip circuit of a circuit breaker for detecting an overcurrent of a power supply line and performing a trip operation to protect a covered electric wire and a load has a current transformer as shown in FIG. The current of the power supply line 21 detected by 20 is converted into AC-DC by the signal conversion circuit 22, the overcurrent is determined by the overcurrent determination circuit 23, and the overcurrent signal Ein is input to the constant voltage circuit 24. The constant voltage circuit 24 outputs a voltage in response to the overcurrent signal, and the current obtained by dividing the voltage by the resistor Ra is charged in the capacitor C _0.
The voltage across both ends of ₀ gradually rises with time T as shown in FIG. 4, and when the charging voltage Ec exceeds the reference voltage Es, the comparator 25 outputs a trip signal to the trigger circuit.

However, when the charging voltage Ec rises due to the charging action of the capacitor C ₀ , the potential across the resistor Ra decreases, the charging current decreases, and the rate of increase of the charging voltage Ec decreases. Therefore, there is a problem that a delay occurs in the time limit for reaching the reference voltage Es. Especially overcurrent signal E
When in is intermittently input, it is necessary to charge the capacitor C ₀ as shown by the broken line in FIG. 5, but due to the intermittent input, the difference between the charging voltage Ec and the value of the overcurrent signal Ein is minute. However, there is a problem in that charging is not performed promptly according to the overcurrent value, the timing of issuing a trip signal is significantly delayed, and the device does not operate within a predetermined time. This causes a problem that the wiring is not completely protected because the timed operation is not reliably performed when the overcurrent in the power supply line occurs intermittently or discontinuously. These are one C ₀ R ₀
Since the time constant operation is performed by the constant circuit, it is difficult to set constants corresponding to continuous input and intermittent input of the overcurrent signal.

[0004]

SUMMARY OF THE INVENTION The present invention solves the above problems and provides an overcurrent trip circuit for a circuit breaker that performs charging according to an overcurrent value and performs an accurate trip operation. is there.

[0005]

According to the present invention, there is provided an integrating circuit having a first constant circuit by C ₁ R ₁ for integrating an overcurrent signal and an integrating circuit when a power supply voltage is zero or an overcurrent signal is zero. A reset circuit that resets the timed output voltage to an initial value and a difference between the timed output voltage of the second constant circuit and the timed output voltage of the integration circuit by C ₂ R ₂ connected to the comparator that outputs the trip signal are output. A differential circuit,
It comprises a peak hold circuit for outputting the peak voltage of the output of the differential circuit, and an adder circuit for adding the peak voltage of the peak hold circuit and the timed output voltage of the integrating circuit.

[0006]

The overcurrent trip circuit of the circuit breaker of the present invention is
When the overcurrent signal is input to the integrating circuit having the first constant circuit of C ₁ R ₁ , the integrating circuit outputs the timed output voltage according to the overcurrent. The addition circuit connected to the integration circuit outputs the difference between the timed output voltage of the integration circuit and the timed output voltage of the second constant circuit by C ₂ R ₂ connected to the comparator to the output voltage of the differential circuit. Peak voltage is input via a peak hold circuit, and the timed output voltage and peak voltage are added by an adder circuit. The output voltage of the adder circuit is input to the second constant circuit of C ₂ R ₂ ,
The difference between the timed output voltage of the second constant circuit and the timed output voltage of the integration circuit due to C ₂ R ₂ is fed back to the adding circuit via the differential circuit again.

Therefore, when the power supply voltage and the overcurrent signal are zero,
Timed output by the reset circuit connected to the integration circuit
The voltage is reset to the initial value of zero. At this time C₂R
₂It is the time when the overcurrent signal is zero even in the second constant circuit by
Resistance R₂Is discharged through and the overcurrent signal flows again
If the branch circuit outputs a timed output voltage, C₂R₂By first
2 constant circuit capacitor C₂Is charged from the middle of discharging
Be done. And the C₂R ₂Timed out the second constant circuit by
The difference between the input voltage and the time output voltage of the integration circuit is
Output by the peak hold circuit.
Output as a peak voltage and an adder circuit with the overcurrent signal
Entered in. And the added output voltage of the adder circuit
Than C₂R₂By the capacitor C of the second constant circuit₂To
Current flows according to the charge amount, and the current for the overcurrent signal is charged.
Be charged. And C₂R₂Time limit of the second constant circuit by
The comparator trips when the output voltage exceeds the reference voltage
It will output a signal.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the illustrated embodiments. Reference numeral 1 is an integrator circuit having a first constant circuit 2 of C ₁ R ₁ to which an overcurrent signal of the power supply line detected by the current transformer is input, and the integrator circuit 1 is a _first constant circuit of C ₁ R ₁ .
The timed output voltage is output based on the voltage charged in the capacitor C ₁ of the constant circuit 2. Reference numeral 3 is a reset circuit connected to the integration circuit 1. The reset circuit 3 is provided with C ₁ when the power supply voltage becomes zero or the overcurrent signal becomes zero.
Short the capacitor C ₁ of the first constant circuit 2 by R ₁ to reset the charged voltage to an initial value of zero to.

Reference numeral 4 is an adder circuit connected to the integrating circuit 1.
The adder circuit 4 adds the timed output voltage Ea of the integrating circuit 1 and the peak voltage Eb of the peak hold circuit 6 described later. Reference numeral 5 denotes a differential circuit connected to the buffer circuit 10 and the integrating circuit 1. The differential circuit 5 includes the buffer circuit 1
The timed output voltage Ed of the second constant circuit 8 and the timed output voltage Ea of the integration circuit 1 by C ₂ R ₂ are input via 0,
The difference between the timed output voltage Ed and the timed output voltage Ea is output. A peak hold circuit 6 outputs the peak potential of the output voltage of the differential circuit 5.

Reference numeral 7 is a constant current circuit, and the constant current circuit 7 is C ₁
A current corresponding to the amount of charge of the second constant circuit 2 by R _{1 is} caused to flow, and the second constant circuit 8 by C ₂ R ₂ is charged by the overcurrent signal. The second constant circuit 8 based on C ₂ R ₂ is connected to the comparator 9 that outputs a trip signal, and the constants of the capacitor C ₂ and the resistor R ₂ are set so as to approximate the heat dissipation characteristics of the covered electric wire. That is, the timed output voltage Ed is given to the comparator 9 and the buffer circuit 10.

With such a configuration, when the overcurrent signal detected by the power supply line is input to the integrating circuit 1, the integrating circuit 1 outputs Ea =-(1 / C ₁ R ₁ ) ∫Ein · dt. = - output _{(Ein / C 1 R 1)} T. At this time, the second constant circuit 8 by C ₂ R ₂
When the capacitor C ₂ is zero, the output voltage Ed of the timed output voltage Ea and a constant current circuit 7 of the integration circuit 1 are equal, the differential circuit 5 Ee = Ea-Ed, in Ee = 0 becomes, Ea =
It operates as Ed, and Ee = 0. Therefore, the peak hold circuit 6 has Eb = 0 when the input voltage Ee is zero, and the output voltage of the adder circuit 4 is Ec = Ea + Eb.
Ea + 0 = Ec, the constant current circuit 7 linearly charges the capacitor C ₂ of the second constant circuit 8 by C ₂ R _2, and when the voltage Ed becomes larger than the reference voltage, the comparator 9 outputs a trip signal. Is. Further, when the power supply voltage is zero, the capacitor C ₁ of the first constant circuit 2 by C ₁ R ₁ of the integrating circuit ₁ is short-circuited and discharged by the reset circuit 3 and reset to the initial value. In this case the capacitor C ₂ of C ₂ R ₂ by the second constant circuit 8 is gradually discharged by the resistor R _2.

Further, when the power supply voltage is on and the overcurrent signal is zero, the first constant circuit 2 by C ₁ R ₁ of the integrating circuit 1
The capacitor C ₁ and the capacitor Cp of the peak hold circuit 6 are short-circuited and discharged by the reset circuit 3,
It is reset to the initial value. At this time, the _second by C ₂ R 2
The constant circuit 8 is gradually discharged by the resistor R ₂ . Then, when the overcurrent signal is turned on, the capacitor C ₁ of the first constant circuit 2 by C ₁ R ₁ of the integrating circuit 1 starts from zero potential, and therefore the second constant circuit 8 by C ₂ R ₂ at the initial operation. Since only the potential of is added to the differential circuit 5,
Ed≈Ee, and the peak hold circuit 6 outputs the output voltage E.
Since the peak voltage of d is held and output to the adder circuit 4, Ec = Ea + Eb is output in the adder circuit 4, the constant current circuit 7 outputs Ec≈Ed, and the _second by C ₂ R ₂ is output.
The capacitor C ₂ of the constant circuit 8 is charged with the output voltage Ed. In this way, when the voltage Ed input to the comparator 9 exceeds the reference voltage, the comparator 9 outputs a trip signal. The time-limit circuit configured in this way performs only the charging operation by the first constant circuit 2 by C ₁ R ₁ when there is an overcurrent signal, and the second constant circuit 8 by C ₂ R ₂ when there is no overcurrent signal. Only performs the discharging operation and separately performs the charging / discharging operation.

[0013]

As is apparent from the above description, the present invention allows the first constant circuit by C ₁ R ₁ of the integrating circuit to be initialized to the initial value by the reset circuit when the overcurrent signal or the power supply voltage becomes zero. Since the resetting is performed, the integrating circuit outputs only the timed output voltage due to the overcurrent to the adding circuit, and the adding circuit outputs the timed output voltage of the second constant circuit and the timed output voltage of the integrating circuit by C ₂ R ₂ . outputs the output voltage timed output voltage is added to the integration circuit to the difference between, C ₂
The overcurrent signal input by the charging amount of the capacitor C ₂ of the second constant circuit by R ₂ does not decrease. Therefore, the linearity of the charging voltage is not impaired as in FIG. Further, by separating the first constant circuit by C ₁ R ₁ and the second constant circuit by C ₂ R _2, it is possible to output an accurate overcurrent signal according to the overcurrent.
The constant of the first constant circuit can be set by ₁ R ₁ , and the second constant by C ₂ R ₂ can be set according to the heat radiation characteristics of the covered electric wire.
The constant of the constant circuit can be set, and even if the overcurrent signal is intermittent and charging / discharging is frequently performed, the overcurrent signal is reliably charged to the second constant circuit by C ₂ R ₂ and the timed output is performed. Since the voltage can be output accurately, the device can operate normally within a predetermined time. Therefore, the present invention is extremely beneficial to the industry as an overcurrent trip circuit for a circuit breaker that solves the conventional problems.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is an output in each circuit of the present invention.

FIG. 3 is a conventional overcurrent trip circuit.

FIG. 4 is an output voltage waveform diagram of a C ₀ R ₀ constant circuit to which an overcurrent is continuously input.

FIG. 5 is a waveform diagram of intermittently input overcurrent signal and C ₀ R
It is an output voltage waveform diagram of a ₀ constant circuit.

[Explanation of symbols]

1 Integrator circuit 2 _First constant circuit by C ₁ R ₁ 3 Reset circuit 4 Adder circuit 5 Differential circuit 6 Peak hold circuit 8 Second constant circuit by C ₂ R ₂ 9 Comparator

Claims (1)

[Claims] 1. An integrator circuit (1) having a first constant circuit (2) of C ₁ R ₁ for integrating an overcurrent signal, and an integrator circuit (1) when the power supply voltage is zero or the overcurrent signal is zero. Reset circuit that resets the timed output voltage to the initial value (3)
And a differential that outputs the difference between the timed output voltage of the second constant circuit (8) and the timed output voltage of the integration circuit (1) by C ₂ R ₂ connected to the comparator (9) that outputs the trip signal. Circuit (5), peak hold circuit (6) that outputs the peak voltage of the output of the differential circuit (5), and peak hold circuit (6)
An overcurrent trip circuit for a circuit breaker, which comprises an adder circuit (4) for adding the peak voltage of 1 to the timed output voltage of the integrator circuit (1).