JPH06348558A - Data processor - Google Patents

Abstract

(57) [Summary] [Object] The present invention realizes efficient processing as a whole system by including threads identifiers in transmission contents in inter-processor communication and associating and linking threads between different processors. Build a data processing device that can. [Structure] A first processor 161 generates a thread in response to a processing request issued from a host device 10, issues a processing request to a third processor 162 together with an identifier of this thread, and receives this. The third processor generates a thread corresponding to the above processing request, analyzes the content of the processing request, and if the content includes input / output,
A data input / output request is issued to the first processor, and a thread in the processor to be processed is specified by adding the thread identifier acquired from the first processor to the request content.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device having an arithmetic processing device for executing arithmetic processing such as sorting or relational algebraic arithmetic on file data to be arithmetically operated in response to a request from a host device.

[0002]

2. Description of the Related Art Generally, a computer system is provided with a dedicated database arithmetic processing unit for performing sort processing, search processing of a relational database and the like at high speed.

This database arithmetic processing device is provided with an arithmetic circuit called a hardware sorter, and by using this arithmetic circuit, sorting and relational algebraic arithmetic etc. in response to arithmetic processing requests from the host device can be performed at high speed. Run.

This device is usually composed of a plurality of processors and functions are distributed. The processors are connected in common by an internal bus to form a tightly coupled multiprocessor system that shares a memory.

The memory is arranged on a common address space of a plurality of processors, and in order to efficiently perform its unique role, each processor is tightly coupled, and its operation is controlled by an independent monitor suitable for each. Is configured. For example, it is composed of three processors, and the third processor manages the whole, and requests processing by issuing commands to the first processor for input / output parts and to the second processor for sorting or relational algebraic operations. Then, each processor operates asynchronously. However, it is necessary to report the completion of processing to the third processor every time the first and second processors finish processing.

However, since the third processor realizes a multi-thread environment, it is impossible to know which thread has requested the processing. Also, for a large file, it is necessary to divide the input / output, but the first processor cannot associate the input / output requests divided into a plurality of times. We also need the previous information, and each time,
There was also a drawback that it involved processing equivalent to opening and closing.

[0007]

As described above, in the conventional case, when the database processing device is composed of a tightly coupled multiprocessor, the internal processing of another processor corresponding to the processing request issued from the host device is specified. Since it was not possible, it was necessary to retransmit all the information necessary for processing each time.

The present invention has been made in view of the above circumstances, and each processor constituting an apparatus is configured such that a transmission content in inter-processor communication includes a thread identifier and the threads between different processors are associated and linked. It is an object of the present invention to provide a data processing device that can realize efficient processing in the entire system and thereby realize efficient processing as a whole system.

[0009]

According to the present invention, there is provided a host device, a secondary storage device in which file data to be operated is stored, and a path for directly accessing the secondary storage device. A data processing device that executes a predetermined calculation process on file data to be processed in accordance with the above request, the calculation target according to the calculation request issued from the host device to the calculation processing device. Input means for obtaining file data from the secondary storage device via the path, operation processing means for executing a predetermined arithmetic logic operation on the input file data to be operated, and operation object. And an internal memory in which the calculation result data by the calculation processing means is stored, and the calculation result data are output to a secondary storage device. A first feature is that it is provided with an inputting means and a monitoring means for performing communication between the input / output means and the arithmetic processing means according to a request issued from the host device and operating the respective processing means in parallel. And

Further, the arithmetic processing unit constitutes a multiprocessor system composed of at least three processors, and performs communication with the host device and data input / output with the secondary storage device in a multithread environment. Input by the first processor, a second processor for performing execution control of arithmetic operations by this arithmetic circuit, a second arithmetic processor for performing predetermined arithmetic logic operation such as sorting or relational algebraic arithmetic, Based on an instruction from the host device supplied via the first processor and the internal memory in which the file data to be operated and the operation result by the operation circuit are stored.
To control the operation of multiple processors by multithreading
In the first to third inter-processor communications, the transmission contents include an identifier of a thread in the processor, and the threads are associated with each other to perform processing in association with each other. Is the second feature. At this time, the first processor generates a thread in response to the processing request issued from the host device, issues a processing request to the third processor together with the thread identifier, and receives the third processing request. The processor generates a thread corresponding to the processing request, analyzes the content of the processing request, and if the content includes input / output, issues a data input / output request to the first processor, In addition, the thread in the processor to be processed is specified by adding the identifier of the thread acquired from the first processor to the request content.

[0011]

According to the present invention, as described above, the multiprocessor configuration including at least the first to third processors is adopted for the arithmetic processing unit, and the data input / output between the database arithmetic processing unit and the secondary storage unit is the first. In the processor, the arithmetic processing using the arithmetic circuit is distributed to the second processor, and the overall control is distributed to the third processor, and the arithmetic processing from the host device is executed by the third processor. In the inter-processor communication, the content of the transmission includes the thread identifier in the processor, and the processing is efficiently performed in conjunction with each other. Specifically, the first processor creates a thread in response to a processing request issued from the host device, issues a processing request to the third processor together with the thread identifier, and receives this. The third processor generates a thread corresponding to the processing request, analyzes the content of the processing request, and when the content includes input / output, issues a data input / output request to the first processor. Then, the thread in the processor to be processed is specified by adding the identifier of the thread acquired from the first processor to the request content. This allows the CPU
1 to the thread in the first processor for the processing request of
It can correspond to one-to-one.

Thus, the load can be efficiently distributed by the first to third processors, and the third processor controls the parallel operation of the input / output by the first processor and the arithmetic processing by the second processor. However, the operation performance of the database arithmetic processing apparatus can be improved by associating and interlocking the threads in the first to third processors.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a data processing device according to an embodiment of the present invention.

The data processing apparatus shown in FIG. 1 comprises a host computer 10, a database operation processing apparatus (database engine; DBE) 16 and a magnetic disk device 17.

The host computer 10 includes a CPU 11,
Main memory device 12 and first and second channel devices 1
4, 15, etc. These CPU11,
The main memory device 12 and the channel devices 14 and 15 are interconnected via a system bus 13.

The host computer 10 and the database arithmetic processing unit 16 are connected by a channel unit 14, and the host computer 10 and the magnetic disk unit 17 are connected by a channel unit 15.

Further, the database arithmetic processing unit 16 and the magnetic disk 17 are connected via a dedicated access path 18. The CPU 11 is the host computer 10
It controls the entire system, and requests the database arithmetic processing unit 16 to execute various arithmetic processes such as sorting and relational algebraic arithmetic.

The main storage device 12 stores a command for instructing the database operation processing device 16 about an operation target file and operation contents. The database arithmetic processing unit 16 executes arithmetic processing on the data of the calculation target file based on the command from the CPU 11, and through the path 18 for input of the calculation target file and output of the calculation result. The magnetic disk device 17 is directly accessed.

The database processing unit 16 includes an engine interface processor (EIP) 161, an engine control processor (ECP) 162, and a large capacity memory (E).
BDM) 163, hardware sorter control processor (ECAM) 164, parallel sorting module (P
SOM) 165, a parallel relational algebra calculation module (PRAM) 166, and the like.

Engine interface processor 16
1, the engine control processor 162, and the hardware sorter control processor 164,
They are interconnected by internal buses 167,
A tightly coupled multiprocessor using the large capacity memory 163 as a shared memory is configured.

The large capacity memory 163 is arranged in a common address space of each of the three processors. In addition, these three processors, that is, the engine interface processor 161, the engine control processor 162,
The functions are distributed to the hardware sorter control processor 164. In this case, in order to efficiently perform their specific roles, each of these processors
While tightly coupled, the operation is controlled by an independent monitor suitable for each.

Engine interface processor 16
The functions of the engine control processor 162, the engine control processor 162, and the hardware sorter control processor 164 are distributed as follows.

That is, the engine interface processor 161 communicates between the host computer 10 and the database arithmetic processing unit 16, and is also connected to the disk controller of the magnetic disk unit 17 via the path 18. Control data input and output to and from.

Further, the engine interface processor 161 also carries out an output file reconstruction process when outputting data to the magnetic disk device 17. In communicating with the host computer 10, the engine interface processor 161 uses the C via the first channel device 14.
It receives the command sent from the PU 11 and sends it to the engine control processor 162.

The engine interface processor 161 also receives the status as a result of the command sent from the engine control processor 162 and sends it back to the CPU 11 via the first channel device 14.

In the data input / output with the magnetic disk device 17, the engine interface processor 161
Receives an input / output request from the engine control processor 162, and receives the large-capacity memory 163 and the magnetic disk device 17.
Data transfer between and. At that time, output file data reconstruction processing is also performed according to a request from the engine control processor 162.

The engine control processor 162 includes an engine interface processor 161, a large capacity memory 16
3 and the hardware sorter control processor 164 via an internal bus 167.
When the command from 1 is an operation processing command such as sorting or relational algebraic operation, various command processing processes corresponding to it are generated and executed.

The large-capacity memory 163 stores the file data to be calculated, CP, read from the magnetic disk device 17.
Various calculation processing commands sent from U11, calculation processing results by the hardware sorter control processor 164, parallel sorting module 165, and parallel relation algebra calculation module 166, and further integration results of calculation results by the engine control processor 162, etc. It is a shared memory for storing.

The file data to be calculated is stored in the input buffer section in the large capacity memory 163, and the calculation processing result is stored in the output buffer section in the large capacity memory 163.
The hardware sorter control processor 164 controls the calculation by the parallel sorting module 165 and the parallel relational algebra calculation module 166 based on the instruction from the engine control processor 162.

In this case, the hardware sorter control processor 164 inputs the data on the large capacity memory 163 to the parallel sorting module 165 and stores the calculation result output from the parallel relation algebraic calculation module 166 on the large capacity memory 163. However, when inputting data to the parallel sorting module 165, first, a key cutout process is executed.

In this key cut-out process, the hardware sorter control processor 164 cuts out only the key field of the operation target required for the operation from each record of the operation target, and the record identification number (the large capacity memory 16
3), and sends it to the parallel sorting module 165.

The parallel sorting module 165 is a dedicated hardware circuit that is driven under the control of the hardware sorter control processor 164 to execute sorting in parallel, and is connected to the parallel relation algebra operation module 166. This parallel sorting module 165
This is called a pipeline merge sorter, and is formed by cascade-connecting a plurality of sort cells that perform 2-way merge.

The parallel relational algebra operation module 166 uses JOIN and RESTI in the relational database.
It is a dedicated hardware circuit that executes relational algebraic operations such as CT (constraints) in parallel, inputs sorted data from the parallel sorting module 165, and outputs the operation results to the hardware sorter control processor 164. When only the sorting process is executed, the parallel relational algebra operation module 166 functions as the final sort cell.

As described above, the engine interface processor 161, the engine control processor 162, and the hardware sorter control processor 164 have functions for executing various arithmetic processes, such as sort process and select process, distributed therein. .

In this case, these processors operate asynchronously except for the exchange of buffers on the large capacity memory 163, and execute the respective functions in parallel. That is, processing such as sorting and selecting is usually composed of input processing, arithmetic processing, and output processing, but arithmetic processing under the control of the hardware sorter control processor 164 is input of arithmetic target data by the engine interface processor 161. It is executed in parallel with processing.

The calculation result from the hardware sorter control processor 164 is used as the engine control processor 162.
When it is necessary to perform the combining process by the combining process, the integration process and the output process by the engine interface processor 161 are also executed in parallel.

In these processes, interprocessor communication may occur due to synchronization in buffer exchange. In such a case, the identifier of the thread that is performing the processing is notified to the other party, and the threads are interlocked across a plurality of processors.

FIG. 2 is a flow chart showing the operation in the embodiment of the present invention. Specifically, the engine control processor 162 and the engine interface processor 16
The flow of communication with 1 is shown.

The operation of the apparatus according to the embodiment of the present invention shown in FIG. 1 will be described below with reference to FIG. Figure 2
The flowchart shown in FIG.
6 shows the flow from receiving a processing request from the CPU 11 to reporting the completion of processing.

First, the processing request issued to the database operation processing device 16 is received by the engine interface processor 161 inside the device (step 201 in FIG. 2).

Engine interface processor 161
Responds to this processing request, a thread is generated in the processor, and the processing request is sent to the engine control processor 162 together with the thread identifier (step 202 in FIG. 2).

The engine control processor 162 also creates a thread corresponding to this processing request, and analyzes the content of the processing request in this thread (step 203 in FIG. 2).

If the contents include input / output, a data input / output request is issued to the engine interface processor 161 (step 206 in FIG. 2).
At this time, the thread identifier obtained from the engine interface processor 161 is added to the request content to identify the thread in the processor that performs the process.

As a result, the threads in the engine interface processor 161 can be made to correspond one-to-one with the processing request of the CPU 11. Further, to the input / output request from the engine control processor 162 to the engine interface processor 161, the identifier of the thread making the request is added.

Therefore, when the data input / output processing is completed, the engine interface processor 161 designates the thread for reporting to the engine control processor 162 and reports the completion of input / output (FIG. 2).
Step 207).

When all the processing is completed by repeating the above processing (step 204 in FIG. 2), the engine control processor 162 specifies a thread to the engine interface processor 161 in the same manner as above and reports the completion of processing. Is performed (step 209 in FIG. 2).

By having the processing function according to the embodiment of the present invention, it becomes possible for the host device to interlock threads across a plurality of processors in the database arithmetic processing device, load of the host device, and database. The load on the arithmetic processing unit is reduced, and consistent processing can be performed in each processor incorporated in the processing unit, and efficient data processing can be realized as the entire system.

[0048]

As described above, according to the present invention, it becomes possible for the host device to link threads across a plurality of processors in the database operation processing device, the load of the host device and the database operation processing device. The load on the system is reduced, consistent processing can be performed in each processor incorporated in the device, and efficient data processing can be realized as the entire system.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an apparatus according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an operation processing procedure of the above embodiment.

[Explanation of Codes] 10 ... Host computer, 13 ... System bus, 14
... Channel, 16 ... B Database processing device (DB
E), 17 ... Magnetic disk device, 161, 162, 16
4 ... Processor, 163 ... Large-capacity memory, 165 ... Parallel sorting module, 166 ... Parallel relational algebra operation module.

Claims (3)

[Claims] 1. A host device, a secondary storage device for storing file data of an operation target, and a path for directly accessing the secondary storage device, the operation target according to a request from the host device. In the data processing device, the data processing device includes a processing device that executes a predetermined calculation process on the file data to be processed, and the processing device passes the file data to be processed according to a processing request issued from the host device. Input means obtained from the secondary storage device via the above, arithmetic processing means for executing a predetermined arithmetic logic operation on the inputted file data to be operated, file data to be operated and said arithmetic processing means An internal memory for storing the operation result data according to, an output means for outputting the operation result data to the secondary storage device, and the host The data processing apparatus characterized by according placed al Issued required performs communication between said input means and processing means, including a monitoring means for operating the respective processing unit in parallel. 2. A host device, a secondary storage device in which file data to be operated is stored, and a path for directly accessing the secondary storage device, and an operation target in response to a request from the host device. A data processing device for performing a predetermined data processing on the file data, the data processing device is configured to perform communication with a host device and data input / output with a secondary storage device. In a multi-thread environment, an arithmetic circuit for performing a predetermined arithmetic logic operation such as sorting or relational algebraic operation, a second processor for executing and controlling the arithmetic operation by the arithmetic circuit, and the first processor. Internal memory for storing the file data to be operated by the processor and the operation result by the operation circuit, and the first processor. A third processor that controls the operation of the first and second processors by multi-threads based on an instruction from the host device supplied via the server. A data processing device characterized in that a transmission content includes an identifier of a thread in a processor, and by associating threads between different processors, processing is interlocked and executed. 3. The first processor creates a thread in response to a processing request issued from the host device, issues a processing request to the third processor together with the thread identifier, and receives the processing request. The third processor generates a thread corresponding to the processing request, analyzes the content of the processing request, and when the content includes input / output, the first processor
Issuing a data input / output request to the processor and assigning the identifier of the thread previously acquired from the first processor to the request content to specify the thread in the processor to be processed. Item 2. The data processing device according to item 2.