JPH06176076A - Data processor - Google Patents

Abstract

PURPOSE:To perform a difference set operation at a high speed without applying any load to a host device by using effectively an operational processor which works in response to the requests given from the host device. CONSTITUTION:When a difference set operation command is given to an operational processor 16 from a CPU 11, an engine control processor 162 inputs a processing subject set to a large capacity memory 163 by an input processing request (a) given to an engine interface processor 161. Meanwhile the processor 162 sets the operation of a parallel relation algebra operational module 166 in the limit of a NOT EQUAL by a limit processing request (b) given to a hardware sorter control processor 164. Then the processor 162 makes the module 166 fetch the record a condition side set reported to the processor 164 through a parallel sorting module 165. Furthermore the record of a subject side set reported to the processor 164 is sent to the module 166 through the module 165 to carry out the limit based on the NOT EQUAL decision.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises an arithmetic processing unit for executing arithmetic processing such as sorting or relational algebraic arithmetic on file data to be arithmetically operated in response to a request from a host device, and particularly for difference set arithmetic. The present invention relates to a suitable data processing device.

[0002]

2. Description of the Related Art Generally, a computer system is provided with a dedicated database arithmetic processing unit for performing sort processing, relational database search processing, and the like at high speed. This database arithmetic processing device is provided with an arithmetic circuit called a hardware sorter, and by using this arithmetic circuit, sorting, relational algebraic arithmetic and the like according to arithmetic processing requests from the host device are executed at high speed.

However, conventionally, in this type of arithmetic processing unit, SQL (Structured Query Language) EX
No difference set operation equivalent to CEPT was provided. Therefore, the difference product set operation needs to be performed by the host device.

Here, what is important for efficiently performing the difference set operation is to reduce the number of record comparisons. For that purpose, it is necessary that sorting processing has already been performed in each set. However, this sort process itself is generally slow. As a result, much of the speedup obtained by the sort process is offset by the load of the sort process itself, and there is a problem that the load is heavy as a whole and the process is slow.

[0005]

As described above, conventionally, the arithmetic processing unit provided separately from the host device can perform the sort and the algebraic arithmetic operation requested by the host device. The difference set operation has to be performed by the host device, and there is a problem that the load on the host device is heavy and the processing is slow.

The present invention has been made in consideration of the above point, and by effectively utilizing an arithmetic processing unit that performs sorting, relational algebraic calculation, etc. in response to a request from the host unit, the load on the host unit is reduced. An object of the present invention is to provide a data processing device capable of performing a difference set operation at high speed without applying the above.

[0007]

According to the present invention, there is provided a host device, a secondary storage device for storing file data to be operated, and a path for directly accessing the secondary storage device. In the data processing device, the data processing device is configured to execute a predetermined operation process on the file data to be operated in response to a request from the data processing device. The data processing device includes first to third processors. 2)
The data input / output between the secondary storage devices is distributed to the first processor, the arithmetic processing using the arithmetic circuit is distributed to the second processor, and the overall control is distributed to the third processor. The arithmetic processing performed
The third processor controls the first processor when the host device requests a difference set operation for generating a difference set from the host device. While the target set is input, the third processor also controls the second processor to sort the input sets into the same circuit in sequence while sorting them by the arithmetic circuit, and in the same circuit, NOT EQUAL This is characterized in that the constraint processing by designation is performed.

[0008]

In the above structure, the first processor in the arithmetic processing unit is used.
Through the third processor, the load can be efficiently distributed, and moreover, the data input / output by the first processor and the arithmetic processing using the arithmetic circuit by the second processor can be performed in parallel. The execution control of the processor can reduce the load on the host device and can sufficiently improve the operation performance of the arithmetic processing device.

When a difference set operation is requested from the host device, the target set is input by the first processor under the control of the third processor, and the input set is input. Are sequentially input to the arithmetic circuit by the second processor under the control of the third processor, and the NOT EQUAL set by the second processor while being sorted by the dedicated hardware circuit of the arithmetic circuit. The constraint processing by the designation is performed by the hardware circuit dedicated to the relational algebraic operation of this arithmetic circuit. As described above, since the sorting function and the constraint processing function based on NOT EQUAL judgment of the arithmetic processing device are effectively used to perform the difference set operation in the arithmetic processing device, the host device is not burdened. It is possible to perform the difference set operation at high speed.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall system configuration of a data processing apparatus according to an embodiment of the present invention. This data processing device includes a host computer 10 and a database arithmetic processing device (database engine; DBE).
16 and an external storage device, for example, a magnetic disk device 17.

The host computer 10 includes a CPU 11,
Main memory 12, first and second channel devices 14,
It is composed of 15. The CPU 11, main storage device 12, and channel devices 14 and 15 are interconnected via a system bus 13.

The host computer 10 and the database processing unit 16 are connected by a channel unit 14,
The host computer 10 and the magnetic disk device 17 are connected by a channel device 15. Furthermore, the database arithmetic processing unit 16 and the magnetic disk unit 17 are connected via a dedicated access path 18.

The CPU 11 controls the host computer 10 as a whole, and requests the database arithmetic processing unit 16 to execute various arithmetic processes such as sorting and relational algebraic arithmetic. The main memory device 12 stores a command group for instructing the database operation processing device 16 about the operation target file and the operation contents.

Database processing unit (DBE) 16
Is for executing arithmetic processing on the data of the arithmetic target file based on a command from the CPU 11,
The magnetic disk device 17 is directly accessed via the path 18 in order to input the calculation target file and output the calculation result.

This database arithmetic processing unit (DBE)
16 is an engine interface processor (EIP)
161, engine control processor (ECP) 162, large capacity memory (EBDM) 163, hardware (HW)
It is composed of a sorter control processor (ECAM) 164, a parallel sorting module (PSOM) 165, and a parallel relational algebra operation module (PRAM) 166.

Engine Interface Processor (EI
P) 161, engine control processor (ECP) 16
2 and hardware sorter control processor (ECA
M) 164 of the three processors are interconnected by an internal bus 167, and a large capacity memory (EBDM) 1
A tightly coupled multiprocessor having 63 as a shared memory is configured. The large capacity memory (EBDM) 163 is arranged in a common address space of each of the three processors.

The functions are distributed among these three processors, that is, the engine interface processor (EIP) 161, the engine control processor (ECP) 162, and the hardware sorter control processor (ECAM) 164. In this case, in order to efficiently perform their specific roles, each of these processors
Although tightly coupled, the operation is controlled by an independent monitor (operating system for microprocessor) suitable for each.

Engine Interface Processor (EI
P) 161, engine control processor (ECP) 16
2 and hardware sorter control processor (ECA
The functional distribution of M) 164 is as follows.

First, the engine interface processor (EIP) 161 communicates between the host computer 10 and the database arithmetic processing unit 16 and is also connected to the disk controller of the magnetic disk unit 17 via a path 18 to It controls data input / output with the disk device 17. Further, the engine interface processor (EIP) 161 also performs reconfiguration processing of an output file when outputting data to the magnetic disk device 17.

In communication with the host computer 10, an engine interface processor (EIP) is used.
161 indicates the CPU 11 via the first channel device 14.
It receives the command sent from the and sends it to the engine control processor (ECP) 162. Further, the engine interface processor (EIP) 161 receives the status as a command result sent from the engine control processor (ECP) 162, and sends it back to the CPU 11 via the first channel device 14.

In inputting / outputting data from / to the magnetic disk device 17, an engine interface processor (E
IP) 161 is an engine control processor (ECP) 1
The I / O request from the 62 is accepted, and the large capacity memory (EB
Data is transferred between the DM) 163 and the magnetic disk device 17. At that time, the engine interface processor (EIP) 161 is connected to the engine control processor (EC
P) Reconstruction processing of output file data is also performed according to the request from 162.

Engine Control Processor (ECP) 162
Is an engine interface processor (EIP) 16
1, a large capacity memory (EBDM) 163, and a hardware sorter control processor (ECAM) 164 are controlled via an internal bus 167. When the command from the CPU 11 is a calculation processing command such as sort or relational algebraic calculation, the engine control processor (ECP) 162 manages generation and execution of various command processing processes corresponding to the command.

The large-capacity memory (EBDM) 163 is file data of an operation target read from the magnetic disk device 17, various operation processing commands sent from the CPU 11, and a hardware sorter control processor (ECAM).
164, parallel sorting module (PSOM) 16
5, and parallel relational algebraic operation module (PRAM) 1
It is a shared memory for storing the calculation result by 66, and further the integration result of the calculation result by the engine control processor (ECP) 162. The file data to be calculated is stored in the input buffer unit in the large capacity memory (EBDM) 163, and the calculation processing result is the large capacity memory (EBDM) 16
3 is stored in the output buffer unit.

Hardware sorter control processor (EC
AM) 164 is an engine control processor (ECP) 1
Based on the command from 62, the operations by the parallel sorting module (PSOM) 165 and the parallel relational algebraic operation module (PRAM) 166 are controlled.

In this case, the hardware sorter control processor (ECAM) 164 is a large capacity memory (EBDM).
Parallel sorting module (PS
The calculation result output from the parallel relational algebraic calculation module (PRAM) 166 is stored in the large capacity memory (EBDM) 163. When the data is input to the parallel sorting module (PSOM) 165, First, a key cutout process is executed. In this key cutout processing, the hardware sorter control processor (ECAM) 164 cuts out only the calculation target key field required for the calculation from each calculation target record, and adds the start address of the record in the large capacity memory (EBDM) 163 to it. A record identification number RID, which is (a pointer indicating), is added and sent to the parallel sorting module (PSOM) 165.

Parallel Sorting Module (PSOM)
165 is a hardware sorter control processor (ECA
M) is a dedicated hardware circuit that is driven by 164 and executes sorting in parallel, and is connected to a parallel relational algebraic operation module (PRAM) 166. The parallel sorting module (PSOM) 165 is called a pipeline merge sorter, and is formed by cascade-connecting a plurality of sort cells that perform 2-way merge.

Parallel Relational Algebra Operation Module (PRAM)
166 is JOIN (join) in the relational database
Is a dedicated hardware circuit that executes relational algebraic operations such as and RESTRICT (constraints, semi-joins) in parallel,
The sorted data is input from the parallel sorting module (PSOM) 165, and the calculation result is output to the hardware sorter control processor (ECAM) 164. When executing only the sorting process, the parallel relational algebraic operation module (PRAM) 166 functions as the final sort cell.

As described above, the engine interface processor (EIP) 161 and the engine control processor (E
The CP) 162 and the hardware sorter control processor (ECAM) 164 are distributed with functions for executing various arithmetic processes such as sort process and select process. In this case, these processors operate asynchronously except for the transfer of data in the buffer on the large capacity memory (EBDM) 163, and execute the respective functions in parallel. That is, processing such as sorting and selecting is usually composed of input processing, arithmetic processing, and output processing.
Hardware sorter control processor (ECAM) 164
The arithmetic processing under the control of is executed in parallel with the input processing of the arithmetic target data by the engine interface processor (EIP) 161. When the engine control processor (ECP) 162 needs to perform an integrated processing of the calculation result from the hardware sorter control processor (ECAM) 164, the integrated processing and the output processing by the engine interface processor (EIP) 161 are also performed in parallel. Is executed. Here, the difference set operation directly related to the present invention will be described with reference to the difference set operation example of FIG.

First, the difference set operation is from a set (called a target) of an element (record) to another set (called a condition).
It is an operation for obtaining a set consisting of elements (records) belonging to.

The example of FIG. 2 shows a case where the table 21 is the target and the table 25 is obtained by performing the difference set operation under the condition of the table 22. Tables 21 and 22 shown in FIG. 2 have four records 211 to 214 and 221-224, respectively.

In the difference set operation, objects and conditions are sorted. In the example of FIG. 2, as a result of performing the sorting process on each of the tables 21 and 22, the results are as shown in the tables 23 and 24 (here, in the order of the Japanese syllabary of the employee name). It is supposed to be sorted).

First, it is searched whether "Kawakami" of the first record 231 in the table 23 (target set) exists in the table 24 (conditional set). The search here is performed by sequentially comparing and determining the identity with the target record 231 from the first record in the table 24. Figure 2
In the example, since “Kawakami” of the record 231 exists in the record 241 of the table 24, that is, the record 231 matches the record 241 of the table 24, it is excluded and is not output.

Next, a search is made as to whether or not "Sato" of the record 232 in Table 23 exists in Table 24. At this time, the record 241 that matches the previous target record 231
Does not need to be compared, and the comparison with the subsequent record 242 is started. "Sato" exists in this record 242, but the affiliation and work location are different (because they are different persons with the same surname).
No record matches are seen. As described above, in checking the identity of records, it is general to compare not only a certain field (attribute) but the entire record.
However, if there is an attribute (for example, employee number) that can be used to determine the identity in the record, this is not the only case, and only the matching of the attribute (employee number) need be inspected.

Target record 232 and record 2 of table 24
42, the same target record 232 and record 24 (following record 242) are detected.
A comparison with 3 is made. This record 243 has "Suzuki", and has come after "Sato" in alphabetical order. Therefore, the subsequent record 24
The identity (matching) check with 4 is unnecessary, and the record 232 with the employee name “Sato” is not excluded and is output.

Next, it is checked whether "Tanaka" of the target record 233 in Table 23 exists in Table 24. As with the case of the record 232, the record 233 can be compared with the record 242. Here, the employee name in the final record of Table 24 is "Soma", which is in alphabetical order before "Tanaka". As a result, the target record 233 with the employee name “Tanaka” can be output. Further, for the records after that (here, the record 234 with the employee name “Nakamura”), see Table 24.
Since it can be seen that there is no match in Table 24 without performing comparison with the record of, the output can be made unconditionally. Therefore, the set (difference set) obtained as the processing result of the above difference set operation is as shown in Table 25 of FIG.

Next, the database operation processing device (D
BE) 16 engine control processor (ECP) 16
The difference set calculation process under the control of 2 will be described with reference to the flowchart of FIG.

First, in the present embodiment, when the host computer 10 (CPU 11 of the host computer) requires the difference set operation, the computer 10 (CPU 11 of the same) to the database arithmetic processing unit (DBE) 16 and the system bus 1
3. A command (difference set calculation command) requesting a difference set calculation is sent via the first channel device 14.

Host computer 10 (of CPU 11)
The difference set operation command sent from the database operation processing device (DBE) 16 from the engine is received by the engine interface processor (EIP) 161, and is passed to the engine control processor (ECP) 162.

Then, the engine control processor (EC
P) 162 first requests the engine interface processor (EIP) 161 for an input process as indicated by symbol a in FIG. 1, and executes the process designated by the difference set operation command from the host computer 10 (CPU 11 of the host computer 10). The target record set (target side set and condition side set) is input to the input buffer on the large capacity memory (EBDM) 163 from the magnetic disk device 17, for example (step S1). It should be noted that various kinds of arithmetic processing are continuously performed, and these sets are already stored in a large capacity memory (EBD).
M) 163, the input processing request a is unnecessary.

In this case, the table 21 (target side record set) and the table 22 shown in FIG.
(Record set on condition side) is a large capacity memory (EBDM) 1
The description will be continued assuming that the data has been input to the input buffer on 63.

Engine Control Processor (ECP) 162
Is an engine interface processor (EIP) 16
When the designated record set (tables 21 and 22) is input by 1, the N (of the entire records) between the target side record set (table 21) and the condition side record set (table 22) is input.
Constraints based on the OT EQUAL decision are made as described below.

First, the engine control processor (ECP)
162 is a hardware sorter control processor (ECA).
M) 164, a constraint process (NOT) based on the NOT EQUAL determination, as indicated by symbol b in FIG.
Request EQUAL specification constraint processing) (step S)
2). As a result, the hardware sorter control processor (ECAM) 164 changes the operation mode of the parallel relational algebraic operation module (PRAM) 166 to NOT EQUA.
Set to L constraint. In this constraint processing request b, the large capacity memory (EBD) to which the constraint processing result is output is output.
M) An area (output buffer) on 163 is also designated.

Next, the engine control processor (ECP)
A hardware sorter control processor (ECAM) 1 162 inputs a record of the constraint condition (Table 21) to the parallel relational algebra operation module (PRAM) 166.
The restriction conditions (Table 22) are notified to 64 as indicated by the symbol c in FIG. 1 (step S3).

Hardware sorter control processor (EC
AM) 164 is an engine control processor (ECP) 1
When the constraint condition notification c from 62 is received, the record of the specified constraint condition (Table 22) stored in the large capacity memory (EBDM) 163 is read via the internal bus 167, and the parallel sorting module (PSOM) 165 is loaded. Through parallel relational algebraic operation module (PRAM) 166
Input to the condition side buffer in. The number of input records is equal to that of the parallel sorting module (PSOM) 165.
There is an upper limit determined by the configuration (number of columns) of the sort cell of, and input of records exceeding the upper limit (allowable number) is waited. The parallel relational algebra calculation module (PRA
M) The capacity of the condition side buffer in 166 matches this upper limit value.

Parallel Relational Algebra Operation Module (PRAM)
The constraint condition input to the condition side buffer of 166, that is, the record group of Table 22 is a parallel sorting module (P) which is a dedicated hardware circuit for executing sorting in parallel.
SOM) 165, so they are sorted (here, they are sorted in alphabetical order by employee name),
It is as shown in Table 24 of FIG. Note that this is not the case when the number of records in Table 22 exceeds the upper limit value described above and cannot fit in the condition side buffer of the parallel relational algebra calculation module (PRAM) 166.

Next, the engine control processor (ECP)
162 indicates to the hardware sorter control processor (ECAM) 164 by the symbol d in FIG. 1 in order to constrain the constraint target with the parallel relational algebraic operation module (PRAM) 166 based on the constraint condition notified previously. As shown, the restriction target (Table 21) is notified (step S).
4).

Hardware sorter control processor (EC
AM) 164 is an engine control processor (ECP) 1
Upon receiving the constraint target notification d from 62, the record of the designated constraint target (Table 21) stored in the large capacity memory (EBDM) 163 is read via the internal bus 167, and the parallel sorting module (PSOM) 165 is loaded. Through parallel relational algebraic operation module (PRAM) 166
To enter. As a result, in the parallel relational algebra calculation module (PRAM) 166, the records of the constraint target (Table 21) are recorded in the parallel sorting module (PSOM) 16
5 is sorted and input. Therefore, Table 21
Records of the parallel sorting module (PSO
In M) 165, the result is as shown in Table 23 of FIG.

Then, the parallel relational algebra operation module (P
Every time the constraint target record is input, the RAM) 166 compares the record with the constraint condition in the condition side buffer (which has been previously input) to determine the identity of the record. When it is determined that the record matching the target record is not on the condition side, the parallel relational algebraic operation module (PRAM) 166 outputs the target record to the hardware sorter control processor (ECAM) 164. Hardware sorter control processor (ECA
The M) 164 stores this record in the output buffer on the large capacity memory (EBDM) 163 designated by the engine control processor (ECP) 162 (at step S2).

The parallel relational algebra operation module (P
The constraint process in the RAM) 166 is repeated until there is no target record input through the parallel sorting module (PSOM) 165 (step S5).
Then, when the processing is completed for all the input constraint target records, the parallel relational algebra operation module (PRA
M) 166 notifies the hardware sorter control processor (ECAM) 164 to that effect. Then, the hardware sorter control processor (ECAM) 164 notifies the engine control processor (ECP) 162 of the completion of the process as indicated by the symbol e in FIG.

In response to this, the engine control processor (E
The CP) 162 checks whether or not the processing for all the records of the constraint conditions has been completed (step S6). If there are still unprocessed constraint condition records because all condition records could not fit into the condition side buffer in the parallel relational algebraic operation module (PRAM) 166, the engine control processor (ECP) 162
Determines a new output result obtained on the large-capacity memory (EBDM) 163 by the constraint processing of the NOTEQUAL specification until then (step S7).

In this case, the engine control processor (EC
P) 162 returns to step S2, and controls the hardware sorter control processor (ECAM) 164 to perform the same processing as described above for restricting a new target by NOT EQUAL designation based on the remaining conditions. And
When the above process is executed for all condition records, the output result at that time becomes the result of the desired difference set operation.

In the flowchart of FIG. 3, the processing of each step is not executed serially, but the processing that can be executed in parallel is processed in parallel. For example, in FIG.
In the flowchart of FIG. 5, after the target side set and the condition side set are input to the input buffer on the large capacity memory (EBDM) 163 (step S1), the records of the condition side set of the two sets on the input buffer are parallel. Although it is shown as being taken in by the parallel relational algebraic operation module (PRAM) 166 via the sorting module (PSOM) 165 (step S3), parallel processing of both steps S1 and S3 is possible by the following. Becomes That is,
In step S1, first, a constraint condition (a set) is input, and then a constraint target is input. By performing step S3 in parallel with the input of the constraint target, the constraint target is converted into the large-capacity memory (EBDM). ) While typing in 163,
The constraint conditions that have already been input are converted into a parallel relational algebra module (P
It can be loaded into the RAM) 166 and high-speed processing becomes possible.

The case of the difference set operation for two sets has been described above, but the present invention is a difference set operation for three or more sets, that is, from a set (target) element to another. The same process can be applied to the calculation for obtaining a set formed by excluding an element belonging to any of two or more sets (conditions). Further, in the difference set operation for three or more sets, it is also possible to obtain the union of the condition side sets and perform the operation using this union as a condition.

[0055]

As described above, according to the present invention, the arithmetic processing device for executing the arithmetic processing on the file data to be operated in response to the request from the host device is provided with the first to third processors. Adopting a multiprocessor configuration, the data input / output between the arithmetic processing device and the secondary storage device is performed by the first processor, the arithmetic processing using the arithmetic circuit is performed by the second processor, and the overall control is performed. The functions are distributed to the respective third processors, and the parallel operation of the data input / output by the first processor and the arithmetic processing by the second processor is executed and controlled by the third processor. When a difference set operation is requested, under the control of the third processor,
The first processor inputs the set to be subjected to the difference set operation, and the second processor inputs the set to the arithmetic circuit to automatically sort using the sorting function of the circuit, and the set after the sorting. NOT EQ against
Since the restriction processing of the UAL designation is configured to be performed in the same circuit, the difference set operation can be performed at high speed by effectively utilizing the operation processing device (database operation processing device), and the host device at the time of the difference set operation process. The load of can be reduced, and an efficient data processing device can be realized as the entire system.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration of a data processing device according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a difference set operation with a specific example.

FIG. 3 is a flowchart for explaining a procedure of difference set calculation processing in the same embodiment.

[Explanation of symbols]

10 ... Host computer, 11 ... CPU, 13 ... System bus, 16 ... Database processing unit (DB)
E), 17 ... Magnetic disk device (secondary storage device), 18
... Path, 161 ... Engine interface processor (EIP, first processor), 162 ... Engine control processor (ECP, third processor), 163 ... Large-capacity memory (EBDM, internal memory), 164 ... Hardware (HW) Sorter control processor (ECAM, second
, 165 ... Parallel sorting module (PSOM, arithmetic circuit), 166 ... Parallel algebraic arithmetic module (PRAM, arithmetic circuit), a ... Input processing request,
b ... NOT EQUAL designated constraint processing request, c ... constraint condition notification, d ... constraint target notification, e ... processing completion notification.

Claims (1)

[Claims] 1. A host device, a secondary storage device for storing file data to be operated, and a path for directly accessing the secondary storage device, wherein the operation is performed in response to a request from the host device. In a data processing device including an arithmetic processing device that executes a predetermined arithmetic process on target file data, the arithmetic processing device is configured to communicate with the host device and to communicate with the secondary storage device. A first processor for performing data input / output of
An arithmetic circuit for performing a sort or relational algebraic operation, a second processor for controlling execution of the arithmetic operation by the arithmetic circuit, file data to be arithmetically input by the first processor, and an arithmetic result by the arithmetic circuit are stored. A third processor that controls the operation of the first and second processors based on an instruction from the host device that is supplied via the first processor. The processor controls the first processor to input the target set and controls the second processor when a difference set operation is requested from the host device to the operation processing device. Then, the input sets are sorted in the arithmetic circuit and sequentially taken into the same circuit, and the not equal (N A data processing device, characterized in that constraint processing is performed by specifying OT EQUAL).