JPH0634520B2 - Video signal processing device for still images - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a still image video signal processing device capable of pseudo-easily reproducing halftones and intermediate colors in a still image.

(Prior Art) With the recent spread of semiconductor memories, television receivers,
BACKGROUND ART It has been practiced to store a video image of a video tape recorder, a video camera, etc., and display it as a still image on a monitor television or output it to a printer. In addition to this, image processing and image analysis for enlarging, reducing, or extracting a feature of the stored image by a Perlnal computer or the like have been developed mainly in the field of industrial design.

However, if a still image is faithfully reproduced with respect to the input image, for example, in the case of a color image composed of red, green, and blue, at least 4 bits to 8 bits (16 colors to 256 colors) for each color. It is said that the resolution of is necessary. Since a large-capacity memory is required to store such a large amount of video data, even though the semiconductor memory tends to be low in price, the price of the memory as a whole becomes considerably high. In addition, such an increase in the memory capacity causes a problem that the scale of the peripheral circuit becomes large.

On the other hand, in the field of obtaining a still image by binarizing an input image, for example, in the field of photo transmission and facsimile, the so-called dither method is well known as a means for obtaining a still image. In this method, a video signal obtained from an original image is input to a comparator whose threshold level is varied stepwise to obtain a plurality of binarized images having different gradations. Then, this image is appropriately combined to obtain a single still image having continuous gradation (shading).

However, according to such a method, there is a problem in that a circuit for changing the threshold value is required and the device becomes complicated. There is also a problem that the process for combining a plurality of binarized images as described above is complicated and it is difficult to perform this in real time.

Therefore, in order to solve this problem, the present applicant has proposed Japanese Patent Application No. 60-259150 (the title of the invention "a video signal processing method and apparatus for still images" filed on November 18, 1985).

FIG. 5 is a circuit block diagram of the invention according to this proposal (hereinafter referred to as a first conventional example), and FIG. 6 is a concrete configuration diagram of the pseudo intermediate color generation circuit of the first conventional example shown in FIG. is there. In the first conventional example, a clock pulse is superimposed in the vicinity of the average value level of a still image, and this clock pulse superimposed video signal is applied to an external display device based on sampling at a timing shorter than the cycle of the clock pulse. It is the case.

However, in the first conventional example, the control unit 11
The clock pulse applied from 0 to each of the memories 91, 92, 93 and the clock pulse of the pseudo intermediate color generation circuit 70 are not synchronized. Therefore, there is another problem in that the phase difference component between both clock pulses causes interference on the screen, and the interference moves around on the screen, making the screen very unsightly.

In order to solve this problem, the applicant of the present invention is further directed to Japanese Patent Application No. 61-989.
68 (Title of Invention “Still image processing device” filing date
April 28, 1986 Hereinafter, the second conventional example) was proposed. A second conventional example according to this proposal is a clock pulse superimposing means for blocking direct current of a clock pulse output from the clock pulse generating means and superimposing this on a video signal of a still image, and an image on which the clock pulse is superposed. A switching transistor that waveform-shapes the signal at a threshold level that is approximately equal to the average value level of the video signal, sampling means that samples the waveform-shaped signal at a timing shorter than the clock pulse cycle, and the sampled signal is stored. And a signal conversion means for appropriately converting the content stored in the storage means and outputting it as video data.

Then, by synchronizing the clock pulse superimposed on the video signal with the video signal, the beat component of the video signal and the clock pulse, which appears as an interference on the screen, is stopped on the screen.

However, in the second conventional example, although the interference stripe is stationary on the screen, it appears as an oblique stripe pattern, and therefore, there remains a problem that the unsightly appearance on the screen is not reduced so much.

(Object of the Invention) The present invention has been made in view of such circumstances, and it is possible to express the gradation of a still image with a relatively simple configuration and display the still image on the screen. In this case, it is an object of the present invention to make the screen easier to see by setting the static interference stripes appearing on the screen in the vertical direction instead of the oblique direction.

(Structure of the Invention) In order to achieve the above-mentioned object, the present invention is synchronized with a first clock pulse and this first clock pulse, and is n times the first clock pulse (where n is a positive integer of 2 or more). Clock pulse generating means for generating and outputting a second clock pulse having a frequency of, and creating a superimposed video signal by superposing the first clock pulse from the clock pulse generating means on a given video signal. The superimposed video signal is binarized
And a memory for storing the binarized signal output from the pseudo intermediate color generating unit by sampling the second clock pulse as the sampling clock pulse and storing the binarized signal output. .

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit block diagram of a still image video signal processing apparatus according to an embodiment of the present invention, and FIG. 2 is a signal waveform diagram in each part of the circuit shown in FIG. In these figures, 1 is 14.318 synchronized with a video signal as a sampling clock pulse for a memory described later.
A control unit 2 that outputs a second clock pulse of MHz and a predetermined clock pulse for an A / D conversion circuit and a D / A conversion circuit described later, and a second clock pulse given from the control unit 2 The frequency is divided and the first clock pulse (frequency is 1/4 of 14.318 MHz, that is,
The frequency divider circuit 3 outputs the signal at 3.58 MHz). The waveform of the first clock pulse is shown in FIG. 2 (c).

Therefore, the second clock pulse is synchronized with the first clock pulse and is n times the first clock pulse (however,
n is a positive integer of 2 or more, and has a clock pulse frequency of 4) in the embodiment.

Reference numeral 4 superimposes the first clock pulse from the frequency dividing circuit 3 of the clock pulse generating means 1 on the luminance signal Y shown in FIG. 2 (b) to create the superimposed luminance signal shown in FIG. 2 (d). Clock pulse superimposing circuit 5 and matrix circuits 6a, 6b, 6 for adding and outputting each of color difference signals BY (see FIG. 2A), RY, G-Y to the superimposed luminance signal.
Pseudo-intermediate color generation consisting of c and A / D conversion circuits 7a, 7b, 7c that output the binarized signal shown in FIG. 2 (e) based on the addition output from each of the matrix circuits 6a, 6b, 6c. It is a means.

The clock pulse superposing circuit 5 is a transistor TR3 to which the first clock pulse from the frequency dividing circuit 3 is given to the base.
And the first output from the emitter of the transistor TR3
Variable resistor VR for adjusting the level of the clock pulse, DC blocking capacitor C for blocking the DC component of the first clock pulse, and transistor for superimposing the first clock pulse given to the emitter on the luminance signal given to the base. And TR2. The DC blocking capacitor C has the function of improving the frequency characteristics of the video signal. That is, the DC blocking capacitor C serves as emitter peaking of the transistor TR2. Therefore, if the capacitance value of the DC blocking capacitor C is reduced, the high frequency band of the video signal is emphasized, and as a result, it is possible to emphasize the halftone color where the change of the screen is large, and therefore The image quality can be improved.

Each of the matrix circuits 6a, 6b, 6c receives a color difference signal at the base and a luminance signal (superposed luminance signal) on which the first clock pulse is superposed on the emitter, and at the same time, the superposed luminance signal and the color difference signal from the collector. Transistors TR1a, TR1b, which output the addition signal of
Includes TR1c.

The A / D conversion circuits 7a, 7b and 7c are the matrix circuits 6 respectively.
By performing analog-to-digital conversion (A / D conversion) on the added signals from a, 6b, and 6c, the binarized signal shown in FIG. 2 (e) is output.

Reference numerals 8a, 8b, and 8c denote memories for storing the binarized signals from the A / D conversion circuits 7a, 7b, and 7c by sampling and storing the second clock pulse given from the control unit 2 as a sampling clock pulse. Is memory 8
It is a D / A conversion circuit that performs digital-analog conversion (D / A conversion) on the signals read from a, 8b, and 8c.

In addition, 10 is a color difference signal BY, R- by demodulating a video signal.
A decoder for outputting Y, G-Y, 11 separates horizontal and vertical sync signals from the video signal, outputs a clamp pulse to the decoder 10, and outputs horizontal and vertical sync signals to the control unit 2. Is a sync separation circuit that outputs
The control unit 2 generates the second clock pulse synchronized with the video signal based on the horizontal and vertical synchronization signals supplied from the synchronization separation circuit 11.

Next, the operation will be described with reference to FIG. 2, FIG. 3 and FIG. In this description, BY will be described as a representative of the color difference signals.

A color difference signal (BY) as shown in FIG. 2 (a) is output from the decoder 10 which decodes the video signal. The color difference signal (BY) is input to the base of the transistor TR1a in the matrix circuit 6a.

On the other hand, the second clock pulse from the control unit 2 receives the frequency dividing circuit 3
Then, the frequency dividing circuit 3 outputs a first clock pulse as shown in FIG. 2 (c). The first clock pulse is applied to the base and emitter of the transistor TR3 of the clock pulse superposing circuit 5 and the emitter of the transistor TR2 via the DC blocking capacitor C. The base of the transistor TR2 has a second
The luminance signal as shown in FIG. As a result, the superimposed luminance signal having the waveform as shown in FIG. 2D is output from the collector of the transistor TR2. This superimposed luminance signal is input to the emitter of the transistor TR1a of the matrix circuit 6a.

In the transistor TR1a, the color difference signal (B-
Y) and the superimposed luminance signal Y are added, and as a result, the blue signal B on which the clock pulse is superimposed is output from the collector of the transistor TR1a. This blue signal B is
The signal is binarized by the A / D conversion circuit 7a and output from the circuit 7a as a signal having a waveform as shown in FIG. 2 (e).

3 (a) and 3 (b) are waveform diagrams used for concrete description of how the blue signal B on which the clock pulse is superimposed is binarized by the A / D conversion circuit 7a. As shown in (a), the blue signal B on which the first clock pulse is superimposed is input to the A / D conversion circuit 7a. The A / D conversion circuit 7a has a threshold level as shown in FIG. 3 (a), and inverts a high level input signal B exceeding the threshold level to output a low level output. Then, for a low level input signal B equal to or lower than this threshold level, it is similarly inverted and a high level output is output. Therefore, when the signal B as shown in FIG. 3 (a) is input to the A / D conversion circuit 7a, the A / D conversion circuit 7a outputs the signal B shown in FIG. 3 (b).
A signal having a waveform as shown in is output.

FIG. 4 (a) is a partially enlarged waveform diagram in the vicinity of the threshold level of FIG. 3 (a), and FIG. 4 (b) corresponds to FIG. 4 (a) and is also shown in FIG. 3 (b). It is a partially expanded waveform diagram. As is clear from FIGS. 4 (a) and 4 (b), the high level of the blue signal B is, for example, yellow,
When the low level is cyan, yellow and cyan are repeated in the halftone process of shifting from the high level to the low level, and the halftone color is obtained. In this case, the pulse width (duty ratio) in one cycle of the clock pulse changes sequentially around the threshold level [in the case of FIG. 4 (b), the pulse width changes in the direction of decreasing sequentially]. Therefore, the halftone changes sequentially.

Next, the second clock pulse from the controller 2 is sent to the memory 8
a, 8b, 8c. Memories 8a, 8b, 8c
Responds to the input second clock pulse as the sampling clock pulse, in response to the A / D conversion circuit 7a,
The output from each of 7b and 7c is stored. Each color signal stored in each of the memories 8a, 8b, 8c is read by a control signal from the control unit 2, converted into an analog signal by each of the D / A conversion circuits 9a, 9b, 9c, and displayed on a television monitor (not shown). Be done.

In this embodiment, the memory 8 synchronized with the video signal
Since the sampling clock pulse (second clock pulse) of a, 8b, and 8c and the first clock pulse superimposed on the luminance signal are synchronized, the beat of the luminance signal and the clock pulse appearing on the screen of the television monitor. The interference caused by the component is stable, and the sampling clock pulse is set to 4 times the frequency of the first clock pulse, so the interference is arranged vertically on the screen, which makes the screen difficult. It becomes easy to see.

In the present invention, the phase of the clock pulse is inverted for each line of horizontal scanning, and the interference stripes are arranged in a vertical and horizontal lattice pattern, so that the visibility of the screen can be further improved.

Further, according to the present invention, in the conventional example shown in FIG. 5, a clock pulse obtained by dividing a clock pulse (corresponding to the second clock pulse in the above embodiment) given to the memories 91 to 93 from the control unit 110. By inputting (corresponding to the first clock pulse of the present invention) to the pseudo intermediate color generation circuit 70, the sampling clock pulse given to the memories 91 to 93 and the clock pulse given to the pseudo intermediate color generation circuit 70 are synchronized, and The pulse frequency relationship may be an integral multiple, and the present invention includes such a case.

(Effects of the Invention) As is apparent from the above description, according to the present invention,
Since the clock pulse is superimposed around the average value level of the video signal and binarized, it is not necessary to change the threshold of the switching transistor as in the case of the conventional dither method. In addition to the effect of being able to realize a device capable of reproducing a color tone and an intermediate color with a relatively simple configuration, there is no need to perform a process for combining a plurality of binarized images as in the case of using the dither method. It is possible to output the video signal of the image in real time.

Further, according to the present invention, in particular, the clock pulse superimposed on the video signal is synchronized with the sampling clock pulse of the memory synchronized with the video signal. There is. Furthermore, in this case, since the frequency of the sampling clock pulse is set to an integer multiple of the clock pulse, the interference stripes are perfectly regularly arranged in the vertical direction on the screen,
The interference does not matter much on the screen, and the screen is very easy to see.

[Brief description of drawings]

1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is an operation waveform diagram of the circuit shown in FIG. 1, and FIG. 3 is a collector output waveform of the transistor TR1a of FIG. 1 and an A / D conversion circuit. 7a and the output waveform of FIG. 7, FIG. 4 is a partially enlarged waveform diagram centered on the threshold level of FIG. 3, FIG. 5 is a circuit diagram of a conventional example, and FIG. 6 is a pseudo intermediate color shown in FIG. It is a concrete block diagram of a generation circuit. 1 is a clock pulse generation circuit, 4 is a pseudo intermediate color generation circuit, 5 is a clock pulse superposition circuit, 6a, 6b and 6c are matrix circuits, 7a, 7b and 7c are A / D conversion circuits,
8a, 8b and 8c are memories.

Claims (1)

[Claims] 1. A first clock pulse, and a frequency synchronized with the first clock pulse and a given video signal and having a frequency n times the first clock pulse (where n is a positive integer of 2 or more). Clock pulse generating means (1) for respectively generating and outputting two clock pulses; and superimposing a video signal by superimposing the first clock pulse from the clock pulse generating means (1) on the video signal, and The superimposed video signal is binarized
Pseudo-intermediate color generating means (4) for outputting as a binarized signal, and a memory (8a, for storing the binarized signal from the pseudo-intermediate color generating means (4) by sampling the second clock pulse as a sampling clock pulse. 8b, 8
(c) A still image video signal processing device comprising: