JPH06338787A - Charge pump circuit for pll frequency synthesizer - Google Patents

Abstract

PURPOSE:To obtain a charge pump circuit for a PLL synthesizer capable of maintaining the operating characteristic of a PLL satisfactorily and shortening lock-up time. CONSTITUTION:The charge pump circuit 16 is constituted of a differential circuit using a pair of bipolar transistors of the same junction type, and a push-pull circuit using a current mirror circuit consisting of the pair of bipolar transistors of the same junction type. Two output of a phase comparator 15 are inputted to the differential input terminal of the difference circuit in the charge pump circuit 16, and a differential operation is performed, and three values are outputted from the charge pump circuit 16 by performing a push-pull operation by the push-pull circuit corresponding to such differential output. The off-leak current of the bipolar transistor which constitutes the difference circuit represents satisfactory symmetry, and also, all the current mirror circuits in the push-pull circuit are comprises of the bipolar transistor of same characteristic, therefore, the influence of the off-leak current on a circuit at the next stage can be extremely suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer, and more particularly to a charge pump circuit for a frequency synthesizer using a phase locked loop.

[0002]

2. Description of the Related Art In wireless communication devices or broadcast receiving devices,
A frequency synthesizer using a PLL (phase locked loop) is used as a local oscillator. Generally, PLL frequency synthesizer circuits used in these fields are
A crystal oscillator that generates a reference signal by an externally connected crystal oscillator, a reference frequency divider that generates a reference signal by dividing the oscillation output of this crystal oscillator with a predetermined frequency division ratio, a voltage-controlled oscillator (hereinafter , VCO) and a comparison frequency divider that divides the oscillation signal with a variable division ratio, and a phase comparison between the frequency division output of the reference frequency divider and the frequency division output of the comparison frequency divider. A phase comparator that outputs a signal, a charge pump circuit that outputs a ternary signal according to the output of this phase comparator, and an output of this charge pump circuit are integrated to obtain a VCO with a voltage that corresponds to the phase difference. Low-pass filter to control (hereinafter L
PF)), and.

A charge pump circuit used in such a PLL frequency synthesizer circuit can be constituted by a push-pull circuit composed of a PMOS type transistor 51 and an NMOS type transistor 52, as shown in FIG. 4, for example. With this circuit, two input terminals 31, 3
An "H" or "L" level signal is input to 2 from the preceding phase comparator according to the comparison result, and operates as follows.

(1) When the output phase of the comparison frequency divider is delayed from the output phase of the reference frequency divider, the input terminal 3
An “L” level signal is input to both 1 and 32. As a result, the transistor 51 is turned on and the transistor 52 is turned off, so that a push current flows from V _CC through the transistor 51 to the LPF of the next stage from the output terminal 39. As a result, the capacitor C in the LPF is charged and the LPF
Output voltage increases, the output frequency of the VCO in the next stage increases, and the phase difference decreases.

(2) When the output phase of the comparison frequency divider leads the output phase of the reference frequency divider, the input terminals 31, 32
An "H" level signal is input to both of them. As a result, the transistor 52 is turned on and the transistor 51 is turned off, so that the pull current flows from the capacitor C in the LPF to the output terminal 39, and flows through the transistor 52 to GND. In this case, the capacitor C in the LPF is discharged, the output voltage of the LPF decreases, the output frequency of the VCO in the next stage decreases, and the phase difference decreases.

(3) In cases other than the above, for example, when the phases match, the "H" and "L" level signals are input to the input terminals 31 and 32, respectively, and the transistors 51 and
Since both 52 are turned off, there is no push current or pull current, and the output of the LPF is maintained at the previous level. still,
In order to match the signal of FIG. 3, an inverter may be connected to the input terminal 31.

[0007]

In the charge pump circuit (FIG. 4) having the above-described MOS type transistor, the transistors 51 and 52 do not include a PN junction, so that a so-called leak occurs when the transistor is off. The current is low. Therefore, as in the case of (3) above, for example, even when both transistors are turned off, the VCO rarely malfunctions due to the leak current, and the C / N characteristic of the PLL is good.

However, this MOS type circuit generally has a drawback that the operation speed is slow and the lock time of the PLL becomes long. This drawback becomes a serious problem in the following cases.

Generally, in a cordless telephone, a mobile telephone or the like having a PLL synthesizer circuit, a battery is used as a power source, but intermittent driving is performed to save power consumption. For example, as shown in FIG. 6, the slave unit has a predetermined period T.
The polling is performed on the base unit to receive an incoming call signal. In this case, in the slave unit, this cycle T (for example, 1 second)
Each time, the power is turned on to operate the PLL, and data is transferred after waiting for the PLL to lock.
Therefore, the power-on time is the sum of the lock-up time t1 of the PLL and the actual communication time t2 (generally about several tens of ms). Therefore, if the lock-up time t1 of the PLL is long, the power supply is in standby. There is a problem that the charging time becomes longer and the battery life becomes shorter. Therefore, it is desired to shorten the lockup time t1 of the PLL as much as possible.

In order to reduce the time, for example, as shown in FIG. 5, a method of forming a charge pump circuit with a bipolar PNP transistor 53 and an NPN transistor 54 can be considered. In this circuit, the operating speed is higher than that of the MOS type, and the purpose of shortening the lockup time of the PLL can be achieved.

However, in this circuit, since the transistors 53 and 54 include the PN junction, there is a large amount of leak current. Moreover, in this case, since the junction types of both transistors are different, it is difficult to make the characteristics of both transistors uniform in manufacturing, and when both transistors are off, there is a non-negligible difference between the leakage current values. Occurs. This difference in leak current value appears as a push current or a pull current from the output terminal 39 and causes a malfunction of the VCO.

As described above, in the conventional charge pump circuit of the PLL synthesizer, it is difficult to simultaneously satisfy the two conditions of improving the operation speed and maintaining the operation accuracy.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a charge pump circuit of a PLL synthesizer capable of maintaining good PLL operation characteristics and shortening the lockup time. And

[0014]

SUMMARY OF THE INVENTION A charge pump circuit of a PLL synthesizer according to the present invention is a crystal oscillator circuit for generating a reference signal, and the output of the crystal oscillator is frequency-divided to generate a P signal.
A reference frequency divider that generates an LL reference frequency signal, a voltage controlled oscillator whose oscillation frequency is controlled by an applied voltage, a comparison frequency divider that divides the output signal of this voltage controlled oscillator, and this comparison frequency divider. A frequency comparator that compares the frequency-divided output of the frequency divider with the phase of the frequency-divided output of the reference frequency divider, and outputs a pulse having a width corresponding to the phase difference, and 3 depending on the output of the phase comparator. In a PLL synthesizer including a charge pump circuit that outputs a value signal and a low-pass filter that generates a voltage for controlling the voltage controlled oscillator circuit based on the output of the charge pump circuit, the charge pump circuit comprises: (i) A differential circuit including the same junction type bipolar transistor pair, which differentially operates using two outputs of the phase comparator as inputs, and (ii) the same junction type bipolar transistor pair. Ranaru comprises a current mirror circuit, is characterized in that it has a push-pull circuit performs a push-pull operation in accordance with the differential output of the differential circuit.

[0015]

In the charge pump circuit of the PLL synthesizer according to the present invention, the two outputs output from the phase comparator according to the phase difference between the frequency division output of the comparison frequency divider and the frequency division output of the reference frequency divider are , Is input to the differential input terminal of the differential circuit of the charge pump circuit, and three-value output is performed by the push-pull operation of the push-pull circuit according to the differential output of the differential circuit.

[0016]

The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a PLL according to an embodiment of the present invention.
This shows the overall structure of the synthesizer. The circuit shown in this figure is a PLL used in a mobile communication device such as a cordless phone or a mobile phone or a broadcast receiving device.
A reference oscillator 1 which is a synthesizer circuit and generates a reference signal by an externally connected crystal unit (not shown).
1, a reference frequency divider 12 for generating a reference signal by dividing the oscillation output of the reference oscillator 11 at a predetermined frequency division ratio, and a VCO
A comparison frequency divider 1 for dividing the oscillation signal of 13 with a variable division ratio.
4 and the frequency-divided output of the reference frequency divider 12 and the frequency-divided output of the comparison frequency divider 14 are compared in phase to obtain two phase difference signals 18, 1.
9, a phase comparator 15 that outputs 9, a charge pump circuit 16 that outputs a ternary signal 20 in accordance with the output of the phase comparator 15, and an output of the charge pump circuit 16 that is integrated to obtain a phase difference. L that controls the VCO 13 with different voltage
It is composed of PF17.

Next, an outline of the operation of the PLL synthesizer circuit having such a configuration will be described.

In this circuit, a reference frequency signal A having a constant frequency as shown in FIG. 3A is generated by the reference frequency divider 12, while a VCO 13 is generated by the comparison frequency divider 14.
A frequency division output B (FIG. 7B) obtained by frequency-dividing the oscillating signal of 1 by a predetermined frequency division ratio is obtained. Then, the phase comparator 15 compares the frequency-divided output B of the comparison frequency divider 14 with the phase of the reference frequency signal A from the reference frequency divider 12, and as shown in (c) and (d) of FIG. The phase difference signal 18 or 19 having a pulse width corresponding to the phase difference between the two is output. Here, when the phase of the divided output B leads the reference frequency signal A, the phase difference signal 18 having a pulse width corresponding to the phase difference is generated.
((C) in the figure) is output, and conversely, when the phase of the frequency-divided output B lags the reference frequency signal A, the phase difference signal 19 having the pulse width corresponding to the phase difference ((d) in the figure). Is output.

These phase difference signals are converted into a ternary signal by the charge pump circuit 16, and further the LPF 17 is supplied.
A control voltage V _o for controlling the VCO 13 is obtained by being integrated by. VCO13 outputs an oscillation signal of a frequency corresponding to the control voltage V _o, is input to the comparison frequency divider 14. In this way, the oscillation signal of an integral multiple of the frequency of the reference frequency signal A is obtained by VCO 13, which becomes the external output frequency signal f _o. This signal is used as, for example, a local oscillation frequency signal, and the frequency can be changed by changing the division ratio of the comparison frequency divider 14.

Next, the charge pump circuit 1 in FIG.
The configuration and operation of No. 6 will be described.

FIG. 2 shows an example of the configuration of the charge pump circuit. This circuit is provided with input terminals 31 and 32 for inputting the phase difference signals 18 and 19 from the phase comparator 15, respectively. Of these, the first input terminal 31 is connected to the base of the first transistor Q1 forming the differential circuit via the resistor 34, and
It is connected to ground via a diode 35. On the other hand, the second input terminal 32 is connected to the base of the second transistor Q2 forming the differential circuit via the resistor 36, and is also connected to the ground via the diode 37.

The emitters of transistors Q1 and Q2 are
They are connected to each other and further connected to the ground via a resistor 38 as a constant current source. The collector of the transistor Q1 is the transistor Q of the first current mirror circuit in which the bases of the transistors Q3 and Q5 are mutually connected.
3 is connected to the collector of the transistor Q2, and the collector of the transistor Q2 is the transistor Q4 of the second current mirror circuit in which the bases of the transistors Q4 and Q6 are interconnected.
Connected to the collector. Transistors Q3 and Q
In 4, the base and collector are directly connected to each other, and each emitter is connected to the power supply V _CC .

The collector of the transistor Q5 which constitutes the first current mirror circuit and the collector of the transistor Q6 which constitutes the second current mirror circuit are the third current mirror circuit in which the bases of the transistors Q7 and Q8 are connected to each other. Are respectively connected to the collector of the transistor Q7 and the collector of the transistor Q8. The emitters of transistors Q5 and Q6 are connected to V _CC .

The collector of the transistor Q7 of the third current mirror circuit is connected to the base of a transistor Q9 for base current correction whose emitter is connected to the bases of the transistors Q7 and Q8. This transistor Q
The collector of 9 is connected to V _CC . The collector of the transistor Q8 is also connected to the output terminal 39. The emitters of the transistors Q7 and Q8 are both grounded.

The operation of the charge pump circuit having the above configuration will be described with reference to FIG.

Input terminals 31, 32 from the phase comparator 15
In addition, the phase difference signal 1 as shown in FIGS.
When 8 and 19 are input, they are applied to the bases of the transistors Q1 and Q2 of the differential circuit, respectively. This charge pump circuit operates as follows according to the combination of the voltages applied to the bases of the transistors Q1 and Q2.

(I) In case of phase lead state In FIGS. 3 (a) and 3 (b), when the phase of the divided output B is ahead of the reference frequency signal A, the pulse width position corresponding to the phase difference is The phase difference signal 18 ((c) in the figure) is output. At this time, the input terminal 3 of the charge pump circuit 16
Since "H" and "L" level signals are input to 1 and 32, respectively, only the transistor Q1 is turned on, and the current I1 flows from V _CC to the transistor Q1 through the transistor Q3, while the current I1 flows to the transistor Q2. Does not flow current. As a result, the current I1 also flows through the transistor Q5 of the first current mirror circuit, and the same current I1 flows through the transistors Q7 and Q8 of the third current mirror circuit.
Flows. At this time, since no current flows in the transistor Q4 of the second current mirror circuit, the transistor Q4
No electric current flows through 6. Therefore, the current I1 flowing from the output terminal 39 flows through the transistor Q8. This current is the discharge current of the next capacitor LPF 17 (FIG. 1), reducing the output voltage V _o of the LPF 17.

When the output voltage V _{o of the} LPF 17 decreases,
Since the oscillation frequency (f _o ) of the VCO 13 is lowered, it is controlled so as to delay the phase of the frequency division output B of the comparison frequency divider 14, and the phase difference from the reference frequency signal A is reduced.

(II) Phase delay state In FIGS. 3 (a) and 3 (b), when the phase of the divided output B is delayed from the reference frequency signal A, the pulse width corresponding to the phase difference is placed. The phase difference signal 19 ((d) in the figure) is output. At this time, the input terminal 3 of the charge pump circuit 16
Since "L" and "H" level signals are input to 1 and 32, respectively, only the transistor Q2 is turned on, and the current I2 flows from V _CC to the transistor Q2 through the transistor Q4, while the current I2 flows to the transistor Q1. Does not flow current. As a result, the current I2 also flows through the transistor Q6 of the second current mirror circuit. At this time, the first
Since no current flows through the transistor Q5 of the current mirror circuit of, no current flows through the transistors Q7 and Q8. Therefore, the current I2 flowing through the transistor Q6 is
It will flow out from the output terminal 39. This current becomes the charging current for the capacitor of the LPF 17 (Fig. 1) in the next stage,
The output voltage of the LPF 17 is increased. When the output voltage V _{o of the} LPF 17 increases, the oscillation frequency (f _o ) of the VCO 13 increases, so the frequency division output B of the comparison frequency divider 14
Is controlled so that the phase of the signal is advanced, and the phase difference from the reference frequency signal A is reduced.

On the other hand, the phase comparator 15 has a dead zone (that is, despite the phase difference, the input terminals 31 and 32).
No pulse is input to any of the above). In this case, the base voltages of the transistors Q1 and Q2 are both at the "L" level, so that both of these transistors are off and no current flows in principle. However, as described in the description of the prior art, since these transistors Q1 and Q2 are of the bipolar type,
The leak currents I _L1 and I _L2 flowing therethrough are relatively large, and in fact, the same currents also flow to the transistors Q5 and Q6 of the first and second current mirror circuits, respectively.

However, since the two transistors Q1 and Q2 that form the differential circuit are NPN transistors of the same junction type, it is possible to make their characteristics coincide with each other with high accuracy in the manufacturing process, and the leakage is caused. Current I _L1 and I
It is easy to make _L2 equal. In addition, the two transistors Q3 and Q forming the first current mirror circuit
5 and the two transistors Q4 and Q6 forming the second current mirror circuit are PNP transistors of the same junction type, the current flowing through the transistors Q5 and Q6 is the current I flowing through the transistors Q3 and Q4, respectively. _{The L1} and I _L2 coincide with each other with high precision, and the currents I _L1 and I _L2 flowing through the transistors Q5 and Q6 respectively coincide with each other with high precision. Similarly, also in the third current mirror circuit, since the transistors Q7 and Q8 can be manufactured so that the characteristics thereof coincide with each other with high accuracy, the currents flowing through them respectively also coincide with each other with high accuracy. Therefore, all the currents I _L1 and I _L2 flowing through the transistors Q5 and Q6, respectively, flow through the transistors Q7 and Q8 as they are, and the current flows in and out of the capacitors of the LPF 17 of the next stage via the output terminal 39. Disappears. Alternatively, even if it occurs, it becomes extremely small compared to the case of the conventional circuit (FIG. 5). Therefore, the VCO 13 does not malfunction due to useless push or pull current.

When the frequency division output B and the reference frequency signal A are in phase with each other, as shown in FIGS. 3 (c) and 3 (d), a sharp instantaneous pulse, which is originally undesirable, is input terminal 3.
It may be input to both 1 and 32. In this case, since the "H" level voltage is applied to both bases of the transistors Q1 and Q2, both transistors are turned on and currents I _S1 and I _S2 respectively flow. Also in this case, the currents I _S1 and I _S2 coincide with each other with high accuracy, due to the same characteristics of the transistors Q1 and Q2, for the same reason as described above. Further, also in the subsequent operation, that is, in the operation of the first, second and third current mirror circuits, the current I _S1 flowing through the transistors Q5 and Q6 is caused by the highly accurate symmetry of the current flowing through each current mirror circuit. , I _S2
Are all transistors Q7 and Q8 as they are.
Through the output terminal 39 and the LP of the next stage.
Almost no current flows in or out of the capacitor of F17. Therefore, the VCO 13 does not malfunction due to useless push or pull current.

Since all the circuits described above are composed of bipolar transistors, the operating speed thereof is higher than that of the conventional circuit (FIG. 4), and the lockup time of the PLL is shortened.

[0035]

As described above, according to the present invention,
The charge pump circuit is composed of a differential circuit using the same junction type bipolar transistor pair and a push-pull circuit using a current mirror circuit consisting of the same junction type bipolar transistor pair, and two outputs of the phase comparator are provided. Is input to the input terminals of the differential circuit for differential operation, and the push-pull operation is performed according to the differential output of the differential circuit. While keeping it extremely small,
High-speed operation can be maintained.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a general PLL synthesizer.

FIG. 2 is a circuit diagram showing a charge pump circuit of a PLL synthesizer according to an embodiment of the present invention.

3 is a timing diagram showing a schematic operation of the PLL synthesizer of FIG.

FIG. 4 is a circuit diagram showing an example of a conventional charge pump circuit.

FIG. 5 is a circuit diagram showing another example of a conventional charge pump circuit.

FIG. 6 is an explanatory diagram for explaining a communication system in a cordless phone or a mobile phone.

[Explanation of symbols]

11 Reference Oscillator 12 Reference Divider 13 VCO 14 Comparison Divider 15 Phase Comparator 16 Charge Pump Circuit 17 LPF 31, 32 Input Terminal 39 Output Terminal Q1, Q2 NPN Transistor (Differential Circuit) Q3, Q5 PNP Transistor (No. 1 current mirror circuit) Q4, Q6 PNP transistor (second current mirror circuit) Q7, Q8 NPN transistor (third current mirror circuit)

Claims (1)

[Claims] 1. A crystal oscillator which generates a reference signal, a reference frequency divider which divides an output of the crystal oscillator to generate a reference frequency signal of a PLL, and a voltage whose oscillation frequency is controlled by an applied voltage. The controlled oscillator, a comparison frequency divider that divides the output signal of this voltage controlled oscillator, the frequency division output of this comparison frequency divider and the phase of the frequency division output of the reference frequency divider are compared, and the phase difference A phase comparator that outputs a pulse having a width corresponding to the voltage, a charge pump circuit that outputs a ternary signal according to the output of the phase comparator, and the voltage controlled oscillator is controlled based on the output of the charge pump circuit. In a PLL frequency synthesizer having a low-pass filter for generating a voltage for operating the charge pump circuit, the charge pump circuit includes a bipolar transistor pair of the same junction type, A differential circuit that operates differentially with two outputs as inputs, and a push-pull circuit that includes a current mirror circuit composed of the same junction type bipolar transistor pair, and that performs a push-pull operation according to the differential output of the differential circuit, A charge pump circuit for a PLL frequency synthesizer, comprising: