JPH06338535A - Tape automated bonding method utilizing solder bupm - Google Patents

Abstract

PURPOSE:To provide a tape automated bonding(TAB) method that an LSI chip electrode is connected to the lead of a film carrier, wherein bonding bumps formed on an electrodes or leads are made of solder so as to be lessened in forming cost and kept high in bonding reliability and to enhance a bonding process in yield taking advantage of the properties of solder. CONSTITUTION:Solder bumps are formed on the required spots of TAB leads or chip electrodes 27, and a copper oxide film 25 or a solder resist film is formed surrounding the solder bumps 24 so as not only to control the lead or the electrode in solder wettability but also to protect a copper foil pattern against corrosion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to tape automated bonding (TAB) for directly bonding an ultra-high density integrated circuit element (LSI) chip to a long resin film. A tape-automated tape using solder bumps, in which a predetermined bump is formed by solder on the electrode and the lead end on the film side, and the solder leak property is regulated in the part other than the surface of the bump, and the two are joined by melting the solder bump. -Regarding the bonding method.

[0002]

2. Description of the Related Art LSIs are widely used for miniaturization of various electronic devices, and TAB has recently been attracting attention as a mounting technique for mounting the LSIs on a circuit board. As you know, TA
B is a long resin film of the same form as the photographic film,
This is a method in which leads and wiring patterns are formed from copper foil, and LSI chips are bonded to them via bumps, and it is possible to bond them all at once regardless of the number of electrodes on the chip. This is a very effective bonding method for ultra-high pin count LSIs in which high cost and low yield cannot be avoided by wire-bonding the leads and leads individually.

The resin film used in the TAB is
Made of polyimide, epoxy resin containing glass fiber, or resin such as polyester with a thickness of 75 to 125 μm and a width of 35 to 70
mm long film shape, and the surface thereof has a predetermined lead or circuit pattern made of rolled copper, electrolytic copper, etc.
The film carrier is formed to have a thickness of up to 35 μm, and fine bump-like bumps are formed in advance on the lead end with pure gold or the like, and the bumps are pressed and heated at the time of bonding to the electrodes of the LSI chip. The bumps are extremely important for the TAB because they are bonded to each other.

Hereinafter, conventional bumps will be described with reference to FIGS. 1 and 2.
Will be described with reference to. In the figure, a large number of predetermined electrodes 2 are formed on the upper surface of the LSI chip 1, and a protective film (passivation) 3 for protecting the electrodes 2 is formed on each of the electrodes 2 and the electrodes 2 are formed. A multi-layer metal film (barrier metal) 4 is formed on the surface of, and bumps 5 of pure gold or the like are deposited on the top of the multi-layer metal film (barrier metal) 4 by electrolytic plating.

The shape of the bump 5 differs depending on the formation process thereof, and in the case of FIG. 1, it is called a mushroom bump, and the thickness of the photoresist film is 1 to 2 when forming the bump 5.
It is formed by electrolytic plating using a thin one having a thickness of μm. The example shown in FIG. 2 is called a straight wall bump and has a thickness of 1 when forming the bump 5.
This is a form that can be obtained when electrolytic plating is performed using a thick photoresist film having a thickness of 0 to 50 μm.

At the time of bonding, as shown in FIG. 3, the lead portion 7 of the film carrier 6 is heated and pressed from above the bumps 5. However, as described above, the general bumps 5 which have been conventionally implemented are pure gold ( Au) and the outer surface of the other lead portion 7 is surface-treated with Au or tin (Sn). In the case of the combination of Au, thermocompression bonding of Au and Au is performed, and the combination of Au and Sn is formed. In this case, Au-Sn eutectic bond is formed.

When forming the bumps 5, first, the barrier metal 4 is deposited on the electrodes 2. At this time, a significant stress acts on the wafer of the LSI chip 1 and the gate is thinned for high integration. The oxide film and the silicon base may be damaged, and the process for forming the bumps 5 is as follows: photolithography step-plating step-plating resist removal step-barrier metal etching photolithography step-photolithography resist removal. Since there are many steps and many steps, the period from the completion of the LSI chip wafer to the completion of the TAB package is long, and there is a problem in productivity.

Known examples of the means for solving these problems include:
A transfer bump method is provided. As shown in FIG. 4, the heat-resistant glass plate 10 has an upper surface on which a plating mask portion 11 having an opening corresponding to a chip electrode is formed, and a conductive layer material 12 serving as a conductive path during electrolytic plating. The bumps 13 are deposited on the film carrier by electrolytic plating, aligned with the leads of the film carrier, heated and pressed to transfer the bumps 13 to the leads.
At the time of mounting, the transfer bump 13 is bonded to the chip electrode of the LSI in the same manner as described above, and the bump forming process is slightly different from the conventional bump (wafer bump) method described at the beginning. Although it becomes complicated, there is an advantage that a barrier metal is unnecessary and there is no restriction on bonding.

[0009]

When bonding the lead and the electrode through the bump formed as described above, specifically, a bonding tool must be used. That is, when a bonding tool that has been heated to a predetermined temperature is uniformly pressed from above the leads of the film carrier at a constant pressure, as described above, Au-Su eutectic bonding or Au / Au thermocompression bonding is performed. However, if pressure and heating become non-uniform in this process, cracks will occur in the silicon base located under the electrodes of the LSI chip. Therefore, the bumps are required to have a high degree of uniformity in height, and for example, the uniformity of bumps of the LSI chip electrode is preferably ± 0.5 μm or less.

Further, the hardness of the material of the bump is important at the time of pressurizing at the time of bonding, and the softer the hardness of the bump itself is, the more the reliability of the bonding is improved. It is necessary to control the precipitated crystals while reducing the amount of time. For example, when the chip-side electrode is aluminum (Al), a bump having a low Vickers hardness of 40 to 60 Hv is desirable to prevent the cracks. In order to meet the requirement, the conditions for bump deposition by micro-part plating of pure gold are usually 1 A / d
The current density of m ² or less is raised to about 15 to 20 μm. However, under this condition, it takes too much time to form a predetermined bump. Of course, as a means for shortening the deposition time, the current density is set to 200 to 400 A / dm ²
Although it can be processed for a short time by pulling it up to the maximum, the plating thickness and shape can be affected by even the slightest fluctuations in the plating conditions. I couldn't do it.

The object of the present invention is to reduce the manufacturing cost by forming the bumps in a short time even if the shape accuracy of the bumps is relatively rough, and to maintain the bonding accuracy equal to or higher than that of the conventional one. To provide a tape automated bonding method using solder bumps.

[0012]

SUMMARY OF THE INVENTION In the present invention, a solder that has been conventionally said to be unusable is used as a material for bumps, and solder bumps for joining the leads of the TAB to the LSI chip are used. A copper oxide film or a solder resist film is formed around the solder bumps in order to limit the solder leak property of the solder bumps and prevent corrosion of the copper foil pattern.

[0013]

In the present invention, since the bumps are formed by solder, the hardness is significantly lower than that of pure gold, and in the chip mounting process, it is possible to bond under pressure and heating conditions lower than before, and the bonding reliability is high. Since there is no risk of damaging the silicon base as well as leakage when solder is melted, it is possible to prevent the solder from spreading and to perform bonding while controlling the amount of solder. The dimensional accuracy of bumps can be afforded, and the current density during bump deposition can be greatly increased to shorten the processing time.

[0014]

Embodiments of the present invention will be described below with reference to FIGS.

First, a photoresist 22 for making a mask for solder plating is applied to the end of each lead 21 of the film carrier, and then an opening 2 for forming a bump is formed there.
3 is formed by a photolithography process (see FIG. 5).
Then, after the solder bumps 24 are deposited and formed in the openings 23 by the minute partial electrolytic plating means, the photoresist 22 is removed (see FIG. 6), and benzo triazole (Benzo Tri Azol) is formed in the next step. When immersed in the liquid, only copper (Cu) in the lead 21 portion is selectively oxidized, and an extremely thin copper oxide film 25 is formed on the surface of the lead 21 as shown in FIG.

On the other hand, when processing the electrode 27 side of the LSI chip 26, conventionally only aluminum (Al) was vapor-deposited. However, in order to enhance the bondability with the solder bump 24, tin, which has a strong affinity with solder, is used. (Sn) is also vapor-deposited on the upper surface of the electrode 27 to form an alloy layer 28 of Al and Sn,
Moreover, the uppermost layer of the electrode 27 is the Sn film 29, and finally the protective film (passivation) 30 is formed.

When the LSI chip 26 is bonded to the leads 21 via the solder bumps 24, the leads 21 are connected to each other.
When heated to 40 to 300 ° C., the solder bumps 24 melt. Here, as is well known, the molten metal is deformed into a sphere (wet back) in order to minimize the surface area due to its property.

The volume V of the sphere at this time is given by the following equation, where the radius is r.

V = 4/3 · πr ³ (1) When the specific gravity of the solder is ρ, the weight W of the solder bump 24 is W.
Is obtained by the following formula.

W = 4/3 · πr ³ · ρ (2) On the other hand, the opening 2 of the solder bump resist film in FIG.
When the opening area of 3 is S and the thickness of the formed solder bump is h, the weight W of the solder bump 24 formed by plating can be expressed by the following formula.

W = Shρ (3) Here, since the above equation (2) and equation (3) are equal, the radius r of the wet-back solder obtained from both equations is as follows.

R = (3Sh / 4π) ^1/3 (4) Therefore, the thickness (height) H of the solder bump which is wet back
Is the diameter of the sphere. H = 2r (5) That is, the height h of the solder bump 24 shown in FIG.
When joining with the SI chip, only the 1/3 power is effective.

This is because the solder bump 24 in FIG.
This is the same as the fact that the accuracy of the height dimension of M is significantly eased, and when forming the solder bumps 24 in the state of FIG.
Since it is not necessary to perform highly accurate control in the electrolytic plating treatment stage, it is possible to increase the current density and perform the treatment for a short time. As a result, even if there are variations in the thickness dimension between a large number of bumps, it is
Since it only affects the third power, it is not a problem for practical use.

On the other hand, the hardness of the solder bumps 24 is much lower than the hardness of pure gold bumps (8-15 Hv in Vickers hardness), and is even lower when the solder is melted. There are no accidents such as the occurrence of cracks due to pressure.

Further, the problem due to the use of solder is that the solder may spread along the surface of the lead 21 at the time of melting, but in the embodiment of the present invention, the solder leak property is regulated on the surface of the lead 21. Since the oxide film 25 is formed, the wet-back solder 24 remains spherical (see FIG. 9). On the other hand, as shown in FIG.
On the electrode surface of the chip 26, tin (S
Since the film 29 of n) is exposed and the periphery thereof is surrounded by the passivation 30 to regulate the leak spread of the melted solder, the amount of solder that is truly necessary for joining can be controlled. .

Next, another embodiment for controlling the solder leak property will be described with reference to FIG.

Instead of forming the metal oxide film for controlling the solder leak property by the above-mentioned TAB process, the entire surface of the lead 21 is previously plated with nickel (Ni), and as shown in FIG. Then, a photoresist is applied to the substrate, a solder bump 24 is formed by plating through a photolithography process, and then the photoresist is removed. As a result, the Ni plating layer 31 is formed on the surface of the lead 21, and the solder bumps 24 are deposited on the Ni plating layer 31 by solder plating.

When the photoresist is removed, the Ni plating layer 31 is exposed directly on the surface, so that the Ni oxide film 3 is formed.
2 is formed, and this oxide film 32 regulates the leakability of the solder. However, due to the rigidity and corrosion resistance of Ni, it is possible to increase the rigidity of the leads of the film carrier and also to provide corrosion resistance, but especially for film carriers for LSIs with an extremely large number of pins. In this case, since the lead copper foil is thinly formed, the improvement of rigidity by the Ni plating is extremely effective.

As another embodiment, the photoresist 2 is used.
The same effect can be obtained by applying a solder resist instead of 2 and hardening it, and using it as a solder plating resist.

In this case, as shown in FIG.
Since the solder resist 41 is formed on the surface of and the solder bumps 24 are also deposited and formed by the same process as described above, the solder resist 41 prevents corrosion of copper, which is the material of the lead 21.

Each of the above embodiments is applied to the process of bonding the leads of the film carrier and the electrodes of the LSI chip via bumps (referred to as inner lead bonding). However, the TAB to which the LSI chip is bonded is applied. Regarding the solder bumps of the outer leads for connecting to the electronic circuit, the bumps can be formed by the same method as the inner leads. In this case, it is necessary to bond the LSI chip and mount the outer lead on the circuit board.
Since the solder bumps on the inner leads and the solder bumps on the outer leads need to be differentiated from each other due to heat history, the silver (A
The melting temperature may be set higher than that of the other solder bump by slightly adding g). That is, the other processes can be the same as those in the above-mentioned embodiment, only by changing the composition of the plating liquid for forming the solder bumps of the inner leads and the plating liquid for forming the solder bumps of the outer leads.

[0032]

As described above, according to the present invention, L
SI chip electrodes, film carrier lead ends, etc.
In a TAB in which bumps are formed and joined via the bumps, the bumps are formed by solder, and a copper oxide film or a solder resist is used to limit solder leakability of the solder bumps and prevent corrosion of the copper foil pattern. Since the outer periphery of the bump is covered with a film, it is possible to absorb the variation in the thickness (height) of the bump and suppress the influence at the time of bonding, and to significantly improve the hardness of the bump compared to that of the conventional one. Since it can be lowered, there is no risk of cracks in the chip base or the like at the time of joining, and further, since the solder is joined by melting,
There are numerous advantages such as a remarkable improvement in the reliability of bonding, an easy bonding process, an improved production yield, and a low bump forming cost.

[Brief description of drawings]

FIG. 1 is an explanatory sectional view showing a conventional bump.

FIG. 2 is an explanatory sectional view showing another example of a conventional bump.

FIG. 3 is an explanatory cross-sectional view showing conventional bonding by bumps.

FIG. 4 is an explanatory sectional view showing a known transfer bump.

FIG. 5 is an explanatory perspective view showing a state in which bump positions are formed in the process of forming solder bumps in the embodiment of the present invention.

FIG. 6 is an explanatory perspective view showing a state in which solder bumps are deposited.

FIG. 7 is an explanatory sectional view showing a state where an oxide film is formed.

FIG. 8 is an explanatory perspective view showing a state in which a solder bump of the present invention is formed on an LSI chip.

FIG. 9 is an explanatory perspective view showing a state where solder bumps are melted.

FIG. 10 is an explanatory perspective view showing a state in which electrodes and leads are joined via solder bumps.

FIG. 11 is an explanatory perspective view showing a state where a nickel oxide film is formed on a lead.

FIG. 12 is an explanatory perspective view showing a state in which a lead is formed with a leak resisting portion formed of a solder resist.

[Procedure amendment]

[Submission date] December 2, 1991

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 7

[Correction method] Change

[Correction content]

[Figure 7]

Claims (1)

[Claims] 1. A bump for bonding is formed by soldering on each lead end of a film carrier or each electrode of an integrated circuit element, and a copper oxide film or a solder resist film is formed in a peripheral region where only the bump is left. A tape automated bonding method using solder bumps, characterized in that the solder leak property is regulated in a region other than the joint portion, and the solder bumps are melt-joined to collectively join the electrodes and the leads.