JPH06338130A - Clock synchronous circuit - Google Patents

Abstract

PURPOSE:To select a clock only by the rise of a reference clock (REF) as the reference of the selected clock without depending upon the width of the REF, and to select only one phase out of polyphase clocks. CONSTITUTION:In a polyphase clock generating circuit 1, a reference clock stable in frequency is delayed by a delay element, etc., and constant phase difference is formed mutually, and polyphase clocks CK1-CKn, in which the reference clock is divided into N, are prepared, and transmitted over a clock selector circuit 2. That is, the polyphase clock generating circuit 1 generating the polyphase clocks having mutually constant phase difference by delaying the reference clock at a regular interval by the delay element, etc., is provided. Flip-flops and gates in the same number as the number of polyphase clock phase are used in clocks synchronized with a regenerative synchronizing signal from the polyphase clocks, thus instantaneously selecting the clocks by a simple circuit constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock synchronizing circuit for synchronizing a clock with an asynchronous signal, and more particularly to a circuit for selecting a clock synchronized with a reproduced signal from among multiphase clocks. The present invention relates to a clock synchronization circuit in which only one phase is selected from multiphase clocks to improve the duty ratio. For example,
It is applied to a clock synchronizing circuit in a recording / reproducing apparatus such as a video tape recorder.

[0002]

2. Description of the Related Art In a recording / reproducing apparatus such as a VTR (Video Tape Recorder), a reproduction signal contains a time axis error called jitter due to fluctuations in relative speed between a recording medium and a reproducing head, and the reproduction is performed as it is. When this is performed, the reproduced image is subject to horizontal shake or the like. Therefore, the conventional recording / reproducing apparatus is provided with, for example, a time axis correction circuit using a clock selection circuit as described below. FIG. 4 is a block diagram of a conventional clock synchronization circuit. In the figure, 21 is a multi-phase clock generation circuit, 22 is a synchronization detection circuit, 23 is a condition setting circuit,
Reference numeral 24 is a CLR (clear) pulse generation circuit, and 25 is a clock selection circuit. A multi-phase clock generation circuit 21 is supplied with a frequency-stable reference clock, and a clock selection circuit 25 is supplied with REF (reference clock) and CLR (clear signal) generated from a reproduction synchronization signal. At this time, REF has almost the same width as the interphase interval of the multi-phase clock, and CLR has a pulse width similar to that of REF.
It is slightly ahead of REF in phase. The multi-phase clock generation circuit 21 delays the reference clock by a predetermined interval to generate multi-phase clocks having a constant phase difference with each other, and supplies the multi-phase clocks to the clock selection circuit 25. The clock selection circuit 25 selects a clock within the pulse width of REF from the input multiphase clocks.

FIG. 5 is a block diagram of the clock selection circuit in FIG. 4, in which 31-1 to 31-n are inverter circuits and 3
2-1 to 32-n are JK flip-flops (FF), 33
-1 to 33-n are AND circuits, and 34 is an OR circuit. The multi-phase clocks CK1 to CKn, REF, and CLR are JK
The flip-flops J-KFF1 to J-KFFn are supplied to the CK input, J input, and RESET input, and first, all flip-flops are initialized by CLR. After the initialization, REF is input to the J input, and the output Q becomes Hi only in the flip-flop having the rising edge of the clock within the pulse period of the REF. Further, by ANDing the Q output of each flip-flop and the multiphase clock, and taking the OR of all the AND outputs, REF
The clock having the rising phase closest to the rising phase of is selected. The selected clock is used as the memory write clock of the time axis correction circuit, and the time axis is corrected by using the reference clock for memory reading.

FIGS. 6 (a) to 6 (i) are timing charts of signals of respective parts in FIG. 5, FIG. 6 (a) is CK1, FIG. 6 (b) is CK2, FIG. 6 (c) is CK3, and FIG. 6 (d). Is CK
4, Figure (e) is CK5, Figure (f) is CKn, Figure (g) is REF, Figure (h) is CLR, Figure (i) is CLR1, Figure (j) is CLR2, and Figure (k) is CLR3. , Figure (m) is C
LR4, FIG. (N) shows CLR5, and FIG. (P) shows SCK signals.

[0005]

As described above, in the conventional clock synchronizing circuit, when the width D of the signal REF which is the reference of the selected clock is a, the interval between the multiphase clock phases is a <D < Set to 2a and select 1 from the multiphase clocks.
Select only the phase. However, it is difficult to maintain a <D <2a due to variations in delay elements, circuit elements, etc., and in some cases D <a, and a clock cannot be selected. In order to get out of this state, it is necessary to set the condition for setting the REF width D to a <D <na (n is an integer) and select one or more phase clocks. Therefore, there is a drawback that the duty ratio of the selected clock is bad and is not always constant. If this clock is used for an element whose duty ratio is strictly controlled (for example, some A / D converters), there is a problem that it may cause a malfunction.

The present invention has been made in view of such circumstances, and does not depend on the width of the reference clock (REF) which is the reference of the selected clock, and the clock is selected only by the rising edge of REF. Moreover, it is an object of the present invention to provide a clock synchronization circuit in which a circuit that selects only one phase of a multi-phase clock is simply configured by only a flip-flop and a gate.

[0007]

In order to achieve the above object, the present invention provides a clock synchronizing circuit for synchronizing a clock with a reproduced signal, wherein a plurality of clocks having a constant phase difference from a reference clock. A multi-phase clock generating means for generating a multi-phase clock, and the clock is selected only by the rising edge of the reference clock, and only one phase is selected from the multi-phase clocks so that the phase of the reproduced signal is almost always matched. And a clock selecting means for performing the operation.

[0008]

With the rising edge of REF created from the reproduced signal, all the multiphase clocks having a constant phase difference created by a delay element or the like are hit, and which clock is R
Hi period or Lo for the rising edge of EF
It is determined whether the period is w. Further, only one clock phase that is closest in phase to the rising edge of REF is selected from the clocks determined to be in the Hi period. As a result, the duty ratio of the selected clock can be kept constant.

[0009]

Embodiments will be described below with reference to the drawings. FIG. 1 is a block diagram for explaining an embodiment of a clock synchronization circuit according to the present invention, in which 1 is a multi-phase clock generation circuit, 2 is a clock selection circuit, 3 is a synchronization detection circuit,
Reference numeral 4 is a CLR (clear) pulse generation circuit. In the multi-phase clock generation circuit 1, the frequency-stable reference clock is delayed by a delay element or the like to provide a constant phase difference, and the reference clock is divided into N multi-phase clocks CK1 to C
Kn is created and supplied to the clock selection circuit 2. That is, by delaying the reference clock by a constant interval with a delay element or the like, a multi-phase clock generation circuit that generates multi-phase clocks having a constant phase difference with each other is provided. By using the same number of flip-flops and gates as the number of clocks, the clocks can be instantly selected with a simple circuit configuration.

FIG. 2 is a block diagram of the clock selection circuit in FIG. 1, in which 11-1 to 11-n are AND circuits and 12-1.
~ 12-n are flip-flops (FF), 13-1 to 13-n
Is an AND circuit, and 14 is an OR circuit. The same number of D flip-flops, OR gates, and ANDs as the number of phases of the multiphase clock
It is composed of a gate. REF synchronized with the input multiphase clocks CK1 to CKn and the reproduction signal is supplied to the D input and the CK input of the D flip-flops FF1 to FFn, respectively. In addition, the CLR which is synchronized with the reproduction signal and slightly advances in phase from REF and has a minute pulse width,
AND with CLRn to obtain D flip-flop FFn
-1 is supplied to the reset input.

First, D flip-flops FF1 to FFn
Are initialized by CLR. RE for FF1 to FFn
Since CK1 to CKn are hit by F, it is determined whether CK1 to CKn are in the Hi period or the Low period with respect to the rising edge of REF. If it is in the Hi period, a part of CLR1 to CLRn becomes Low, and if it is in the Low period, it becomes Hi in reverse, and if the duty ratio of the input clock is 1: 1, CLR1 to CLRn.
The Hi, Low ratio of is also about 1: 1. At this time, CL
Since the AND of R and CLRn is supplied to the reset input of FFn-1, the state of FFn-1 is determined by the state of FFn (CLRn becomes Low if the clock is in the Hi period with respect to the rising edge of REF). , FF
Initialize n-1.

3 (a) to 3 (p) are timing charts of the signals of the respective parts in FIG. 2. FIG. 3 (a) is CK1, FIG. 3 (b) is CK2, FIG. 3 (c) is CK3, and FIG. Is CK
4, Figure (e) is CK5, Figure (f) is CKn, Figure (g) is REF, Figure (h) is CLR, Figure (i) is CLR1, Figure (j) is CLR2, and Figure (k) is CLR3. , Figure (m) is C
LR4, FIG. (N) shows CLR5, and FIG. (P) shows SCK signals.

FF1 to FFn are initialized by CLR and CK1 to CKn are tapped by REF. At this time, F
FF3, FF to which CK3, CK2, ... Of phase (including CK4) leading from CK4 with respect to F4 are input
2, reset outputs CLR3, CLR2, ... are Lo
The reset outputs CLR5, CL of FF5, FF6, ... To which CK5, CK6, ...
R6, ... Become Hi (the Hi / Low ratio of the reset output is 1: 1 if the duty ratio of the input clock is 1: 1). The state of FFn-1 is the reset output C of FFn.
Since it depends on LRn, FF3, FF2, ... Are initialized. Regarding the FF4, since the reset output CLR5 of the FF5 is in the Hi state, initialization is not performed at this point, and this state is maintained until the next CLR is input. A clock synchronized with REF, that is, a reproduction signal, is obtained by ANDing the set outputs GATE1 to GATEn of FF1 to FFn and the respective multiphase clocks CK1 to CKn that perform the above-described operation, and further taking the OR of all AND outputs. Select only one phase. In the example of the timing chart of FIG. 3, only CK4 is selected.

[0014]

As is apparent from the above description, the present invention has the following effects. That is, since the clock can be selected only by the rising edge of REF without depending on the pulse width of REF created from the reproduced signal, R
It is not necessary to set the pulse width of EF. In addition, since only one phase is selected from the multi-phase clocks, the duty ratio of the selected clock can always be kept constant, and even if the selected clock is used for an element that is strict in duty ratio management, no problem will occur. It is possible to use it stably.

[Brief description of drawings]

FIG. 1 is a configuration diagram for explaining an embodiment of a clock synchronization circuit according to the present invention.

FIG. 2 is a configuration diagram of a clock selection circuit in FIG.

FIG. 3 is a timing chart of signals of respective parts in FIG.

FIG. 4 is a configuration diagram of a conventional clock synchronization circuit.

5 is a configuration diagram of a clock selection circuit in FIG.

FIG. 6 is a timing chart of signals of respective parts in FIG.

[Explanation of Codes] 1 ... Multi-phase clock generation circuit, 2 ... Clock selection circuit, 3
... Synchronous detection circuit, 4 ... CLR (clear) pulse generation circuit.

Claims (1)

[Claims] 1. A clock synchronization circuit for synchronizing a clock with a reproduction signal, comprising: a multi-phase clock generation means for generating a multi-phase clock composed of a plurality of clocks having a constant phase difference from a reference clock; A clock synchronizing circuit, characterized in that the clock is selected only by the rising edge of the reference clock, and a clock selecting means for selecting only one phase of the multiphase clocks whose phase almost always matches the reproduction signal. .