JPH06337793A - Interruption control system - Google Patents

Abstract

PURPOSE:To use a program error detecting circuit without reconstituting it even when a case wherein a program error is detected is changed owing to specification alterations of a computer. CONSTITUTION:When the system is started up, a specific data set instruction M is executed and mask data am set in a register 5. Consequently, AND gates 9-0-9-11 in a program error interruption inhibiting circuit 9 permit or inhibit program error detection signals E0-E11 to be outputted or from being outputted from the program error detecting circuit 4 according to the logical states of bits 0-11 of the register 5 and the program error detection signal of a factor designated by the register 5 is made ineffective to inhibits an interruption signal 14 from being generated by an interruption processor 12 owing to the detection of the factor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt control system in a computer equipped with a program error detection circuit for detecting a plurality of program errors.

[0002]

2. Description of the Related Art Generally, in a computer, when an instruction that cannot be executed, such as an undefined instruction, is to be processed, this is detected as a program error and interrupt processing is performed. This detection is performed by hardware called a program error detection circuit.

Especially, VLIW (Very Long Instruction Wo)
A computer to which the architecture of the (rd) type parallel processing system (VLIW system) is applied (hereinafter, referred to as a VLIW system computer) often detects a program error by hardware as compared with other sequential execution system computers.

FIG. 4 shows an example of the structure of an instruction word of the VLIW system. In the example of FIG. 4, one instruction word is in fields F1 to F.
It is divided into four fields of 4 and each field F1
Instructions I1 to I4 are set in F4. Basically, these four instructions I1 to I4 are processed simultaneously.

Now, in the VLIW type computer to which the instruction word having the structure shown in FIG. 4 is applied, as shown in FIG. 5, each field F1 to F1 is used for the purpose of reducing the amount of hardware and improving the utilization rate of hardware. The instructions that can be specified in F4 are often limited.

In the example of FIG. 5, only the addition / subtraction instruction, the data set instruction and the LD (load) instruction can be designated in the field F1, and only the addition / subtraction instruction, the data set instruction and the shift instruction can be designated in the field F2. Further, only an addition / subtraction instruction, a data set instruction and an ST (store) instruction can be designated in the field F3, and only an addition / subtraction instruction, a data set instruction and a branch instruction can be designated in the field F4.

The program error detection circuit is created in consideration of the limitation (constraint) of the instructions that can be specified in each field, and its configuration is complicated. However, adding the amount of hardware of VLIW type computer,
In order to create a high-end model with less restrictions on the instructions that can be specified in each field, a complicated program error detection circuit must be newly created (redesigned) correspondingly. Also, compatibility is lost due to changes in the hardware functions. Furthermore, higher-level models cannot develop software for lower-level device types.

[0008]

As described above, in the conventional computer, a complicated program error detection circuit must be newly re-created when the case where a program error occurs due to a change in hardware specifications. There was a problem that the compatibility of the hardware was lost.

The present invention has been made in view of the above circumstances, and an object thereof is to use a program error detection circuit having the same configuration as that before the specification change when the case where the program error is detected changes due to the specification change of the computer. However, it is possible to prevent the program error interrupt from being generated due to the fact that the detection of the program error is not necessary due to the specification change, the program error detection circuit can be standardized regardless of the specification change of the computer, and the hardware It is to provide an interrupt control method capable of maintaining the compatibility of software.

[0010]

SUMMARY OF THE INVENTION The present invention is a program error interrupt inhibiting means for inhibiting a program error interrupt due to an arbitrary factor among a plurality of program error factors detected by a program error detecting circuit of a computer, and this program. Program error interrupt prohibition means is provided to specify the program error interrupt prohibition specifying means for specifying the program error factor that is the target of program error interrupt prohibition. It is characterized in that the program error interrupt is prohibited by the designation of the program error interrupt prohibition designating means.

The present invention further includes a prohibition bit holding means for holding a prohibition bit for designating the prohibition of the program error interrupt to the program error interrupt prohibition means for each program error factor detected by the program error detection circuit. Is provided in the program error interrupt prohibition designating means, and the prohibition bit holding means is operated according to a specific data set instruction executed when the computer system is started up.

[0012]

In the above structure, a specific data set instruction is executed when the system is started up. This instruction has a mask field for setting / resetting the inhibit bit for each program error cause (detected by the program error detection circuit) retained in the inhibit bit retaining means of the program error interrupt inhibit designating means, and the same instruction Is executed, each inhibit bit is set / reset.

The program error interrupt inhibiting means invalidates the program error according to the state of the corresponding inhibit bit held in the inhibit bit holding means for each program error cause detected by the program error detection circuit, Disable the program error interrupt due to the program error factor.

Therefore, since the program error detection circuit having the same configuration as that before the specification change of the computer is used, even if the program error which is not necessary to be detected due to the change of the specification of the computer is detected, the above specific data set instruction is generated. By specifying the corresponding bit in the mask field of
By setting the prohibition bit of the prohibition bit holding means corresponding to the program error cause to the prohibition designated state,
The program error interrupt due to the program error factor can be prohibited, and the program error detection circuit can be shared.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of essential parts showing one embodiment of a VLIW type computer to which the present invention is applied. It is assumed that the computer of FIG. 1 uses the command word having the structure shown in FIG.

In FIG. 1, reference numeral 1 is a memory for storing various programs including instruction words, data, and the like. At a predetermined address of the memory 1, a specific data set instruction M is stored which is executed when the system is started up and sets data in the register 5 described later. The specific data set instruction M is included in the boot program. Although this boot program is stored in the ROM in the actual machine, it is assumed here that it is stored in the memory 1 for simplification of the description.

Reference numeral 2 is a memory control device. Unless there is a branch request, the memory control device 2 sequentially fetches instruction words from the memory 1 while incrementing the memory address. Further, when a branch request is issued, the memory control device 2 causes the memory 1 indicated by a branch address (branch destination address) given from an instruction address generation device 15 described later.
The fetching of the instruction word is started from the memory address of.

Reference numeral 3 is an instruction decoding device for decoding the instruction word supplied from the memory 1 for each of the fields F1 to F4, and 4 is a program error detection circuit. The program error detection circuit 4 is hardware that detects a predetermined program error based on the decode signals 31 to 34 for each of the fields F1 to F4 output from the instruction decoding device 3.

The program error detection circuit 4 in the present embodiment is developed on the assumption that the instruction constraints that can be specified in each field F1 to F4 of the instruction word are as shown in FIG. Yes, 12 types of program errors are detected. Therefore, the program error detection signals output from the program error detection circuit 4 include the program error detection signals E0 to E11.
There are 12 types. These signals E0 to E11 and the field F
FIG. 2 shows the correspondence relationship with the instructions designated by 1 to F4 that cause a program error.

As shown in FIG. 2, the signal E0 is a program error in which a shift instruction is designated in the field F1 of the instruction word, the signal E1 is a program error in which a ST (store) instruction is designated in the same field F1, and the signal E2 is The program error in which the branch instruction is designated in the same field F1 is shown respectively.

Next, the signal E3 is an instruction word field F2.
Indicates a program error in which an ST instruction is designated, a signal E4 indicates a program error in which a branch instruction is designated in the same field F2, and a signal E5 indicates a program error in which an LD (load) instruction is designated in the same field F2.

Next, the signal E6 is a command word field F3.
Indicates a program error in which a branch instruction is designated, a signal E7 indicates a program error in which the LD instruction is designated in the same field F3, and a signal E8 indicates a program error in which a shift instruction is designated in the same field F3.

Next, the signal E9 is the command word field F4.
The signal E10 indicates a program error in which the shift instruction is designated in the field F4, and the signal E11 indicates a program error in which the ST instruction is designated in the field F4.

Reference numeral 5 is a 12-bit register. This register 5 has the above-mentioned program error detection signals E0 to E11.
The bit 0 to 11 for inhibiting the program error interrupt caused by is held. Each bit 0 to 11 of the register 5 can be set / reset by the above specific data set instruction M.

Reference numeral 6 is a control signal for permitting (enabling) the data set to the register 5. The control signal 6 becomes true when the instruction decoding device 3 decodes the data set instruction M.

Reference numeral 7 is a data line for supplying the data set in the register 5 from the instruction decoding device 3. The data supply through the data line 7 is performed when the instruction decoding device 3 decodes the specific data set instruction M.

Reference numerals 8-0 to 8-11 denote inverters for inverting the states of the bits (prohibited bits) 0 to 11 of the register 5, and reference numeral 9 denotes an output state of the inverters 8-0 to 8-11.
This is a program error interrupt inhibit circuit for invalidating the program error detection signals E0 to E11 from the program error detection circuit 4. The program error interrupt prohibition circuit 9 is composed of twelve AND gates 9-0 to 9-11. AND gate 9-i (i = 0 to 11)
The program error detection signal Ei from the program error detection circuit 4 and the output signal of the inverter 8-i are input, and when the output signal of the inverter 8-i is "0", the output of the program error detection signal Ei is prohibited.

Reference numeral 10 is an OR gate which takes the logical sum of the outputs of the AND gates 9-0 to 9-11. The output signal of the OR gate 10 is a control signal 11 indicating a program error detection.
Used as.

An interrupt processing unit 12 receives a control signal 11 indicating a program error detection from the OR gate 10 and a control signal 13 indicating an error other than the program error, and generates an interrupt signal 14 indicating that an interrupt has occurred. Reference numeral 15 is an instruction address generator. The instruction address generator 15 includes an interrupt signal 14 from the interrupt processor 12 and a control signal 16 from the instruction decoder 3.
Outputs a branch request and a branch address to the memory controller 2. The control signal 16 becomes true when the instruction decoding device 3 decodes the branch instruction.

Next, the operation of the configuration shown in FIG. 1 will be described. First, the specific data set instruction M stored in the memory 1 is executed. The data set instruction M is included in the boot program and is executed once when the system is started up. The instruction format of the data set instruction M applied in this embodiment is shown in FIG.

Here, the data set instruction M is bit 0.
32 bits of 31 to 31, 8 bits of 0 to 7 are OP (operation) codes designating a data set, and 12 bits of 20 to 31 are data set in the register 5 (hereinafter referred to as mask data). It is called). The destination designation field for designating the data set destination (register 5) is omitted.

When the system is started up, the memory 1 to V including the specific data set instruction M of the format shown in FIG.
It is assumed that the LIW method instruction word is fetched by the memory control device 2, supplied to the instruction decoding device 3, and decoded by the device 3. In this case, the instruction decoding device 3 sets the control signal 6 to true according to the data set instruction M, and at the same time, sets the 12-bit mask (bits 20 to 31 of the data set instruction M set on the data line 7 ( MASK) data is output.

The control signal 6 becomes a latch enable signal (EN) for the register 5, and accordingly, 12 is supplied from the instruction decoding device 3 to the register 5 via the data line 7.
The bit mask data is set in the register 5. The 12-bit mask data set in the register 5, that is, each bit (inhibit bit) of bits 0 to 11 of the register 5 is "1" to inhibit the program error interrupt caused by the program error detection signals E0 to E11. specify.

After that, the system started up, and eventually,
It is assumed that the instruction word having the structure shown in FIG. 4 including the instruction that causes the program error to be detected by the program error detection circuit 4 is fetched from the memory 1 by the memory control device 2 and supplied to the instruction decoding device 3.

The instruction decoding device 3 is a memory control device 2.
The instruction word supplied from each of the fields F1 to F4 is decoded, and the decoded signal 31
~ 34 is output.

The program error detection circuit 4 receives the decode signals 31 to 34 for the respective fields F1 to F4 from the instruction decoding device 3, and receives the fields F1 to F4.
A predetermined program error is detected for each. That is, the program error detection circuit 4 uses, for example, the field F
If it is 1, it is detected whether or not the decode signal 31 indicates a shift instruction, an ST instruction, or a branch instruction. Then, the program error detection circuit 4 uses the decode signal 31
Indicates a shift instruction, the program error detection signal E0 is set to true ("1"), and if ST instruction is also set, the program error detection signal E1 is set to true ("1") and the branch instruction is also set. , The program error detection signal E2 is set to true ("1") (see FIG. 2).

On the other hand, if the decode signal 31 indicates an addition / subtraction instruction, a data set instruction, or an LD instruction that can be specified in the field F1, the program error detection circuit 4 causes the program error detection signal E0.
Neither of ~ E2 is true.

Program error detection signals E0 to E11 from the program error detection circuit 4 correspond to AND gates 9-0 to 9-1 in the program error interrupt prohibition circuit 9.
Supplied to one input of 1. This AND gate 9-0 ~
The outputs of the inverters 8-0 to 8-11 are supplied to the other input of 9-11. The outputs of the inverters 8-0 to 8-11 are obtained by inverting the logical states of the bits (prohibited bits) 0 to 11 of the register 5.

The AND gate 9-i (i = 0 to 11) outputs "0" when the output of the inverter 8-i is "1", that is, the bit i of the register 5 indicates program error interrupt permission.
In the reset state, the program error detection signal Ei is output as it is. On the other hand, the inverter 8-i
When the output of the above is "0", that is, when the bit i of the register 5 is in the set state of "1" indicating the inhibition of the program error interrupt, the AND gate 9-i inhibits the output of the program error detection signal Ei.

Therefore, even if the program error detection circuit 4 detects a program error which is the target of the program error detection signal Ei and makes the signal Ei true, the bit (prohibit bit) i of the register 5 is set. If is set, the same signal Ei is sent to AND gate 9-i.
Is forced to false by. This is because the program error detection circuit 4 is recreated and the program error detection signal E
It is equivalent to removing the program error detection function targeted for i output.

In this case, the program error detection signal Ei
If all other program error detection signals are not true, the outputs of AND gates 9-0 to 9-11 are all "0".
Since it is (false), the control signal 11 which is the output of the OR gate 10 is also "0" (false), and the output of the interrupt signal 14 from the interrupt processing device 12 according to the program error detection is prohibited.

From the above, the hardware specifications of the computer shown in FIG. 1 are changed, for example, a shifter is added corresponding to the field F1 of the instruction word, and an instruction which can be designated in the field F1 is shown in FIG. When a shift instruction is newly added in addition to the addition / subtraction instruction, the data set instruction, and the LD instruction shown, the following mask data is set in the register 5 so that the program error detection circuit 4 does not need to be recreated. However, it is possible to prevent the program error interrupt from being generated because the shift instruction is specified in the field F1.

That is, when the shift instruction is designated in the field F1, the program error detection circuit 4 outputs the program error detection signal E0 as described above (assuming that the program error has not been recreated according to the change in the hardware specifications). To be true. Therefore, in order to prohibit the program error interrupt according to the program error detection signal E0, bit 0 of the register 5 may be set to "1".

To set bit 0 of register 5 to "1", bits 20 to 31 of data set instruction M are set.
12-bit mask data in which the first bit (the bit corresponding to bit 20) is “1” is set, that is, the bit pattern is “1 ×× ... ××” (× is “1” or “0”). ), A data set instruction M having 12-bit mask data is prepared, and the instruction M may be executed at system startup.

On the other hand, the bit i of the register 5 corresponding to the error detected by the program error detection circuit 4, that is, the program error detection signal Ei whose logic state is true.
When is reset, AND gate 9-i
The program error detection signal Ei is output as it is. In this case, the control signal 1 output from the OR gate 10
1 becomes "1" (true).

When the control signal 11 indicating the detection of the program error is "1", the interrupt processing unit 12 detects the interrupt and notifies the instruction address generating unit 15 of the interrupt generation by the interrupt signal 14. In response to this, the instruction address generator 15 outputs a branch request and a branch address (address of the interrupt handler of the program error) to the memory controller 2.

The memory controller 2 fetches the instruction placed in the program error interrupt handler from the memory 1 and supplies it to the instruction decoder 3. In this way
Program error interrupt processing is performed.

As is apparent from the above description, in the computer having the configuration shown in FIG. 1, a specific one of the program error detection signals E0 to E11 corresponding to the 12 types of program error factors detected by the program error detection circuit 4 is selected. Only the program error detection signal which is made true by the detection of the program error factor is masked through the register 5 by the mask (MASK) data in the specific data set instruction M executed at the time of system startup, thereby enabling the program error interrupt. / You can control the prohibition.

Therefore, when the amount of hardware of the computer of FIG. 1 is added and the upper model having less restrictions on the instructions that can be specified in each field F1 to F4 of the instruction word is made, the program error detection circuit 4 is remade. Even without,
Only by changing the mask data of the data set instruction M, it is possible to prevent the inconvenience that a program error interrupt occurs due to a program error that is no longer required to be detected.

In the above embodiment, the case where the register 5 for designating the enable / disable of the program error interrupt for each program error factor to the program error interrupt prohibition circuit 9 is operated by the data set instruction M has been described. It is not limited to this. For example, instead of the register 5, a DIP switch may be used and the mask data may be set by the user's operation. In this case, there is a risk of causing an erroneous operation, but the operation may be performed only when the hardware specifications of the computer have changed. Further, it is needless to say that the structure of the command word and the constraint of the command for each field are not limited to those in the above embodiment.

[0051]

As described above in detail, according to the present invention,
For each program error factor detected by the program error detection circuit, the program error interrupt due to that factor is configured to be enabled / disabled by, for example, the specification at system startup.
It is possible to prohibit the occurrence of program error interrupts due to program error factors that are no longer required to be detected because of changes in computer specifications.

Therefore, even if some of the plurality of program error factors to be detected by the program error detection circuit are not required to be detected due to the specification change of the computer, the program error detection circuit is used as it is. Therefore, the program error detection circuit can be shared, and the compatibility of the hardware can be maintained.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part showing an embodiment of a VLIW type computer to which the present invention is applied.

FIG. 2 is a diagram for explaining a function of a program error detection circuit 4 in FIG. 1 by a correspondence relationship between an instruction which becomes a program error designated in each field of an instruction word and each program error detection signal.

FIG. 3 is a diagram showing the format of a specific data set instruction M for setting mask data in a register 5 in FIG.

FIG. 4 is a diagram showing a structural example of a VLIW method instruction word.

5 is a diagram showing an example of an instruction that can be specified in each field of the instruction word shown in FIG.

[Explanation of symbols]

1 ... Memory, 2 ... Memory control device, 3 ... Instruction decoding device, 4 ... Program error detection circuit, 5 ... Register (program error interrupt prohibition designating means, prohibition bit holding means), 9 ... Program error interrupt prohibiting circuit, 9- 0
9-11 AND gate, 10 OR gate, 12 interrupt processor, 15 instruction address generator, M data set instruction (program error interrupt prohibition designating means), E0 to E11 program error detection signals.

Claims (3)

[Claims] 1. An interrupt control system in a computer having a program error detection circuit for detecting a plurality of predetermined program errors, wherein the program error detection circuit detects one of the plurality of program error factors detected by the program error detection circuit. A program error interrupt prohibition means for prohibiting a program error interrupt by an arbitrary factor, and a program error interrupt prohibition specifying means for specifying a program error factor for which a program error interrupt is prohibited by this program error interrupt prohibition means, An interrupt control system characterized in that the occurrence of a program error interrupt due to a program error factor that is no longer required to be detected due to the specification change of the computer is prohibited by the designation of the program error interrupt prohibition designation means. 2. The program error interrupt prohibition designating means for designating the prohibition of the program error interrupt to the program error interrupt prohibiting means for each of the program error factors detected by the program error detection circuit. 2. The interrupt control system according to claim 1, further comprising a prohibition bit holding means for holding the prohibition bit. 3. The interrupt control system according to claim 2, wherein the prohibition bit holding means is operated according to a specific data set instruction executed when the system of the computer is started up.