JPH06337730A - Redundancy device - Google Patents

Abstract

PURPOSE:To eliminate the need to switch a redundancy system by an operator, to simplify the constitution, and to eliminate the possibility that a wrong system is selected. CONSTITUTION:As the device is powered ON, power-ON resetting circuits 31 and 41 output low-level signals for a certain time. The output low-level signal of the circuit 41 is supplied to selectors 342 and 343. The signal D of the circuit 31 is supplied to the selectors 342 and 343, so the selector 342 outputs a low level and the selector 343 outputs a high level. Consequently, a select signal generating circuit 35 outputs a high-level signal A and supplies it to a latch 451. At this time, the signal C is supplied to the hold input of the latch 451 while held at the high level, so the high level of the D input is outputted and supplied to an OR circuit 43 and a selector 46. The selector 46 selects and outputs a 0-system clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundant device, and more particularly to a redundant device having two or more processing modules (for example, processing boards, processing units, etc.).

[0002]

2. Description of the Related Art In recent years, various configurations have been realized to improve the reliability of electronic devices. For example, in a certain communication device, a failure rate (MTBF: Mean Time Betww) of each processing module or processing board in the device.
een Failure), etc., and modules and boards with a high failure rate are configured in a redundant redundant configuration,
It is common practice to reduce the failure rate of devices and increase their reliability.

In addition, even when the target device is not allowed to be out of operation in operation, a redundant configuration of at least dual processing modules and boards is adopted. In operation, one processing module or one processing board is used for the current operation, and when a failure occurs, it is switched to any one of the processing modules or processing boards of the standby system and continuously operated. By switching in this way, the operation could be continuously performed without stopping the operation as if there was no failure in operation.

For example, FIG. 2 is a functional block diagram of an example of a conventional duplexer. In FIG. 2, this 2
In the duplication device, the package that generates the basic clock is duplicated. That is, a 0-system clock generation package 10 and a 1-system clock generation package 20 that can be inserted and removed from this device are provided. And
Both packages 10 and 20 output clocks of the same frequency and have the same circuit configuration.

The duplication of the clock generation package in this manner makes it virtually impossible to stop the operation of the device due to the interruption of the clock supply to each processing package in the device. This is to increase the reliability of the device.

The 0-system clock generation package 10
The output clock of (1) is given to the A1 input of the selector 46 via the buffer 47 built in the controlled unit 8 that can be inserted and removed from this device. The output clock of the 1-system clock generation package 20 is also given to the B1 input of the selector 46 via the buffer 48 of the controlled part 8.

At the time when power supply to the duplexer is started (initial state), the output clock of the 0-system clock generation package 10 is selected by the selector 46 as the active system, and the duplexer is selected. It is configured so as to be supplied to each processing package inside which can be inserted and removed from this device.

That is, at the control input C1 of the selector 46, the signal from the latch 451 is logic 1 (high level).
If it is a signal, the monitor control unit 7 and the controlled unit 8 are operated so that the 0-system clock given to the input A1 can be output from the output D1.

That is, in the initial state (when power is turned on),
In order to allow the 0-system clock to be used, the toggle control (single-pole double-throw) switch SW1 is set to the b side (0-system selection) in the monitor control unit 7 which can be inserted and removed from this device. By thus setting the switch SW1 to the b side, a high level (logic 1) signal is given to the NOT circuit 341 of the switching signal input circuit 34 and the input A1 of the selector 343.

Initial operation (operation at power-on) And in the initial state (at power-on), the monitor control unit 7
The power-on reset circuit 31 outputs the power-on reset signal at logic 0 (low level) for the first several hundred msec of power-on and supplies it to the NOT circuit 36.
Then, the NOT circuit 36 performs logical level inversion,
It outputs a logic 1 (high level) signal, and the selector 342,
To the control input C1 of 343.

The functions of the selectors 342 and 343 will be described with reference to FIG. Selector 34
2, 343 has a signal input A1, a signal input B1, a control input C1 and a signal output D1. Then, the control input C1
When a logic 1 (high level) signal is applied to, the signal input A1
And the signal output D1 are connected. Then, when a logic 0 (low level) signal is given to the control input C1, the signal input B1 and the signal output D1 are brought into a connected state.

Therefore, the logic 1 (high level) signal is given to the control inputs of the selectors 342 and 343 by the above power-on reset, so that the selectors 342 and 3 are provided.
43 outputs the signal provided to the signal input A1 from the signal output D1.

That is, the selector 342 outputs the logic 0 (low level) signal from the NOT circuit 341, which is applied to the A1 input, from the signal output D1 of the selector 342, and the RS flip-flop of the selection signal generation circuit 35. Is applied to the NAND circuit 351 which constitutes At the same time, the switch SW is connected to the signal input A1 of the selector 343.
The logic 1 (high level) signal from the a side of 1 is given, and the logic 1 from the signal output D1 of this selector 343 is given.
(High level) is being output. This selector 343
The logic 1 (high level) signal from the signal output D1 of
It is given to the NAND circuit 352 of the selection signal generating circuit 35 which constitutes the -S flip-flop.

The selection signal generating circuit 35, to which the signals from the selectors 342 and 343 described above are applied, constitutes an RS flip-flop, so that from the Q output, a logical 1
A (high level) signal is output and is given to the latch 451 as the selection signal A through the buffer 353 through the buffer 452 of the controlled part 8.

When a logic 0 (low level) signal is applied to the hold (HOLD) input, the latch 451 outputs the signal applied to the signal input D from the Q output. Further, at the same time when a logic 1 (high level) signal is given to the hold (HOLD) input, the signal given to the signal input D is latched and output from the Q output, and even if there is a change in the input signal, it is output from the Q output. The value of the latch output of is not changed.

Then, the hold (H
A protect signal is given to the OLD) input from an external control unit or the like. The Q output of the latch 451 is controlled by this protect signal. That is, in normal operation, a logic 0 (high level) signal is given to the hold (HOLD) input of the latch 451 as a protect signal. As a result, the latch 451 outputs the signal at the time of power-on reset applied to the D input, that is, the logic 1 (high level) signal from the Q output.

The logic 1 (high level) signal from the Q output is applied to the control input C1 of the selector 46. The selector 46 is the selector 342, 34 described above.
3 has a single function similar to that of No. 3, and specifically has the function described in FIG. Therefore, when a logic 1 (high level) signal is given to the control input C1 of the selector 46,
The clock from the 0-system clock generation package 10 given to the input A1 is output from the output D1 of the selector 46 and supplied to each required processing package.

Operation after power-on The power-on reset is, as described above, performed from the time of power-on 10
After the lapse of 0 msec, the output of the power-on reset circuit 31 changes from the logic 0 (low level) signal to the logic 1
Since it changes to a (high level) signal, the selector 342,
A logic 0 (low level) signal is applied to the control input C1 of 343. Thereby, the selectors 342 and 343
Is changed from the connection between the signal input A1 and the signal output D1 to the connection between the signal input B1 and the signal output D1.

The signal input B1 of the selector 342 is supplied with the signal from the 1-system failure detection circuit 33. Further, the signal from the 0-system failure detection circuit 32 is applied to the signal input B1 of the selector 343.

Operation in case of 0-system failure If , for example, the 0-system failure detection circuit 32 detects a failure (failure) in the 0-system clock generation package 10, a failure signal
A logic 0 (low level) signal is output and given to the signal input B1 of the selector 343.

At this time, since the logic 0 (low level) signal is given from the NOT circuit 36 to the control input C1 of the selector 343, the signal input B1 and the signal output D1 of the selector 343 are connected. Because
The logic 0 (low level) signal of the failure signal given to the signal input B1 is output from the signal output D1 and the NAND
Applied to the gate input of circuit 352.

By the logic 0 (low level) signal of this failure signal, the NAND circuit 351 of the selection signal generating circuit 35.
The output Q output outputs a logic 0 (low level) signal and is applied to the input D of the latch 451 of the controlled unit 8 through the buffer 353. At this time, the hold (HOLD) input of the latch 451 is supplied with a logic 0 (low level) signal indicating inactivity as a protect signal, so that the logic 0 (low level) signal supplied to the input D is It is output from the output Q and applied to the control input C1 of the selector 46.

The control input C1 of the logic 0 (low level) signal causes the selector 46 to output the clock from the 1-system clock generation package 20 supplied to the signal input B1 from the signal output D1 of the selector 46. Supplied to processing package. In this way, switching to the 1-system clock is performed due to the failure of the 0-system clock generation package 10.

Operation in case of 1-system failure
Even in the case of a system failure, the switching operation from the 1-system clock output to the 0-system clock output can be performed by the same operation.

[0025]

As described above, the 0-system clock is supplied to each processing package in the initial state when power is turned on. The setting of the 0-system clock or the 1-system clock in this initial state is made by setting the switch SW1 of the monitor control unit 7 which can be inserted and removed.

That is, regarding the selection of the clock in the initial state, the 1-system clock is selected when the switch SW1 is set to the a side, and the 0-system clock is selected when the switch SW1 is set to the b side.

However, when the above-mentioned detachable monitor controller 7 has some trouble, for example, the protect signal is given in the active state to set the logic 1
Hold (high level) signal of latch 451 (HOL
D) It is conceivable that the monitoring control unit 7 is supplied to the input, and the monitoring control unit 7 is removed from the duplexer and naturally replaced with a normal monitoring control unit.

In such a case, for example, when the supervisory controller 7 is removed from the duplexer, the 0-system clock is still selected, but the normal supervisory controller 7 is replaced with the duplexer. In this case, if the system selection of the switch SW1 is mistakenly set to the 1-system clock side a, even if the 0-system clock is selected in this duplexer, the normal monitoring control unit 7 is By inserting into the duplexer and setting the protect signal to inactive, that is, to logic 0 (low level), the 0 system clock is automatically switched to the 1 system clock.

When the switching is performed in this way, each processing package which has been supplied with the 0-system clock is suddenly switched to the supply of the 1-system clock, which causes a momentary interruption of the processing at the time of switching, which affects the processing. There was a problem.

That is, the above-mentioned problem is because there is a possibility that the setting of the switch SW1 may be erroneous when the monitoring control unit is replaced.

When the monitor control unit 7 is pulled out, for example,
When the 1-system clock is selected, the protect signal is removed in the active state (logic 1, high level), and in this state, the protect signal is erroneously inactive (logic 0, low level). With latch 451
Is applied to the hold input of the latch 451 at that time, the logic 1 (high level) applied to the D input of the latch 451 at that time is output from the Q output and applied to the selector 46.
Then, the selector 46 outputs 0 applied to the A1 input.
The system clock is output from the D1 output.

As described above, there is a problem in that clock switching is performed due to an error in how the protect signal is given, and the processing in the processing module is affected by a momentary interruption or the like.

Therefore, the operator is not entrusted with the switching operation of the system, that is, the switch SW1 as described above.
There is a demand for a safe mechanism in which the wrong system selection cannot occur, and the clock system is not wrongly selected even when the protect signal is applied incorrectly.

The present invention has been made in view of the above problems, and an object thereof is to eliminate the need for the operator to perform a switching operation of a redundant system, to have a simple structure and to prevent an erroneous system. The purpose is to provide a redundant device in which no choice can occur.

[0035]

In order to achieve the above object, the present invention is configured such that at least two processing modules (for example, processing boards and processing units) are redundantly configured, and one or more of the above processing modules are provided. Two or more processing modules are selected and operated as the active system, and the remaining processing modules are standby systems. The operating status of the above processing modules is monitored, and if the active processing module fails, , A supervisory control unit that outputs a selection control signal for making one of the normal processing modules of the standby system the active system, and, when the selection control signal is given, sets any one of the processing modules of the standby system to the active system. A redundant device (for example, a processing device) provided with a selection unit for realizing the above is realized by the following characteristic configuration.

In other words, the power-on operation system that supplies a power-on operation system setting signal for setting one or more of the processing modules as an operation system to the monitoring control unit when power is supplied to the inside of the apparatus. When the power-on operation system setting signal is supplied, the monitoring control unit includes a setting means, and gives the selection unit a selection control signal for setting one or more of the processing modules as an operation system. The selection unit selects the corresponding processing module as an active system according to the selection control signal.

Further, the selection unit holds and outputs the selection state information indicating that the processing module is in the operating state for the monitoring control unit, and the monitoring control unit can be inserted / removed from the device. It is preferable to output a selection control signal in order to make one or two or more of the processing modules corresponding to the selection state information active as an operating system when the processing module is inserted after being removed from the apparatus.

[0038]

According to the present invention, when power is supplied to the inside of the apparatus, the power-on operation system setting means sets the operation system to the operation system from among the processing modules having two or more.
Alternatively, a power-on operation system setting signal for selecting two or more processing modules is automatically output. Therefore, the conventional switch setting for selecting the operating system is not performed.

When the power-on operation system setting signal is given to the supervisory control unit, a selection control signal for making one or more of the processing modules the operation system is given to the selection unit. This selection control signal is a control signal that allows the selection unit to select a processing module as an active system. Then, since the selecting unit selects the designated processing module as the operating system based on the selection control signal, selection control by the operator is not necessary.

In addition, when the processing module of the active system has a failure, the monitoring control unit can change the normal processing module from the standby system to the active system among the processing modules which are the standby system. Therefore, it is possible to realize a redundant device that can normally and continuously operate even if a failure occurs. In addition, maintenance can be facilitated and an erroneous selection of the operating system can be eliminated.

The monitoring control unit can be inserted into and removed from this device, and selection state information indicating that the selection unit is in the operating state until the monitoring control unit is removed is provided. Since the output is held for monitoring control, if you insert the monitoring control after removing it,
The held selection state information can be used to bring the state up to the state before the removal.

In this way, the monitoring control unit is automatically reset to the state before the removal, so that even if the processing module in the operating state has a failure, the selection unit is set to the normal standby system. It is possible to switch the existing processing module to the active system properly.

Therefore, since the supervisory control unit is replaced at the time of failure, the selection state of the active system is not changed even if it is removed and inserted, and even if the processing module of the active system fails, the processing module of the standby system To reconfigure the operating system,
A redundant device can be realized.

[0044]

BEST MODE FOR CARRYING OUT THE INVENTION Next, the present invention is applied to a clock generation package 2
A preferred embodiment in the case of being applied to a redundant redundant device will be described with reference to the drawings.

Configuration of Redundant Device FIG. 1 is a functional block diagram of the duplicated redundant device of this embodiment. In FIG. 1, the same parts as those of the conventional apparatus of FIG. 2 described above are denoted by the same reference numerals, and thus the functions are also the same. Therefore, the description of the same portions as those in FIG. 2 of the conventional description will be omitted.

The duplex redundant device of FIG. 1 is roughly composed of a monitor control unit 3, a controlled unit 4, a 0 system clock generation package 10 and a 1 system clock generation package 20. That is, the 0-system clock generation package 10 and the 1-system clock generation package 20 are duplicated.
Is the same clock generation package as the conventional one. Therefore, here both packages are, for example, a few MH
A clock of about z is generated and given to the controlled unit 4.
Then, it is assumed that a clock of either the 0-system clock or the 1-system clock is selected from the controlled unit 4 and given to each processing package.

In the duplicated redundant device of FIG. 1, the characteristic configuration is that the monitoring control unit 3
The controlled part 4 will be described in detail below. That is, the monitoring control unit 3 does not include the switch SW for system switching, for example, as compared with the conventional FIG. Further, the controlled unit 4 is also characteristically provided with a power-on reset circuit 41, and supplies this output signal to the monitoring control unit 3. Further, the power-on reset signal from the power-on reset circuit 31 of the monitor control unit 3 is given to the switching controlled circuit 45 of the controlled unit 4.

Next, an initial selection operation at power-on, a selection operation after power-on, a selection operation in the case of 0 system failure, a selection operation in the case of 1 system failure, etc. will be described.

Initial operation (operation at power-on) In FIG. 1, when the power supply to the duplex redundant device is started, the power-on reset circuit 31 of the monitor control unit 3 outputs the power-on reset signal D, For example. About 100
The signal is output for about msec, and the logical 1 (high level) signal is applied to the control input C1 of the selectors 342 and 343 through the NOT circuit 36.

Further, the power-on reset circuit 41 newly provided in the controlled unit 4 also outputs a logic 0 (low level) signal for the power-on reset signal G for, for example, about 100 msec, and through the NOT circuit 42, Logic 1
A (high level) signal is given to the OR circuit 43. And
The OR circuit 43 outputs a logic 1 (high level) signal B,
The signal is supplied to the switching signal input circuit 34 of the monitoring controller 3 through the buffers 44 and 37.

Then, the NO of the switching signal input circuit 34
When the T circuit 341 is given the logic 1 (high level) signal B from the controlled section 4, it gives a logic 0 (low level) signal to the A1 input of the selector 342. Further, the selector 343 of the switching signal input circuit 34 also inputs a logic 1 to the A1 input.
A (high level) signal B is provided.

Then, since the logic 1 (high level) signal is applied to the control inputs C1 of the selectors 342 and 343, the logic 1 (high level) signal applied to the A1 input of the selector 343 is output. Output from D1, N
It is given to the AND circuit 352. Further, A of the selector 342
A logic 0 (low level) signal applied to the 1 input is output from the signal output D1 and applied to the NAND circuit 351.

As a result, the NAND circuit 3 of the selection signal generating circuit 35 composed of the RS flip-flop.
A logic 1 (high level) signal is output from the Q output of 51. This logic 1 (high level) signal is given to the latch 451 signal input D of the controlled unit 4 as the selection command signal A.

On the other hand, when the power is turned on, the protect signal is inactive, and a logic 0 (low level) signal is given, and this signal is given to the OR circuit 453. Then, the power-on reset circuit 31 of the monitor control unit 3 supplies a logical 1 (high level) signal to the OR circuit 453 at the time of power-on, so the OR circuit 453 outputs a logical 1 (high level) signal, It is applied to the hold (HOLD) input of the latch 451.

As a result, the latch 451 holds (latches) a logic 1 (high level) signal at the D input and Q
Output from output. The output signal E (logic 1 (high level) signal) is given to the control input C1 of the OR circuit 43 and the selector 46. Then, the selector 46 outputs the 0-system clock given to the A1 input from the signal output D1.

Operation after power-on Then, the above-mentioned power-on reset is performed for about 100 ms after the power is turned on.
After ec has elapsed, the outputs of the power-on reset circuits 31 and 41 change from logic 0 (low level) signal to logic 1
Change to (high level) signal. Therefore, the monitoring controller 3
To the control input C1 of the selectors 342 and 343 of
A (low level) signal is given. As a result, the selectors 342 and 343 are changed from the connection between the signal input A1 and the signal output D1 to the connection between the signal input B1 and the signal output D1.

Then, the signal input B1 of the selector 342 is on standby so as to receive the signal from the 1-system failure detection circuit 33. Further, the signal input B1 of the selector 343 is on standby so as to receive the signal from the 0-system failure detection circuit 32.

Even in the above-mentioned state, the Q output state of the selection signal generating circuit 35 does not change and the logic 1 (high level) is output.

On the other hand, although the protect signal is continuously inactive from the above, that is, is set to logic 0 (low level), the power-on reset circuit 31 of the monitor control unit 3 is used.
By outputting the output D of the logic 1 (high level) signal, the signal given to the OR circuit 453 of the controlled part 4 is given logic 0 (low level). Then, the OR circuit 453 outputs a logic 0 (low level) signal and supplies it to the hold (HOLD) input of the latch 451, so that the latch 451 is changed from the hold (latch) state to the through (th) (th).
Rough) state. Therefore, the latch 451
As the Q output, the output of the logic 1 (high level) signal is continued.

Selection operation when the monitor control unit 3 is removed / inserted
Even removing and inserting the monitoring control unit 3 in such a state of work above, it will be described that the setting state of the above is not changed. As a premise for this operation, regarding the length of the connector connecting pin to this device related to the signals A and C of the monitoring control unit 3, the length of the connector connecting pin of the signal A is calculated from the connector connecting pin of the signal C. Also keep it long.

Assuming such a connector connection pin,
When removing the monitor control unit 3 from this device, the signal A
The signal C is disconnected earlier than the signal C. Therefore, the input side of the buffer 454 of the controlled unit 4 is + 5V via the resistor R6.
Since it is pulled up to, it is set to logic 1 (high level). Therefore, the hold (HO) of the latch 451 is
A logic 1 (high level) signal is applied to the (LD) input. Therefore, the latch 451 is brought into the hold (latch) state.

Next, since the connector connecting pin of the signal A is pulled out, the supply of the signal A to the D input of the latch 451 is stopped. Therefore, the Q output of the latch 451 does not change from the time described above, and since the logic 1 (high level) signal is continuously output, the 0 system clock selection state does not change.

Then, when the monitor control unit 3 is inserted into this device, D of latch 451 of signal A precedes signal C.
Supply to the input is started. After that, since the signal C is supplied to the hold (HOLD) input of the latch 451, it is assumed that the signal C is supplied at the logic 1 (high level) after the signal A is supplied at the logic 1 (high level). Also, the latch 451 does not change the original logic 1 (high level) output state. Therefore, even after the supervisory control unit 3 is removed and inserted, the above-described 0 system clock selection state is not changed.

Operation in case of 0-system failure Next, for example,
0 system failure detection circuit 32 is a 0 system clock generation package 1
When a 0 failure (fault) is detected, a logic 0 (low level) signal is output as a failure signal and is applied to the signal input B1 of the selector 343.

At this time, the control circuit C1 of the selector 343 receives a logic 0 (low level) signal from the NOT circuit 36, and the signal input B1 and signal output D1 of the selector 343 are connected. Therefore, the logic 0 (low level) signal of the failure signal given to the signal input B1 is outputted from the signal output D1 and given to the gate input of the NAND circuit 352. At this time, the 1-system failure detection circuit 33 continuously outputs a logic 1 (high level) signal from the D1 output of the selector 342, which is applied to the NAND circuit 351.

Then, according to the logic 0 (low level) signal of this failure signal, the Q output of the NAND circuit 351 output of the selection signal generation circuit 35 outputs the logic 0 (low level) signal, and the latch of the controlled part 4 is latched through the buffer 353. 45
Input D of 1. At this time, this latch 45
A logic 0 (low level) signal indicating inactivity is given as a protect signal to the 1 hold (HOLD) input, and the signal C is also given at the logic 0 (low level), and is input to the hold (HOLD) input of the latch 451. Since it is given, the latch 451 is through.
h) The state is set.

Therefore, the logic 0 (low level) signal applied to the input D of the latch 451 is output from the output Q and applied to the control input C1 of the selector 46. Moreover, the logic 0 (low level) signal of the Q output is also given to the OR circuit 43. As a result, the OR circuit 43
Outputs a logic 0 (low level) signal, and this signal is given to the switching signal input circuit 34 of the monitoring controller 3.

On the other hand, by the control input C1 of this logic 0 (low level) signal, the selector 46 causes the 1-system clock from the 1-system clock generation package 20 supplied to the signal input B1 to be output from the signal output D1 of the selector 46. It is output and supplied to each processing package. In this way
Due to a failure of the 0-system clock generation package 10, switching to the 1-system clock is performed.

Operation in case of 1-system failure
Even in the case of a system failure, the switching operation from the 1-system clock output to the 0-system clock output can be performed by the same operation as the above-described 0-system operation. That is, the 1-system failure detection circuit 33
Detects a failure (failure) in the 1-system clock generation package 20, outputs a logic 0 (low level) signal, and this signal is output from the D1 output of the selector 342.
It is given to the ND circuit 351. On the other hand, since the 0-system is not in failure, the gate input of the NAND circuit 352 is set to logic 1 (high level). As a result, the Q output of the selection signal generation circuit 35 outputs a logic 1 (high level) and is given to the D input of the latch 451 as the selection command signal A.

The latch 451 has a through (thr
Since it is in the off state, the logic 1 (high level) signal of the D input is Q-outputted and applied to the control input C1 of the selector 46 and also applied to the OR circuit 43. Therefore, the selector 46
Switches so as to selectively output the 0-system clock.

Effects of One Embodiment According to the duplexing redundant device of the above one embodiment, the controlled part 4 is provided with the power-on reset circuit 41, and the output signal G of this circuit is used to monitor and control part 3.
Since it is given to the switching signal input circuit 34, the switch is automatically set to 0 at the initial stage without any switch setting for initial system selection as in the prior art.
The system clock can be selected.

Further, the monitor control unit 3 is removed from this device,
Even if it is inserted after that, the selection state of the system can be continued without changing the selection state of the system before the removal.

Therefore, since no means for system selection by the operator is provided, there is no risk of mistakenly changing system selection when the monitor control unit 3 is inserted or removed. Moreover, the system is realized with a simple configuration, and highly reliable system selection can be performed. Furthermore, maintenance becomes easy.

[0074] FIG other embodiments In the above embodiment 1
In the above configuration, the 0-system clock is automatically selected upon power-on, but the configuration is not limited to this 0-system clock selection. For example, in the case of selecting the 1-system clock upon power-on, this can be realized by configuring the circuit in the dotted line portion of FIG. 1 as shown in FIG.

That is, in FIG. 4, the power reset signal is output as a logic 0 (low level) in accordance with the power-on and is given to the AND circuit 49. Then, the AND circuit 49
Irrespective of which logic state (level state) the Q output of the latch 451 is in, it outputs a logic 0 (low level) as the output of the AND circuit 49. This logic 0 (low level) signal is supplied to the monitoring controller 3 through the buffer 44. As a result, the selection signal A is set to logic 0.
A (low level) signal is applied to the D input of the latch 451, and a logic 0 (low level) signal is applied to the selector 46 from the Q output of the latch 451 to select the 1-system clock.

As a configuration of the above-mentioned redundant device, FIG.
It is not limited to the functional blocks of. For example, although the case where the present invention is applied to the duplication redundant device has been described in the above embodiment, the present invention is not limited to such duplication. For example, it may be triple or more. Further, it is possible to adopt a configuration in which any one of three or more layers is selected. In addition, as another configuration, two or more of the triple or more may be set as an active system and the rest may be set as a standby system.

Furthermore, in the above-described embodiment, the clock generation package is a redundant system, but the invention is not limited to such a clock generation package. For example,
The present invention can also be applied to a processing module, a power supply (power processing) module, and a device in which other components are redundantly configured.

[0078]

As described above, according to the redundant device of the present invention, it is provided with the power-on operation system setting means, and the supervisory control unit receives the power-on operation system setting signal, A selection control signal for making one or more or more active systems is given to the selection unit, and the selection unit can select the corresponding processing module as the active system, so that the operator can switch the redundant system. It is possible to prevent an incorrect system from being selected without the need to perform an operation, with a simple configuration.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a duplex redundant device according to an embodiment of the present invention.

FIG. 2 is a functional block diagram of a conventional duplexer.

FIG. 3 is a functional explanatory diagram of a selector.

FIG. 4 is a partial explanatory diagram for explaining another embodiment.

[Explanation of symbols]

3 ... Supervisory control unit, 4 ... Controlled unit, 10 ... 0 system clock generation package, 20 ... 1 system clock generation package, 3
1, 41 ... Power-on reset circuit, 32 ... 0 system failure detection circuit, 33 ... 1 system failure detection circuit, 34 ... Switching signal input circuit, 35 ... Selection signal generating circuit, 45 ... Switching controlled circuit, A ... Selection command Signal, B ... Selected signal, C ... Power-on reset signal.

Claims (2)

[Claims] 1. A device in which at least two or more processing modules are redundantly configured, and one or more processing modules among the processing modules are selected and operated as an active system, and the remaining processing modules are standby systems. Therefore, the monitoring control unit that monitors the operation status of the above processing module and outputs a selection control signal for making one of the normal processing modules of the standby system the active system when the processing module of the active system has a failure. When the above selection control signal is given,
In a redundant device equipped with a selection unit that makes one of the processing modules of the standby system the active system, in order to make one or more of the processing modules the active system with the supply of power to this device. A power-on operating system setting means for supplying the power-on operating system setting signal to the monitoring control section, and the monitoring control section receives one of the processing modules when the power-on operating system setting signal is supplied. Alternatively, the redundant device is characterized in that a selection control signal for making two or more active systems is given to the selection unit, and the selection unit selects the corresponding processing module as an active system by the selection control signal. 2. The selection unit holds and outputs selection state information indicating that the processing module is in an operating state for the monitoring control unit, and the monitoring control unit can be inserted and removed from the device, With the insertion after removal, of the above processing modules,
2. The redundancy device according to claim 1, wherein a selection control signal is output in order to set one or more or more corresponding to the selection state information as an active system.