JPH06335102A - Pulse input processor for electric railcar controller - Google Patents

Abstract

PURPOSE:To accurately read the latest data and to use the data for control by sending a latch signal from a latch circuit to a register only while there is a signal impossible to be read, and applying a read command from a weight timing circuit to the register while there is no signal impossible to be read. CONSTITUTION:A latch circuit outputs a latch signal TH to registers 5, 6 according to a latch signal RCK in the case of a read signal 'H'. A weight timing circuit 8 outputs a read command (RD) when a read disable signal (XT) is 'L' of a read disable signal circuit 10 to the registers 5, 6 to a READ signal from a CPU 11. Thus, data in the registers 5, 6 become unstable, the XT is formed in a period not to read data. When data read READ is input during the XT, a weight is applied to the RD until the XT is interrupted, and data is read after the XT is interrupted, and hence the data can be effectively read after it is updated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse input processing device of an electric vehicle controller used for automatically measuring the speed and mileage of an electric vehicle.

[0002]

2. Description of the Related Art In recent years, as the performance of electric vehicles has improved, accurate vehicle information such as traveling speed and traveling distance has been required. The traveling speed is important information in vehicle traveling control, driving information, etc., and the traveling distance is important information for confirming the vehicle position in operation control.

To grasp the traveling speed and traveling distance of a vehicle, a pulse signal is generated from the rotation of an axle by a tacho generator or a pulse generator, and this pulse signal is counted at regular intervals. Then, the travel distance per pulse is obtained from the wheel diameter, and the travel distance per constant time, that is, the travel speed is calculated by multiplying the pulse count value and the travel distance per pulse, and this constant By accumulating the mileage per hour, the data is about a kilometer.

Conventionally, as a pulse input processing device of an electric vehicle control device of a system that takes out the rotation of such an axle as a pulse signal and obtains a traveling speed and a traveling distance, a configuration according to a timing chart shown in FIG. 4 is conventionally known. Has been. This conventional pulse input processing device normally counts the number of pulses PI input by a counter for each constant time (time base) TB of sampling, latches the count value in a register (RCK), and also stores this data. Then, the speed, frequency and mileage are calculated. In this case, the timing of latching the count data in the register and the clearing of the data in the counter are performed by inputting the first pulse of the time base TB.

For this reason, counter clear (CCLR)
Sometimes, when the pulse input PI enters the counter, the pulse cannot be counted, and the count value latch (RC
When reading the count data at the time of K), there was a problem that wrong data was read.

For example, when two counters are used for each of upper and lower 8 bits to form 16-bit data, when the first count value is (0100) H and the next count value is (00FF) H, The two count values actually differ by only one count, but only the upper 8 bits latch the new count value, and the lower 8 bits have not latched the new count value yet and remain latching the previous value. If so, the read value may be (0000) H.

Therefore, the input pulse PI is converted into a signal PIC synchronized with the system clock SYSCLK, the signal PIC is counted, and the timing is missed by counter clear CCLR or counter latch RCK. I try to prevent it from becoming count data.

When pulse input processing is performed by such a method, pulse count is performed when speed and frequency are calculated using data of the same sampling timing of two types of related pulse count data such as a period counter. The counter is an N counter, the counter that counts the clock CK (Hz) that is the basis of the frequency is an M counter, and the timing NRD for reading the data (N) of the N counter and the timing for reading the data (M) of the M counter MRD,

[Equation 1] The frequency f is calculated as

At this time, the data of the M counter and the data of the N counter must be calculated using the data of the same sampling timing. Therefore, the CPU is the timing MR
The BUSY signal is output from the time when the data M is read at D until the timing NRD at which the data N is read.
As a result, while the BUSY signal is being output, there is the first pulse input PI from the time base TB and the timing R
Even if the timing CCLR for latching the count value with CK and clearing the counter comes, the next pulse signal PI is input after latching and counter clearing are not performed and the BUSY signal is released after reading the M and N data. When it comes, the count value is latched and the counter is cleared.

By doing so, data having the same sampling timing can be obtained as the data (M) and the data (N) without considering the data read timing on the CPU side. Moreover, pulse input PI, latch RC
The timings of K and counter clear CCLR are synchronized with the system clock SYSCLK, and there is an advantage that clearing is applied at the same time as counting and the pulse input is not missed.

[0011]

However, such a conventional pulse input processing device for an electric vehicle control device has the following problems. That is, when the count value of the pulse signal is read from the CPU, erroneous data may be read. Therefore, the BUSY signal is provided during the reading to prevent the count value from being latched or cleared during this period. The count shifts to the next sampling timing by the amount of the BUSY signal, which has little influence on the frequency calculation, but there is a problem that an accurate count value cannot be obtained strictly.

Explaining the reason for this, basically, each sampling time ts10, ts20 is basically ts10 = t.
Although it is s20, when the output period of the BUSY signal overlaps with the data update timing, it is actually ts11, ts21.
And then | ts11-ts21 | = tsd> 0. This sampling time difference tsd is equal to the above-mentioned MR.
It becomes large when the interval between D and NRD is long and when the frequency of the input pulse is low. Especially when the frequency of the pulse input is low at low speed, the deviation to the next sampling time becomes large.

Therefore, if the pulse input count value is read once in the time base TB, when latching and counter clearing is delayed by the BUSY signal, it is the same as the time base one time before. The sampling data was read twice, and there was a problem that the latest data was not always used for control. This is because in the case of the example shown in FIG. 4, the data read by NDR1 and NDR2 is the data of the next sampling timing when viewed from the CPU side, but in reality, both are RCK.
The same data is latched at the timing of 1.

When the count value of the pulse input data is not cleared for each time base TB and is cumulatively used as the data of the kilometers, the traveled distance, and the current position, the time actually corresponds to the time base, and in the meantime. Since there must have been an input pulse, there must have been a movement distance, but with the conventional device, the same data is read twice, so it means that there was no movement during this time base.
When read next time, if the BUSY signal and the counter value latch timing do not overlap, they will be added to the next data. Therefore, if the BUSY signal and the latch are overlapped and the latch is delayed every time, the old sampling data is read once, which causes a delay in control.

In order to avoid such problems, BU
If the read timing is considered by the software program without using the SY signal, there is a problem that the load on the software side increases.

The present invention has been made in view of such conventional problems, and data is sampled and updated at a constant cycle regardless of the frequency of the input pulse signal, and the read timing is set at a constant interval. If you read the data without being aware of it, you can always read the latest data accurately, and always use the latest data for control.
An object of the present invention is to provide a pulse input processing device of an electric vehicle control device that can always obtain accurate mileage data by accumulating data for each sampling timing and using the data for about a kilometer.

[0017]

According to a first aspect of the present invention, there is provided a pulse input processing device for an electric vehicle control device, wherein a pulse signal generator for converting the rotation of the propulsion rotating portion of the electric vehicle into a pulse signal and extracting the pulse signal is provided. Arithmetic processing of input pulse count data by outputting a system clock signal with a frequency higher than the pulse signal output by the generator, a latch timing signal, a sampling timing signal, a latch timing signal, and a count data read timing signal. And the pulse signal from the pulse generator
A counter that inputs and counts in synchronism with the system clock from, a register that latches the count data of the counter, and the first pulse of the system clock at each sampling timing provided by the CPU makes it impossible to read for a certain period. A read disable signal generating circuit that outputs a signal, a latch circuit that receives a latch timing signal from the CPU, and gives a latch signal to the register only during a period when the read disable signal creating circuit is giving the count, and a count from the CPU A wait timing circuit that receives a data read timing signal and does not output a read command during the period when the read disable signal is given from the read disable signal creation circuit, and gives a read command to the register if the read disable signal is not given. And Those were.

According to a second aspect of the present invention, in the pulse input processing device of the electric vehicle controller according to the first aspect of the invention, a one-shot circuit that receives a latch signal of the latch circuit and outputs a data update information signal of a constant time width. It is equipped with.

According to a third aspect of the present invention, a plurality of pulse input processing devices of the electric vehicle control device according to the second aspect are arranged in parallel, and each count data of pulse signals related to each other is output, and the CPU counts the pulse count data. Each of the one-shot circuits is read during the period in which the data update information signal is output.

[0020]

In the pulse input processing device of the electric vehicle controller according to the first aspect of the present invention, the rotation of the propulsion rotating portion of the electric vehicle is converted into a pulse signal by the pulse signal generator and is taken out to the counter. In the counter, the pulse signal from the pulse generator is input in synchronization with the system clock given from the CPU to count. The latch circuit receives the latch timing signal from the CPU and gives the latch signal to the register only during the period when the read impossible signal is given from the read impossible signal generating circuit. The register receives this latch signal and latches the count data of the counter.

The read disable signal generating circuit outputs a read disable signal for a fixed period by the first pulse of the system clock at each sampling timing given from the CPU, and the wait timing circuit receives the count data read timing signal from the CPU. Then, it waits for the period when the read disable signal is given from the read disable signal generation circuit. If the read disable signal disappears, a read command is given to the register, and the pulse count latched by the CPU until then is sent during this period. Output the data.

In this way, the pulse count data is latched in the register, and at least at the timing when the counter is cleared, the reading is waited so that the count data before and after the data is updated and the count data at the previous sampling timing are updated. Which of the count data at different sampling timings is to be read?
Make sure that the CP is read after the data is surely updated.
Allow U to accurately calculate the speed and mileage of an electric vehicle.

According to another aspect of the pulse input processing device of the electric vehicle control device of the present invention, the pulse input processing device receives the latch signal of the latch circuit,
If the CPU receives the data update information signal and reads the latch data of the register by providing the one-shot circuit that outputs the data update information signal of a fixed time width, the updated data is surely read. Will be able to.

According to a third aspect of the present invention, a plurality of pulse input processing devices of the electric vehicle control device according to the second aspect are arranged in parallel so as to output respective count data of pulse signals related to each other, and the CPU outputs the pulse data. By reading each count data during the period in which the data update information signal is output from each one-shot circuit, the count data of a plurality of related pulse signals can be read at the timing when they are all updated. The pulse input processing can be performed accurately.

[0025]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a circuit block diagram of a common embodiment of the first and second aspects of the invention. As shown in FIG. 1, a pulse for converting the rotation of an electric vehicle axle or other propulsion unit into a pulse signal and outputting the pulse signal. A pulse signal PI output from a pulse generator (not shown) such as a generator, a tacho generator, or the like is input in synchronization with a system clock signal SYSCLK having a frequency sufficiently higher than the pulse signal PI, and a pulse signal PIC is output. And a first counter 2 and a second counter 3 for counting the output signal PIC of the flip-flop 1.

The first and second counters 2 and 3 are counters each having 8 bits, and the first counter 2 has the lower 8 bits C0.
7-00 is counted, the second counter 3 counts the upper 8 bits C15-08, and the second counter 3 enables the carrier CA1 of the first counter 2 and counts the pulse PIC. The carrier CA2 of the second counter 3 is the other flip-flop 4
To the overflow bit OVF. The overflow clear signal CLOVF is also input to the flip-flop 4,
The overflow bit signal OVF is a digital input signal when viewed from the CPU 11 side, and the overflow bit clear signal CLOVF is a digital output signal when viewed from the CPU 11 side. The CPU 11 confirms the overflow and then clears the overflow. .

The counter values of the first and second counters 2 and 3 are input to the first and second registers 5 and 6, respectively, and the 16-bit data D1 is output from these registers 5 and 6.
5-00 is read as RD.

The pulse input processing device also includes a one-shot circuit 7, a wait timing circuit 8, a latch signal output circuit 9, and a read disable signal generation circuit 10 for generating a read disable signal XT.

The one-shot circuit 7 is a circuit for generating a one-shot for a certain period of time immediately after the counter value is latched in the first and second registers 5 and 6, and thereby creates the data update information signal SIN. The data update information signal SIN can be read as a digital signal when viewed from the CPU 11 side.

The latch signal output circuit 8 outputs a latch signal LTH to the first and second registers 5 and 6, respectively. The read disable signal generation circuit 8 is a circuit that creates a latch and counter clear timing signal, and outputs the read disable signal XT. The wait timing circuit 8 reads the data when the read disable signal XT is output,
Wait is applied to the read signal RD until the read disable signal XT is released.

Next, the operation of the pulse input processing device of the electric vehicle control device having the above configuration will be described. FIG. 2 shows a timing chart showing the operation of the pulse input processing apparatus of this embodiment, and FIG. 3 shows a data read timing chart.

The system clock signal SYSCLK is input to the flip-flop 1, and the pulse signal PI is input from the pulse generator of the rotating portion such as the axle, and the system clock SYSCL is input in the flip-flop 1.
In synchronism with K, the pulse signal PI is the first and second PIC as PIC.
It is output to the respective counters 2 and 3.

Each of the counters 2 and 3 counts this PIC signal until the counter clear signal CCLR is input, but the first counter 2 counts the lower 8 bits C07-00 of the pulse input PIC, The carrier CA1 is given to the second counter 3 to enable it, and the second counter 3 counts the pulse signal PIC in the enabled state to obtain the counter value of the upper 8 bits C15-08. The carrier CA2 of 3 is output to the other flip-flop 4, and when the carrier CA2 is input to the flip-flop 4, the overflow bit OVF is output.

When the overflow of the counters 2 and 3 is confirmed by the input of the overflow bit OVF from the flip-flop 4 from the CPU 11, the overflow clear signal CLOVF is output to the second flip-flop 4.

The read disable signal generating circuit 10 is a CPU 11
To time base signal TB, system clock signal SY
Receives SCLK, counter clear signal CCLR, reset signal RESET, and clock synchronization pulse signal PIC from flip-flop 1, and outputs read disable signal XT that gives counter clear and register store timing to wait timing circuit 8 and latch circuit 9. .

The latch circuit 9 receives the latch signal RCK,
By inputting the latch signal RCK when the read disable signal is "H", the latch signal LTH is output to each of the first and second registers 5 and 6, and at the same time, the one-shot circuit 7
Also outputs a latch signal LTH, and the one-shot circuit 7 receives this and outputs a one-shot signal SIN to the CPU 11.

In the CPU 11, the one-shot circuit 7
The data update information signal SIN from the device is received as a digital input signal.

The wait timing circuit 8 responds to the read signal READ from the CPU 11 with the read disable signal XT.
Is not "H", the read command RD is not output,
When the read disable signal XT becomes "L", the read command RD is output to each of the first and second registers 5 and 6.

The first register 5 stores the counter value C07-00 of the lower 8 bits of the first counter 2 at the timing when the latch signal LTH is input, and the second register 6
Then, at the timing when the latch signal LTH is input, the second
The counter value C15-08 of the upper 8 bits of the counter 3 is stored. Then, at the timing when the read command RD is input from the wait timing circuit 8, these first,
16-bit data D15-0 from the second registers 5 and 6
8; D07-00 is read. Therefore, only one of the two registers 5 and 6 latches new data and the other one is latched after reading, and the above 8 bits of the read data and the lower 8 bits become data of different sampling periods, which is erroneous. It is possible to prevent the reading of the data, and the counter value of the same sampling period is latched between the two registers 5 and 6, and the counter value is read in the period different from that.

At the time of reading the pulse count data D15-00, the one-shot circuit 7 outputs the data update information signal SIN to the CPU 11, and the CPU 11 receives the data update information signal SIN to update the current data. Determine whether it is immediately after or before changing to the next data. Then, the read timing R is set so that the CPU 11 reads the counter value during the period in which the data update information signal SIN is output, that is, immediately after the data is updated.
Control EAD.

Thus, in the pulse input processing apparatus of this embodiment, as shown in FIG. 2, when the count of the pulse input PI and the timing of the counter clear CCLR overlap, the pulse count may be missed. All of the latch timing RCK and the counter clear timing CCLR are synchronized with the same system clock SYSCLK having a frequency fSYSCLK which is sufficiently higher than the frequency fPI of the input pulse so that they do not overlap and pulse dropout is prevented.

Further, the time base TB (this frequency is f
When the data is read every TB), the sampling cycle of the pulse input should not be changed so that the latest sampling data can be read without fail. If this sampling cycle is shifted due to the timing of reading data, the data that is read periodically may be the same as the previous one. In this case, it is not possible to obtain accurate mileage data even if the data is accumulated and used for about a kilometer.

By the way, in the case of the microcomputer, the data in the register becomes unstable only when the counter value is latched for only a few nanoseconds. Therefore, it is not necessary to read the data even during this period.
When the timings of the counter value latch RCK and the counter clear CCLR are separated, the count of the pulse input during this time is cleared together with the previous data, so the timing of the latch and the counter clear cannot be separated. Therefore, these latch RCK and counter clear C
If the CLR is synchronized with the system clock SYSCLK having a frequency fSYSCLCK which is sufficiently higher than the input pulse frequency fPI and is generated immediately after the first input pulse from the reference time base TB, the counter value is latched and the counter is cleared. Does not overlap with the next input pulse.

Thus, in the pulse input processing apparatus of this embodiment, the counter value latch RCK and the counter clear CC are
The LRs are grouped together, the data in the registers 5 and 6 becomes unstable, and a timing period including a margin period in a period in which data reading should not be performed is created as the data reading disable signal XT. When a data read READ is entered during the period, the read disable signal XT
The read command signal RD is weighted (RD1) until is cleared, and data is read after the read disable signal XT is cleared. If the read signal READ is input when the read disable signal XT is not output, in this case, a normal read command is given without waiting.
Reading is performed (RD2, RD3).

According to this embodiment, the read disable signal XT
When the system clock SYSCLK is set to several MHz, it is several tens of nanoseconds to several hundred nanoseconds, and the maximum value fPI of the frequency of the input pulse is several tens of kilohertz.
If a relation of fTB << fPI << fSYSCLK is provided so that a sufficient count value can be obtained, the frequency fTB of the time base TB becomes several tens Hz to several KHz.

Therefore, the period tTB of the time base TB is about several msec even if it is small. On the other hand, the overlap between the read disable signal XT and the read signal READ is at most several tens.
It is 0 nsec, and it is almost impossible that the read signal READ enters from the beginning of the read disable signal XT, but even if they overlap, the probability is 0.
The value is as low as 01%, and the reading delay in the case of overlapping is not a problem.

Next, an embodiment of the invention of claim 3 will be described. When two pulse input processing devices shown in FIG. 1 are prepared and configured to count each of two pulse inputs associated with each other, whether or not the count value of each pulse input processing device is data of the same sampling period is determined. In order to detect, the data update information signal SIN output for a certain period of time tSIN (where tTB> tSIN) immediately after the data is updated to a new count value by the one-shot circuit 7 is used.

For example, one pulse input processing device counts the input pulse PI in the time base TB,
The other pulse input processing device counts the system clock SYSCLK in the time base TB of the input pulse PI, so that the data ND,
When it is desired to read MD and use it in the calculation for calculating the PI period of the input pulse, the CPU 11 reads the states of the data update information signals MSIN and NSIN of each pulse input processing device at the same time.

Assuming that the voltage becomes "H" for a fixed time tSIN from the data update, depending on the read timing,
There is a case where one is "H" and the other is "L". In such a case, the "H" side is the updated data and the "L" side remains the data of the previous sampling timing. Therefore, they cannot be used as data for reading these and calculating the cycle. Also, both are "L"
In the state of, even though the data has the same sampling timing, it is possible that only one side will be updated when trying to read the data because the time has passed since the data was updated. No data should be read. Therefore, in order to utilize new information as soon as possible, the update information MSI of each pulse input processing device
It is necessary to read the data when both N and NSIN are in the "H" state, which enables the newest data of the same sampling timing to be read at the earliest timing.

Therefore, as shown in the timing chart of FIG. 3, the CPU 11 reads out the data of the two pulse input processing devices related to each other within the timing which is the read timing tREAD, and the counter value M thereof is read.
The newest data of D and ND can be read out at the earliest timing.

[0051]

As described above, according to the invention of claim 1,
The pulse signal generator takes out the rotation of the propulsion rotating portion of the electric vehicle as a pulse signal and gives it to the counter. In the counter, the pulse signal from the pulse generator is input in synchronization with the system clock given from the CPU 11 to count. The read disable signal generating circuit outputs a read disable signal for a fixed period by the first pulse of the system clock at each sampling timing given from the CPU, and the latch circuit receives the latch timing signal from the CPU and outputs from the read disable signal creating circuit. A latch signal is given to the register to latch the count data of the counter only during the period when the read disable signal is given, and then the wait timing circuit receives the count data read timing signal from the CPU and the read disable signal generation circuit Read not possible signal It waits for the obtained period, and when the read disable signal disappears, a read command is given to the register, and the pulse count data latched by the register is output during this period, so the pulse count data is latched in the register. The read data can be waited at least at the timing when the counter is cleared, and the count data before and after the data is updated is either the count data at the previous sampling timing or the count data at the new sampling timing. Is not read at the time of being read or is unstable, and can be read after the data is surely updated so that the CPU can accurately calculate the speed and mileage of the electric vehicle. Become.

According to the second aspect of the invention, since the one-shot circuit for receiving the latch signal of the latch circuit and outputting the data update information signal of a constant time width is provided, the CPU receives this data update information signal. If the latch data of the register is read out, the updated data can be surely read out.

According to a third aspect of the present invention, a plurality of pulse input processing devices of the electric vehicle control device according to the second aspect are arranged in parallel so as to output respective count data of pulse signals related to each other. Reads each pulse count data during the period when the data update information signal is output from each one-shot circuit. Therefore, the count data of a plurality of related pulse signals are read at the timing when all of them are updated. The pulse input processing can be performed accurately.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of a common embodiment of the inventions of claims 1 and 2. FIG.

FIG. 2 is a timing chart showing the operation of the above embodiment.

FIG. 3 is a timing chart showing the operation of an embodiment of the invention of claim 3;

FIG. 4 is a timing chart showing an operation of a conventional example.

[Explanation of symbols]

 1 Flip-flop 2 1st counter 3 2nd counter 4 Flip-flop 5 1st register 6 2nd register 7 One-shot circuit 8 Wait timing circuit 9 Latch circuit 10 Unreadable signal generation circuit PI pulse input PIC pulse synchronized with system clock Input SYSCLK System clock RCK Latch timing signal CCLR Counter clear signal XT Read disable signal SIN Data update information signal READ Read timing signal RD Read command signal TB Sampling time base

Claims (3)

[Claims] 1. A pulse signal generator for converting the rotation of a propulsion rotating portion of an electric vehicle into a pulse signal and extracting the pulse signal, a system clock signal having a frequency higher than the pulse signal output from the pulse signal generator, and a latch timing signal. A sampling timing signal, a latch timing signal, a count data read timing signal, and a calculation process of the input pulse count data, and a pulse signal from the pulse signal generator,
A counter for inputting and counting in synchronism with the system clock from, a register for latching the count data of the counter, a sampling period given by the CPU, and a first pulse of the system clock at that timing for a certain period. Read disable signal generating circuit for outputting a read disable signal, and a latch for receiving a latch timing signal from the CPU and giving a latch signal to the register only during a period in which the read disable signal is given from the read disable signal creating circuit. The circuit and the CPU receive the count data read timing signal, and do not output the read command during the period when the read disable signal creation circuit gives the read disable signal. If the read disable signal is not given, the read command is not output. Directive the above Regis A pulse input processing device for an electric vehicle control device, comprising: 2. Receiving the latch signal of the latch circuit,
The pulse input processing device of the electric vehicle control device according to claim 1, further comprising a one-shot circuit that outputs a data update information signal having a constant time width. 3. A plurality of pulse input processing devices of the electric vehicle control device according to claim 2, wherein a plurality of pulse input processing devices are arranged in parallel so as to output respective count data of pulse signals related to each other.
A pulse input processing device of an electric vehicle controller, wherein the PU reads each of the pulse count data during a period in which a data update information signal is output from each of the one-shot circuits.