JPH06334347A - Multilayer interconnection substrate - Google Patents

Multilayer interconnection substrate

Info

Publication number
JPH06334347A
JPH06334347A JP5116832A JP11683293A JPH06334347A JP H06334347 A JPH06334347 A JP H06334347A JP 5116832 A JP5116832 A JP 5116832A JP 11683293 A JP11683293 A JP 11683293A JP H06334347 A JPH06334347 A JP H06334347A
Authority
JP
Japan
Prior art keywords
wiring
layer
wiring layer
ceramic
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5116832A
Other languages
Japanese (ja)
Other versions
JP3234045B2 (en
Inventor
Chie Kono
智恵 河野
Susumu Kimijima
進 君島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP11683293A priority Critical patent/JP3234045B2/en
Publication of JPH06334347A publication Critical patent/JPH06334347A/en
Application granted granted Critical
Publication of JP3234045B2 publication Critical patent/JP3234045B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To provide the title multilayer interconnection substrate capable of setting up and controlling the characteristics impedance of a signal wiring layer as well as composing at low cost. CONSTITUTION:The title multilayered wiring substrate is provided with a ceramic laminated layer wiring parts 3 comprising a laminated layer 3a, a power supply wiring layer 3b and a signal wiring layer 3c as well as a thin film wiring layer 4 comprising plural signal wiring layers 4a including a gland wiring layer 4b integrally formed on said ceramic laminated layer wiring parts 3. In such a constitution, said multilayer interconnection wiring substrate is composed of the gland wiring layer 4b of the thin film wiring part 4 to be positioned on the upper layer than the topmost signal wiring layer 4a' as well as said plural signal wiring layers 4a, 4a' laminatedly arranged between the grand wiring layers 4b of the ceramic laminated layer wiring part 4.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、高速・高機能なシステ
ムを実現する高密度な実装構造の構成に適する多層配線
基板に係り、特にマルチチップモジュール(MCM)用に適
する多層配線基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layer wiring board suitable for a high-density and high-performance system having a high-density mounting structure, and more particularly to a multi-layer wiring board suitable for a multi-chip module (MCM).

【0002】[0002]

【従来の技術】クロック周波数が50 MHzを超えるような
高速システムは、高速な LSI素子の開発だけでは実現で
きない。すなわち、高速な LSI素子を高密度に実装し、
LSI素子間の実装遅延を最小にする配線基板が必要であ
る。そして、このような配線基板は、一般に高密度な微
細配線、および所要の特性インピーダンスを実現するた
めに、いわゆる薄膜技術の併用によって多層配線構造に
構成されている。図3は、このような用途に対応して構
成された多層配線基板の構成を断面的に示したもので、
いわゆるセラミック系積層配線部1と、薄膜配線部2と
で構成されている。すなわち、グランド配線層1a、電源
配線層1bおよび信号配線層1cがセラミック絶縁層1dを介
して積層され、この積層領域を貫通して一主面に配置さ
れたロウ付け用パッド1eに接続する入出力ピン1fと他主
面に配置された接続部1gとを電気的に接続するスルホー
ル接続部1hから成るセラミック系積層配線部1をベース
基板としている。そして、前記ベース基板を成すセラミ
ック系積層配線部1上に、前記接続部1gに電気的にビァ
ホール接続する信号配線層を含む複数の信号配線層2aお
よびパッド2bが、たとえばポリイミド樹脂などの樹脂系
絶縁層2cを介して積層・一体的に薄膜配線部2を形成し
た構成を採っている。
2. Description of the Related Art A high-speed system whose clock frequency exceeds 50 MHz cannot be realized only by developing high-speed LSI elements. That is, high-speed LSI elements are mounted at high density,
A wiring board that minimizes the mounting delay between LSI elements is required. Further, such a wiring board is generally formed into a multi-layer wiring structure by using so-called thin film technology in order to realize high-density fine wiring and a required characteristic impedance. FIG. 3 is a cross-sectional view showing a structure of a multilayer wiring board configured for such an application.
It is composed of a so-called ceramic-based laminated wiring portion 1 and a thin film wiring portion 2. That is, the ground wiring layer 1a, the power supply wiring layer 1b, and the signal wiring layer 1c are laminated via the ceramic insulating layer 1d, and are connected to the brazing pads 1e arranged on one main surface through the laminated region. The ceramic-based laminated wiring section 1 including the through-hole connection section 1h electrically connecting the output pin 1f and the connection section 1g arranged on the other main surface is used as the base substrate. A plurality of signal wiring layers 2a and a pad 2b including a signal wiring layer electrically connected to the connection portion 1g by a via hole are formed on the ceramic-based laminated wiring portion 1 forming the base substrate by using a resin system such as a polyimide resin. The thin film wiring part 2 is laminated and integrally formed via the insulating layer 2c.

【0003】[0003]

【発明が解決しようとする課題】上記構成の多層配線基
板においては、薄膜配線部2の信号配線層2aの特性イン
ピーダンスを、セラミック系積層配線部1のグランド配
線層1aとの距離によって制御し得るが、各導体層1a,1
b,1c間のセラミック絶縁層1d厚のバラツキに起因し
て、前記特性インピーダンスを設計値通りに設定し得な
いのが実状である。また、この種の多層配線基板を、た
とえば動作速度50 MHz以上の高速で動作させる場合、前
記薄膜配線部2の信号配線層2aの特性インピーダンスを
一定に制御する必要性から、信号配線層2aとグランド配
線層1aとの距離を大きく設定することになる。つまり、
セラミック絶縁層1d(層間絶縁)の厚さを厚くしなけれ
ばならないが、セラミック絶縁層1dの膜厚化には、コン
バクト化や多層配線密度などの点から限界ある。したが
って、前記信号配線層2aの特性インピーダンスを十分に
制御し得ないので、電気(回路)特性が劣ったままの状
態で実用に供せざるを得ないといえる。
In the multilayer wiring board having the above structure, the characteristic impedance of the signal wiring layer 2a of the thin film wiring portion 2 can be controlled by the distance from the ground wiring layer 1a of the ceramic laminated wiring portion 1. But each conductor layer 1a, 1
In reality, the characteristic impedance cannot be set as designed due to the variation in the thickness of the ceramic insulating layer 1d between b and 1c. Further, when this type of multilayer wiring board is operated at a high speed of, for example, 50 MHz or more, it is necessary to control the characteristic impedance of the signal wiring layer 2a of the thin film wiring portion 2 to a constant value. A large distance from the ground wiring layer 1a is set. That is,
The thickness of the ceramic insulating layer 1d (interlayer insulation) must be increased, but there is a limit to the thickness of the ceramic insulating layer 1d in terms of compactness and multilayer wiring density. Therefore, since the characteristic impedance of the signal wiring layer 2a cannot be sufficiently controlled, it can be said that the signal wiring layer 2a must be put to practical use in a state where the electrical (circuit) characteristic remains poor.

【0004】本発明は上記事情に対処してなされたもの
で、信号配線層の特性インピーダンスを所要値に設定・
制御することが可能で、かつ低コストで構成し得る多層
配線基板の提供を目的とする。
The present invention has been made in consideration of the above circumstances, and sets the characteristic impedance of the signal wiring layer to a required value.
An object of the present invention is to provide a multilayer wiring board that can be controlled and can be constructed at low cost.

【0005】[0005]

【課題を解決するための手段】本発明に係る多層配線基
板は、グランド配線層、電源配線層、および信号配線層
が積層されて成るセラミック系積層配線部と、前記セラ
ミック系積層配線部上に一体的に形成されたグランド配
線層を含む複数の信号配線層から成る薄膜配線部とを具
備して成る多層配線基板であって、前記薄膜配線部のグ
ランド配線層が信号配線層より上層に位置し、かつ複数
の信号配線層はセラミック系積層配線部のグランド配線
層との間に積層的に配置された構成を成していることを
特徴とする。
A multilayer wiring board according to the present invention comprises a ceramic-based laminated wiring section formed by laminating a ground wiring layer, a power supply wiring layer, and a signal wiring layer, and a ceramic-based laminated wiring section on the ceramic-based laminated wiring section. A multi-layer wiring board comprising a thin film wiring section composed of a plurality of signal wiring layers including a ground wiring layer formed integrally, wherein the ground wiring layer of the thin film wiring section is located above the signal wiring layer. In addition, the plurality of signal wiring layers are arranged in a laminated manner between the plurality of signal wiring layers and the ground wiring layer of the ceramic laminated wiring portion.

【0006】[0006]

【作用】本発明に係る多層配線基板においては、信号配
線層がセラミック系積層配線部のグランド配線層および
薄膜配線部のグランド配線層に挟まれた構成を採ってい
る。つまり、信号配線層は、上下2層のグランド配線層
に挟まれたストリップ構造を採ることになるため、前記
信号配線層の特性インピーダンスの制御が容易になさ
れ、たとえば高速な LSI素子を高密度に実装した場合、
LSI素子間の実装遅延を最小にする多層配線基板として
機能することが可能となる。換言すると、低価格で高機
能な MCMの提供が可能となる。
In the multilayer wiring board according to the present invention, the signal wiring layer is sandwiched between the ground wiring layer of the ceramic laminated wiring portion and the ground wiring layer of the thin film wiring portion. That is, since the signal wiring layer has a strip structure sandwiched between two upper and lower ground wiring layers, the characteristic impedance of the signal wiring layer can be easily controlled, and for example, high-speed LSI elements can be densely arranged. If implemented,
It becomes possible to function as a multilayer wiring board that minimizes the mounting delay between LSI elements. In other words, it is possible to provide low-priced, high-performance MCM.

【0007】[0007]

【実施例】以下本発明に係る多層配線基板の要部構成例
を断面的に示す図1、および本発明に係る多層配線基板
のセラミック系積層配線部の要部構成例を一部切断し拡
大して斜視的に示す図2を参照し、本発明の実施例を説
明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 which is a cross-sectional view showing an example of the essential part configuration of a multilayer wiring board according to the present invention, and a partial cutaway of the essential part of the ceramic type laminated wiring part of the multilayer wiring board according to the present invention. An embodiment of the present invention will be described with reference to FIG.

【0008】図1は、 MCM(マルチチップモジュール)
の構成に用る標準的な多層配線基板であり、セラミック
系積層配線部3と、薄膜配線部4とで構成されている。
すなわち、グランド配線層3a、電源配線層3bおよび信号
配線層3cがセラミック絶縁層3dを介して積層され、この
積層領域を貫通して一主面に配置されたロウ付け用パッ
ド3eに接続する入出力ピン3fおよび接続部3gとを具備し
て成るセラミック系積層配線部3をベース基板としてい
る。なお、このセラミック系積層配線部3において、3h
は封止キャップの開口端面を接合するためのシールリン
グであり、またこのセラミック系積層配線部3は、この
種のセラミックスを絶縁層とした多層積層配線基板の製
造に採用されている常套的な手段によって製造される。
FIG. 1 shows an MCM (multi-chip module).
This is a standard multilayer wiring board used for the above-mentioned configuration, and is composed of a ceramic-based laminated wiring section 3 and a thin-film wiring section 4.
That is, the ground wiring layer 3a, the power supply wiring layer 3b, and the signal wiring layer 3c are stacked via the ceramic insulating layer 3d, and the input for connecting the brazing pad 3e arranged on one main surface through the stacked area. The ceramic-based laminated wiring portion 3 including the output pin 3f and the connecting portion 3g is used as the base substrate. In addition, in this ceramic-based laminated wiring part 3, 3h
Is a seal ring for joining the open end faces of the sealing cap, and the ceramic-based laminated wiring portion 3 is a conventional one that is used in the manufacture of a multilayer laminated wiring board using this type of ceramic as an insulating layer. Manufactured by means.

【0009】前記ベース基板を成すセラミック系積層配
線部3上に、前記接続部3gに電気的にビァホール接続す
る信号配線層を含む複数の信号配線層4a、グランド配線
層4b、およびパッド4cが、たとえばポリイミド樹脂など
の樹脂系絶縁層4dを介して積層・一体的に薄膜配線部4
を形成した構成を採っている。ここで、薄膜配線部4
は、樹脂系絶縁層4dを介して信号配線層4aを多層的に形
成する常套的な薄膜配線部(層)の形成手段、換言する
と薄膜プロセスにおいて、最上層の信号配線層4a′の上
層として、樹脂系絶縁層4dを介してグランド配線層4bを
設けた後、接続用のパッド4cなどを形成するように、そ
の製造工程の一部を変更することにより製造ないし形成
し得る。
A plurality of signal wiring layers 4a including a signal wiring layer electrically connected to the connecting portion 3g by a via hole, a ground wiring layer 4b, and a pad 4c are provided on the ceramic-based laminated wiring portion 3 forming the base substrate. For example, a thin film wiring part 4 is laminated and integrally formed through a resin-based insulating layer 4d such as a polyimide resin.
Is adopted. Here, the thin film wiring part 4
Is a conventional means for forming a thin film wiring portion (layer) that multi-layers the signal wiring layer 4a via the resin-based insulating layer 4d, in other words, in the thin film process, as an upper layer of the uppermost signal wiring layer 4a '. After the ground wiring layer 4b is provided via the resin-based insulating layer 4d, a part of the manufacturing process may be changed so as to form the connection pad 4c or the like.

【0010】なお、本発明に係る多層配線基板は、前記
例示のごとく、薄膜配線部4を形成したセラミック系積
層配線部3の一主面側に入出力ピン3fを導出させずに、
上記図3に示した場合と同様に、入出力ピン3fを他の主
面(裏面)に導出させた構成としてもよい。また、前記
セラミック系積層配線部3においては、信号配線層3cを
内層させず、グランド配線層3aおよび電源配線層3bのみ
を内層させた構成としてもよい。そして、グランド配線
層3aおよび電源配線層3bのみを内層させた構成の場合
は、接続部3gと入出力ピン3fとの間は貫通した形で、直
接電気的に接続されるため、各接続部3gは互いに独立し
て接続パッドとしてのみ機能することになる。したがっ
て、この場合、接続部3gの占める面積(領域)は、セラ
ミック系積層配線部3におけるグランド配線層3aと薄膜
配線部4の信号配線層4aとの間の障害を少なくし、かつ
特性インピーダンスの制御を容易にするため、薄膜配線
部4主面の20%程度以下に設定することが望ましい。
In the multilayer wiring board according to the present invention, as described above, the input / output pin 3f is not led out to the one main surface side of the ceramic type laminated wiring section 3 in which the thin film wiring section 4 is formed,
Similar to the case shown in FIG. 3, the input / output pin 3f may be led out to another main surface (back surface). Further, in the ceramic laminated wiring section 3, the signal wiring layer 3c may not be formed as an inner layer, but only the ground wiring layer 3a and the power supply wiring layer 3b may be formed as inner layers. Then, in the case of the structure in which only the ground wiring layer 3a and the power supply wiring layer 3b are made inner layers, since the connection portion 3g and the input / output pin 3f are directly connected in a penetrating manner, each connection portion The 3g will only function as connection pads independently of each other. Therefore, in this case, the area (region) occupied by the connecting portion 3g reduces the obstacle between the ground wiring layer 3a in the ceramic-based laminated wiring portion 3 and the signal wiring layer 4a in the thin film wiring portion 4, and reduces the characteristic impedance. In order to facilitate control, it is desirable to set it to about 20% or less of the main surface of the thin film wiring portion 4.

【0011】さらに、前記薄膜配線部4の構成におい
て、絶縁層4dはポリイミド樹脂以外のの他の樹脂類、あ
るいは SiO2 など無機物系であってもよいし、さらにグ
ランド配線層3a,4b、電源配線層3b、信号配線配線3c,
4a,4a′、接続部3e,3g、接続用パッド4cなどは、たと
えばAl,Cuなどで形成される。
Further, in the structure of the thin film wiring portion 4, the insulating layer 4d may be made of another resin other than the polyimide resin or an inorganic material such as SiO 2 , and the ground wiring layers 3a and 4b and the power source. Wiring layer 3b, signal wiring wiring 3c,
The parts 4a, 4a ', the connecting parts 3e, 3g, the connecting pad 4c, etc. are formed of, for example, Al, Cu or the like.

【0012】[0012]

【発明の効果】本発明による多層配線基板は、前述のよ
うに、信号配線層がセラミック系積層配線部のグランド
配線層および薄膜配線部のグランド配線層に挟まれた構
成を採っている。つまり、信号配線層は、上下2層のグ
ランド配線層に挟まれたストリップ構造を採っているた
め、信号配線層の特性インピーダンスの制御が容易にな
される。たとえば高速な LSI素子を高密度に実装した場
合、 LSI素子間の実装遅延を最小にする多層配線基板と
して機能することが可能となり、低価格で高機能な MCM
を提供し得ることになる。
As described above, the multilayer wiring board according to the present invention has a structure in which the signal wiring layer is sandwiched between the ground wiring layer of the ceramic laminated wiring portion and the ground wiring layer of the thin film wiring portion. That is, since the signal wiring layer has a strip structure sandwiched between the upper and lower ground wiring layers, the characteristic impedance of the signal wiring layer can be easily controlled. For example, when high-speed LSI elements are mounted in high density, it can function as a multi-layer wiring board that minimizes the mounting delay between LSI elements.
Will be provided.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る多層配線基板の要部構成例を示す
断面図。
FIG. 1 is a cross-sectional view showing a configuration example of a main part of a multilayer wiring board according to the present invention.

【図2】本発明に係る多層配線基板の一部を成すセラミ
ック系積層配線部の要部構成例を示す斜視図。
FIG. 2 is a perspective view showing a configuration example of a main part of a ceramic-based laminated wiring portion forming a part of a multilayer wiring board according to the present invention.

【図3】従来の多層配線基板の要部構造を示す断面図。FIG. 3 is a cross-sectional view showing a main part structure of a conventional multilayer wiring board.

【符号の説明】[Explanation of symbols]

1,3…セラミック系積層配線部 1a、3a,4b…グラ
ンド配線層 1b、3b…電源配線層 1c,2a,3c,4
a,4a′…信号配線層 1d,3d…セラミック絶縁層
1e,3e…ロウ付け用パッド 1f,3f…入出力ピン
1g,3g…接続部 1h…スルホール接続部 2,4…薄膜配線部 2b,
4c…パッド 2c,4d…樹脂系絶縁層 3h…シール用
リング
1, 3 ... Ceramic-based laminated wiring section 1a, 3a, 4b ... Ground wiring layer 1b, 3b ... Power supply wiring layer 1c, 2a, 3c, 4
a, 4a '... Signal wiring layer 1d, 3d ... Ceramic insulating layer
1e, 3e ... Brazing pads 1f, 3f ... I / O pins
1g, 3g ... Connection part 1h ... Through hole connection part 2, 4 ... Thin film wiring part 2b,
4c… Pads 2c, 4d… Resin insulation layer 3h… Sealing ring

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 グランド配線層、電源配線層、および信
号配線層が積層されて成るセラミック系積層配線部と、 前記セラミック系積層配線部上に一体的に形成されたグ
ランド配線層を含む複数の信号配線層から成る薄膜配線
部とを具備して成る多層配線基板であって、 前記薄膜配線部のグランド配線層が信号配線層より上層
に位置し、かつ複数の信号配線層はセラミック系積層配
線部のグランド配線層との間に積層的に配置された構成
を成していることを特徴とする多層配線基板。
1. A plurality of ceramic wiring layers including a ground wiring layer, a power wiring layer, and a signal wiring layer, and a plurality of ground wiring layers integrally formed on the ceramic wiring layer. A multilayer wiring board comprising a thin film wiring portion formed of a signal wiring layer, wherein the ground wiring layer of the thin film wiring portion is located above the signal wiring layer, and the plurality of signal wiring layers are ceramic-based laminated wiring. A multilayer wiring board characterized in that the multilayer wiring board is arranged in a laminated manner with a ground wiring layer of a part.
JP11683293A 1993-05-19 1993-05-19 Multilayer wiring board Expired - Lifetime JP3234045B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11683293A JP3234045B2 (en) 1993-05-19 1993-05-19 Multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11683293A JP3234045B2 (en) 1993-05-19 1993-05-19 Multilayer wiring board

Publications (2)

Publication Number Publication Date
JPH06334347A true JPH06334347A (en) 1994-12-02
JP3234045B2 JP3234045B2 (en) 2001-12-04

Family

ID=14696734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11683293A Expired - Lifetime JP3234045B2 (en) 1993-05-19 1993-05-19 Multilayer wiring board

Country Status (1)

Country Link
JP (1) JP3234045B2 (en)

Also Published As

Publication number Publication date
JP3234045B2 (en) 2001-12-04

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