JPH05136567A - Thin film multilayer wiring board - Google Patents
Thin film multilayer wiring boardInfo
- Publication number
- JPH05136567A JPH05136567A JP29697091A JP29697091A JPH05136567A JP H05136567 A JPH05136567 A JP H05136567A JP 29697091 A JP29697091 A JP 29697091A JP 29697091 A JP29697091 A JP 29697091A JP H05136567 A JPH05136567 A JP H05136567A
- Authority
- JP
- Japan
- Prior art keywords
- layers
- layer
- power supply
- ground
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
Landscapes
- Structure Of Printed Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高速・高機能なシステ
ムを実現する高密度な実装構造の構成に適する薄膜多層
配線基板体に係り、特にマルチチップモジュール用に適
する微細配線の薄膜多層配線基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film multi-layer wiring board suitable for a high-density, high-performance mounting structure that realizes a high-speed, high-performance system, and particularly for fine wiring thin-film multi-layer wiring. Regarding the substrate.
【０００２】[0002]
【従来の技術】クロック周波数が50 MHzを超えるような
高速システムは、高速なLSI 素子の開発だけでは実現で
きない。すなわち、高速なLSI 素子を高密度に実装し、
LSI 素子間の実装遅延を最小にする配線基板が必要であ
る。そして、このような配線基板は、一般に高密度な微
細配線を実現するために、いわゆる薄膜技術によって製
造されている。また、ノイズの発生を最小にするために
図５(a) 〜(c) にそれぞれ要部構造を断面的に示すよう
に、各信号配線層1a,1b をグランド層／電源層2a,2b,2c
で挟んだストリップ構造（図５(a) ）、両信号配線層1
a,1b をグランド層／電源層 2a,2cで挟んだダブル・ス
トリップ構造（図５(b) ）、もしくは両信号配線層 1a,
1bをグランド層／電源層2aの上に配設したマイクロスト
リップ構造（図５(c) ）を採用している。なお、図５
(a) 〜(c) において、3a,3b,3c,3d は前記各信号配線層
1a,1b、グランド層／電源層 2a,2bの層間を絶縁する絶
縁層である。勿論上記の構成においては、信号配線層 1
a,1bは層間絶縁層 3a,3b,3c,3dを貫通する図示されてい
ない接続部（ビアホール）によって、グランド層／電源
層 2a,2b,2c などと所要の電気的な接続が成されてい
る。2. Description of the Related Art A high-speed system whose clock frequency exceeds 50 MHz cannot be realized only by developing high-speed LSI elements. That is, high-speed LSI elements are mounted at high density,
A wiring board that minimizes the mounting delay between LSI elements is required. Such a wiring board is generally manufactured by a so-called thin film technique in order to realize high-density fine wiring. Further, in order to minimize the generation of noise, the signal wiring layers 1a and 1b are connected to the ground layers / power supply layers 2a and 2b, as shown in FIGS. 2c
Strip structure sandwiched between (Fig. 5 (a)), both signal wiring layers 1
Double strip structure in which a and 1b are sandwiched between ground layer / power supply layer 2a and 2c (Fig. 5 (b)), or both signal wiring layers 1a and
A microstrip structure (Fig. 5 (c)) in which 1b is disposed on the ground layer / power supply layer 2a is adopted. Note that FIG.
In (a) to (c), 3a, 3b, 3c, 3d are the signal wiring layers
An insulating layer that insulates the layers 1a and 1b and the ground layer / power supply layer 2a and 2b. Of course, in the above configuration, the signal wiring layer 1
a, 1b are electrically connected to the ground layer / power supply layers 2a, 2b, 2c, etc. by the unillustrated connecting portions (via holes) penetrating the interlayer insulating layers 3a, 3b, 3c, 3d. There is.
【０００３】前記薄膜多層配線基板の構成について詳述
すると、次のような構成を成している。先ず、図５(a)
の構成の場合は、たとえばCu、Alのグランド／電源層2a
面上にたとえばポリイミドの絶縁層3aを形成する。さら
に、たとえばCu、Alの信号層1aのパターン形成、絶縁層
3bの形成というようにして、グランド層／電源層、絶縁
層、信号配線層、絶縁層の順に交互に積層した構成を採
っている。図５(b) の構成の場合は、図５(a) の場合の
中間のグランド層／電源層2bを省略したものであり、図
５(c) の場合は、図５(b) の構成において上層のグラン
ド／電源層2cを省略した構造になっている。そして、薄
膜多層配線基板としての電気特性は図５(a) の構成の場
合が最もすぐれており、以下図５(b) の構成、図５(c)
の構成の順になっている。The structure of the thin-film multilayer wiring board will be described in detail below. First, Fig. 5 (a)
In the case of the above configuration, for example, Cu / Al ground / power supply layer 2a
An insulating layer 3a made of, for example, polyimide is formed on the surface. Further, for example, pattern formation of the signal layer 1a of Cu, Al, an insulating layer
As in the formation of 3b, a structure in which a ground layer / power supply layer, an insulating layer, a signal wiring layer, and an insulating layer are alternately laminated in this order is adopted. In the case of the configuration of FIG. 5 (b), the intermediate ground layer / power supply layer 2b in the case of FIG. 5 (a) is omitted, and in the case of FIG. 5 (c), the configuration of FIG. 5 (b). In the above structure, the upper ground / power supply layer 2c is omitted. The electrical characteristics of the thin-film multilayer wiring board are the best in the case of the configuration of FIG. 5 (a), and the configuration of FIG. 5 (b) and FIG.
The order of the configuration is.
【０００４】[0004]
【発明が解決しようとする課題】しかし、上記構成の薄
膜多層配線基板においては、製造工程からみると逆に図
５(c) の構成の場合、一番工程数が少なく、図５(b) の
構成の場合、図５(a) の構成の場合の順に工程数が増加
する。そして、薄膜多層配線基板の価格は工程数に比例
するので、電気特性を優先するとコストがアップすると
いう問題が生じる。 さらに、実装するLSI 素子がCMOS
などのように単一電源で動作可能な場合は、図５(b) に
図示する構造の薄膜多層配線基板でも対応し得るが、LS
I素子がBiCMOS、ECL などのように複数の電源を必要と
する場合は、図５(a) に図示する構造のように、グラン
ド層／電源層2a,2b …を増やす必要がある。しかしなが
ら、前記指摘したように、図５(a) に図示した構成のご
とく、グランド層／電源層 2a,2b…を増やすことは、製
造工程が増加し繁雑になりコストアップを招来するばか
りでなく、薄膜多層配線基板の厚さなども必然的に増大
してコンパクト化の支障となる。However, in the thin-film multi-layer wiring board having the above-mentioned structure, the number of steps is the smallest in the case of the structure shown in FIG. In the case of the configuration of FIG. 5, the number of steps increases in the order of the configuration of FIG. Since the price of the thin-film multilayer wiring board is proportional to the number of steps, giving priority to the electrical characteristics causes a problem of cost increase. Furthermore, the LSI element to be mounted is CMOS
If it can be operated with a single power supply such as the one shown in Fig. 5 (b), a thin film multilayer wiring board with the structure shown in Fig. 5 (b) can also be used.
When the I element requires multiple power supplies such as BiCMOS and ECL, it is necessary to increase the number of ground layers / power supply layers 2a, 2b ... Like the structure shown in FIG. 5 (a). However, as pointed out above, increasing the number of ground layers / power supply layers 2a, 2b ... As in the configuration shown in FIG. 5 (a) not only causes an increase in the number of manufacturing steps but also makes the cost more expensive. The thickness of the thin-film multilayer wiring board is inevitably increased, which hinders compactness.
【０００５】上記のように、MCM ( マルチチップモジュ
ール）では、ノイズの減少などの電気的特性の向上や、
２電源または３電源の高機能デバイスを搭載してMCM を
高機能化しようとする場合、それらのLSI 素子を搭載・
実装する配線基板の多層配線化は不可避である。したが
って、製造工程の増加などに伴う低価格化が困難である
という問題点を抱えながら、実用に供しているのが実情
である。As described above, in the MCM (multi-chip module), improvement of electrical characteristics such as noise reduction,
If you want to enhance the functionality of MCM by installing high-performance devices with 2 or 3 power supplies, install those LSI elements.
It is inevitable that the wiring board to be mounted has multiple layers. Therefore, in reality, it is put to practical use while having a problem that it is difficult to reduce the price due to an increase in the manufacturing process.
【０００６】本発明は上記事情に対処して成されたもの
で、高機能な MCM( マルチチップモジュール）の構成に
適する薄膜多層配線基板の提供を目的とする。The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a thin-film multilayer wiring board suitable for the construction of a highly functional MCM (multi-chip module).
【０００７】[0007]
【課題を解決するための手段】本発明に係る薄膜多層配
線基板は、グランド層および電源層を含む薄膜配線層と
絶縁層とを交互に積層し、かつ薄膜配線層間が絶縁層を
貫通して選択的に接続されて成る薄膜多層配線基板にお
いて、少なくとも２つのグランド層／電源層が互いに絶
縁離隔して同一層に配設されていることを特徴とする。A thin-film multilayer wiring board according to the present invention comprises a thin-film wiring layer including a ground layer and a power supply layer, and an insulating layer which are alternately laminated, and the thin-film wiring layers penetrate the insulating layer. In the thin-film multilayer wiring board that is selectively connected, at least two ground layers / power supply layers are arranged in the same layer while being insulated and separated from each other.
【０００８】ここで、同一層に配設されるグランド層／
電源層は、櫛の歯が噛み合う形に形成することが好まし
い。また、前記同一層に配設されるグランド層／電源層
が平行に並んだ部分の配線ピッチは、信号配線ピッチの
２倍以下が好ましく、さらにグランド層／電源層の平行
に並んだ部分は、近接する信号配線層の信号配線と斜交
（好ましくは45°）する構成とすることが望ましい。[0008] Here, the ground layer /
The power supply layer is preferably formed in such a manner that the teeth of the comb mesh with each other. Further, the wiring pitch of the portion where the ground layer / power supply layer arranged in parallel in the same layer is preferably not more than twice the signal wiring pitch, and further, the portion where the ground layer / power supply layer arranged in parallel is It is desirable that the signal wirings of the adjacent signal wiring layers intersect obliquely (preferably 45 °).
【０００９】[0009]
【作用】本発明に係る薄膜多層配線基板においては、複
数のグランド層／電源層を同一層内にたとえば櫛の歯を
噛み合せた形に配置してすることにより、グランド層／
電源層の数を増加させずに、実質的にはグランド層／電
源層の数を増加させることが出来る。しかも、必要とす
る箇所近くで容易に所定のグランド層／電源層に信号配
線層を接続できるので、グランド層／電源層への配線も
比較的簡略な構成となる。つまり、MCM の低価格化の実
現に最も効果的な手段である薄膜多層配線基板の構造の
簡素化により、低価格で高機能なMCM の提供が可能とな
った。In the thin-film multilayer wiring board according to the present invention, a plurality of ground layers / power supply layers are arranged in the same layer, for example, in such a manner that the teeth of a comb are engaged with each other.
It is possible to substantially increase the number of ground layers / power supply layers without increasing the number of power supply layers. Moreover, since the signal wiring layer can be easily connected to a predetermined ground layer / power supply layer near the required portion, the wiring to the ground layer / power supply layer also has a relatively simple structure. In other words, by simplifying the structure of the thin-film multi-layer wiring board, which is the most effective means for realizing the low cost of MCMs, it has become possible to provide high-performance MCMs at low prices.
【００１０】[0010]
【実施例】以下図１〜図４を参照して本発明の実施例を
説明する。Embodiments of the present invention will be described below with reference to FIGS.
【００１１】図１は MCM（マルチチップモジュール）の
構成に用る標準的な薄膜多層基板の要部構造を断面的に
示したもので、４はベース基板、たとえばアルミナ基
板、5a、5a′は前記ベース基板４面上に互いに絶縁・離
隔したパターンに形成された第１のグランド層／電源
層、3aは前記グランド層／電源層5a、5a′形成面上に形
成された第１の絶縁層である。そして、前記絶縁層3aに
は、前記グランド層／電源層5aと、絶縁層3a面上に形成
される第１の信号層6aとを接続するための貫通接続部
（ビアホール）7aが形成されている。さらに、前記第１
の信号層6a形成面上には、第２の絶縁層3b、第２の信号
配線層6b、第３の絶縁層3c、第２のグランド層／電源層
5b,5b′、第４の絶縁層3d……と順次積層されて、所要
の薄膜多層基板を構成している。そして、前記絶縁層 3
b,3cには、前記第１の信号層6aと第２の信号配線層6b
間、および第２の信号配線層6bと第２のグランド層／電
源層5b′とをそれぞれ接続するための貫通接続部7b,7c
が形成されている。FIG. 1 is a cross-sectional view showing the structure of a main part of a standard thin film multilayer substrate used in the construction of an MCM (multi-chip module). Reference numeral 4 is a base substrate, for example, an alumina substrate, and 5a and 5a 'are A first ground layer / power supply layer formed on the surface of the base substrate 4 in a pattern insulated and separated from each other, and 3a is a first insulation layer formed on the formation surface of the ground layer / power supply layers 5a and 5a '. Is. The insulating layer 3a is provided with a through connection portion (via hole) 7a for connecting the ground layer / power supply layer 5a and the first signal layer 6a formed on the surface of the insulating layer 3a. There is. Further, the first
The second insulating layer 3b, the second signal wiring layer 6b, the third insulating layer 3c, the second ground layer / power supply layer are formed on the signal layer 6a formation surface of
5b, 5b 'and the fourth insulating layer 3d are sequentially laminated to form a required thin film multilayer substrate. And the insulating layer 3
b and 3c include the first signal layer 6a and the second signal wiring layer 6b.
Through portions 7b and 7c for connecting the second signal wiring layer 6b and the second ground layer / power supply layer 5b ', respectively.
Are formed.
【００１２】ここで、ベース基板１の材料としてはSi、
セラミックスなどでもよいし、絶縁層3a〜3dはポリイミ
ド樹脂、 SiO2 などで形成され、さらに信号配線層 6a,
6b、グランド層／電源層 5a,5a′、 5b,5b′はAl、Cuな
どで形成される。Here, the material of the base substrate 1 is Si,
Ceramics or the like may be used, and the insulating layers 3a to 3d are formed of polyimide resin, SiO 2 or the like, and the signal wiring layer 6a,
6b, the ground layer / power supply layers 5a, 5a ', 5b, 5b' are made of Al, Cu or the like.
【００１３】図２は、図１に図示した構成の薄膜多層配
線基板におけるグランド層／電源層5a,5a ′のパターン
を平面的に示したもので、前記薄膜多層配線のグランド
層／電源層 5a,5a′は、ベース基板４面に櫛の歯が互い
に噛み合った形状に構成されている。このようにグラン
ド層／電源層 5a,5a′を櫛の歯が互いに噛み合った形状
に配設することにより、薄膜多層配線の層数を増やすこ
となくグランド層／電源層の数を容易に増やし得る。ま
た、図１に図示した構成においてのグランド層／電源層
5a,5a′、5b, 5b′をともにそれぞれ櫛の歯が互いに噛
み合った形状に配設２することにより、グランド層／電
源層の数を４に増やすことができる。つまり、薄膜多層
配線基板の価格を上げずに高機能化できる。FIG. 2 is a plan view showing the patterns of the ground layers / power supply layers 5a and 5a 'in the thin film multilayer wiring board having the structure shown in FIG. , 5a 'are formed on the surface of the base substrate 4 so that the teeth of the comb mesh with each other. By arranging the ground layers / power layers 5a and 5a 'in such a shape that the teeth of the comb are intermeshed with each other, the number of ground layers / power layers can be easily increased without increasing the number of thin-film multilayer wiring layers. .. In addition, the ground layer / power supply layer in the configuration shown in FIG.
By arranging 5a, 5a ', 5b, 5b' in such a shape that the teeth of the combs mesh with each other, the number of ground layers / power supply layers can be increased to four. That is, the thin film multilayer wiring board can be highly functionalized without increasing the price.
【００１４】上記のごとく構成された薄膜多層配線基板
上に、所要の LSI素子を、たとえばワイヤーボンディン
グ、TAB(Tape Autmated Bonding)、あるいはフリップチ
ップなどの手段で接続・実装することによって、所望の
MCMを形成し得る。A desired LSI element is connected and mounted on the thin-film multilayer wiring board constructed as described above by means such as wire bonding, TAB (Tape Autmated Bonding), or flip chip, to obtain a desired LSI element.
Can form an MCM.
【００１５】図３はグランド層／電源層 5a,5a′の他の
構成例を斜視的に示したもので、たとえばベース基板４
面上にそれぞれ形成された櫛の歯状のグランド層／電源
層5a, 5a′（ 5b,5b′）を用いて消費電力の大きいデバ
イスへの電源供給を行う場合に適する構成である。すな
わち、櫛の歯の先端部近くより電源の供給を行う場合、
または１本の櫛の歯から多数のデバイス電源供給を行う
場合には、櫛の歯状のグランド層／電源層 5a,5a′（ 5
b,5b′）の配線抵抗などにより、電圧降下を起こすこと
がある。そのような場合には、前記図３に示すようにグ
ランド層／電源層 5a,5a′（ 5b,5b′）の各櫛の歯の先
端部 8a,8bを隣接する信号配線層に設けた接続配線 9a,
9bを使い接続することにより電圧降下が防止できる。櫛
の歯の先端部8aと接続配線9a、および櫛の歯の先端部8b
と接続配線9bとは、それぞれ層間絶縁層（膜）3aに設け
た貫通接続部（ビアホール）7a,7b …よって接続されて
いる。この構成においては、櫛の歯の先端部 8a,8bの接
続は隣接する信号配線層の周辺部で行うので、信号配線
層への影響はほとんどない。FIG. 3 is a perspective view showing another configuration example of the ground layer / power supply layers 5a and 5a '.
This structure is suitable when power is supplied to a device with high power consumption by using the comb-teeth-shaped ground layers / power layers 5a, 5a '(5b, 5b') formed on the respective surfaces. That is, when power is supplied from near the tips of the comb teeth,
Alternatively, when a large number of device power supplies are supplied from one comb tooth, the comb tooth-shaped ground layer / power layer 5a, 5a '(5
A voltage drop may occur due to the wiring resistance of b, 5b '). In such a case, as shown in FIG. 3, the connection of the tip 8a, 8b of each comb tooth of the ground layer / power supply layer 5a, 5a '(5b, 5b') provided on the adjacent signal wiring layer. Wiring 9a,
The voltage drop can be prevented by connecting with 9b. Comb tooth tips 8a and connecting wiring 9a, and comb tooth tips 8b
The connection wiring 9b and the connection wiring 9b are connected by through connection portions (via holes) 7a, 7b, ... Provided in the interlayer insulating layer (film) 3a. In this configuration, since the tip portions 8a and 8b of the comb teeth are connected at the peripheral portion of the adjacent signal wiring layer, there is almost no influence on the signal wiring layer.
【００１６】図４はグランド層／電源層 5a,5a′のさら
に他の構成例を平面的に示したものである。この例は、
２つの櫛の歯状のグランド層／電源層 5a,5a′間にもう
１つのグランド層／電源層5cを配設して、薄膜多層配線
の層数を増やさずにグランド層／電源層の数を増やした
構成例である。この構成の場合も上記の場合と同様に、
薄膜多層配線基板のコストアップを抑制し得ることはい
うまでもなく、また、大きな電力を必要とする場合に
は、前記図３に図示した構成のように隣接する信号配線
層を使い各櫛の歯の先端、グランド層／電源層の湾曲部
を接続すればよい。 なお、上記において同一層に配設
（配置）するグランド層／電源層は、グランド層同士も
しくは電源層同士でもよく、薄膜多層配線の機能ないし
用途などによって任意に選択・設定すればよく、またそ
れらグランド層／電源層の形状も、前記例示の形状に限
定されない。FIG. 4 is a plan view showing still another configuration example of the ground layer / power supply layers 5a and 5a '. This example
The number of ground layers / power supply layers is increased without increasing the number of layers of thin-film multilayer wiring by disposing another ground layer / power supply layer 5c between two comb-shaped ground layers / power supply layers 5a, 5a '. This is a configuration example in which In the case of this configuration, as in the case above,
Needless to say, the cost increase of the thin-film multilayer wiring board can be suppressed, and when a large amount of power is required, the adjacent signal wiring layers are used as in the configuration shown in FIG. It suffices to connect the tips of the teeth and the curved portions of the ground layer / power supply layer. In the above, the ground layers / power supply layers arranged (arranged) in the same layer may be ground layers or power supply layers, and may be arbitrarily selected and set according to the function or application of the thin-film multilayer wiring. The shape of the ground layer / power supply layer is not limited to the above-exemplified shape.
【００１７】[0017]
【発明の効果】本発明によると、前述のように薄膜多層
配線の層数を増やすことなくグランド層／電源層の数を
増やすことができるので、MCM の高機能化など容易に達
成し得る。すなわち、グランド層／電源層の数を増やし
ても薄膜多層配線基板のコストアップを抑制し得るばか
りでなく、グランド層／電源層を櫛の歯が噛み合った形
状に設定した場合は、グランド層／電源層の配線ピッチ
を信号配線の配線ピッチ以下にし得るので、グランド層
／電源層へ接続したい場所も極く近傍で接続できる。し
たがって、信号配線／電源層の配線引き回しに与える影
響を最小限におさえることも可能となる。しかも、製造
工程数も増加しないので、工程の増加による歩留まりの
低下をも防止することができる。According to the present invention, the number of ground layers / power supply layers can be increased without increasing the number of layers of the thin film multilayer wiring as described above, so that it is possible to easily achieve high functionality of the MCM. That is, not only can the cost increase of the thin-film multilayer wiring board be suppressed even if the number of ground layers / power layers is increased, but if the ground layers / power layers are set to have a shape in which the teeth of the comb are engaged, Since the wiring pitch of the power supply layer can be set to be equal to or smaller than the wiring pitch of the signal wiring, it is possible to connect to the ground layer / power supply layer in a very close place. Therefore, it is possible to minimize the influence on the wiring layout of the signal wiring / power supply layer. Moreover, since the number of manufacturing steps does not increase, it is possible to prevent a decrease in yield due to an increase in steps.
【図１】本発明に係る薄膜多層配線基板の要部構成例を
示す断面図。FIG. 1 is a sectional view showing a configuration example of a main part of a thin-film multilayer wiring board according to the present invention.
【図２】本発明に係る薄膜多層配線基板におけるグラン
ド層／電源層の配設（配置）例を示す平面パターン図。FIG. 2 is a plan pattern diagram showing an arrangement (arrangement) of ground layers / power supply layers in the thin-film multilayer wiring board according to the present invention.
【図３】本発明に係る薄膜多層配線基板における他のグ
ランド層／電源層の構成例を示す斜視図。FIG. 3 is a perspective view showing a configuration example of another ground layer / power supply layer in the thin-film multilayer wiring board according to the present invention.
【図４】本発明に係る薄膜多層配線基板における別のグ
ランド層／電源層の構成例を示す平面図。FIG. 4 is a plan view showing a configuration example of another ground layer / power supply layer in the thin-film multilayer wiring board according to the present invention.
【図５】ａ、ｂおよびｃは従来の薄膜多層配線基板のそ
れぞれ異なる構造例を断面図。5A, 5B and 5C are cross-sectional views showing different structural examples of a conventional thin film multilayer wiring board.
1a、1b、6a、6b…信号配線層 2a、2b、2c、5a、5
a′、5b、5b′…グランド層／電源層 3a、3b、3c、3
d…層間絶縁層 ４…ベース基板 7a、7b、7c…貫
通接続部（ビアホール） 8a、8b…櫛形のグランド層
／電源層の先端部 9a、9b…接続配線1a, 1b, 6a, 6b ... Signal wiring layers 2a, 2b, 2c, 5a, 5
a ', 5b, 5b' ... Ground layer / power supply layer 3a, 3b, 3c, 3
d ... Interlayer insulating layer 4 ... Base substrates 7a, 7b, 7c ... Through connection portions (via holes) 8a, 8b ... Comb-shaped ground layer / power supply layer tip portions 9a, 9b ... Connection wiring
Claims (1)
含む薄膜配線層と絶縁層とを交互に積層し、かつ薄膜配
線層間が絶縁層を貫通して選択的に接続されて成る薄膜
多層配線基板において、少なくとも２つのグランド層、
電源層が互いに絶縁離隔して同一層に配設されているこ
とを特徴とする薄膜多層配線基板。1. A thin-film multi-layer wiring, wherein thin-film wiring layers including ground layers / power supply layers and signal wiring layers and insulating layers are alternately laminated, and the thin-film wiring layers are selectively connected through the insulating layers. At least two ground layers on the substrate,
A thin-film multi-layer wiring board, characterized in that the power supply layers are insulated from each other and arranged in the same layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29697091A JPH05136567A (en) | 1991-11-13 | 1991-11-13 | Thin film multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29697091A JPH05136567A (en) | 1991-11-13 | 1991-11-13 | Thin film multilayer wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05136567A true JPH05136567A (en) | 1993-06-01 |
Family
ID=17840564
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29697091A Withdrawn JPH05136567A (en) | 1991-11-13 | 1991-11-13 | Thin film multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05136567A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002118384A (en) * | 2000-08-01 | 2002-04-19 | Mitsubishi Electric Corp | Electronic equipment |
| US6445564B1 (en) | 1999-02-25 | 2002-09-03 | Fujitsu Limited | Power supply bypass capacitor circuit for reducing power supply noise and semiconductor integrated circuit device having the capacitor circuit |
| US6573600B2 (en) | 2000-11-20 | 2003-06-03 | Fujitsu Limited | Multilayer wiring substrate having differential signal wires and a general signal wire in different planes |
| JP2007096212A (en) * | 2005-09-30 | 2007-04-12 | Fujitsu Ltd | Feeder system to power supply pin of electric component |
| JP2011053354A (en) * | 2009-08-31 | 2011-03-17 | Toshiba Corp | Optoelectronic wiring film and optoelectronic wiring module |
-
1991
- 1991-11-13 JP JP29697091A patent/JPH05136567A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6445564B1 (en) | 1999-02-25 | 2002-09-03 | Fujitsu Limited | Power supply bypass capacitor circuit for reducing power supply noise and semiconductor integrated circuit device having the capacitor circuit |
| JP2002118384A (en) * | 2000-08-01 | 2002-04-19 | Mitsubishi Electric Corp | Electronic equipment |
| US6573600B2 (en) | 2000-11-20 | 2003-06-03 | Fujitsu Limited | Multilayer wiring substrate having differential signal wires and a general signal wire in different planes |
| JP2007096212A (en) * | 2005-09-30 | 2007-04-12 | Fujitsu Ltd | Feeder system to power supply pin of electric component |
| JP2011053354A (en) * | 2009-08-31 | 2011-03-17 | Toshiba Corp | Optoelectronic wiring film and optoelectronic wiring module |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100281813B1 (en) | Thermally and electrically enhanced ball grid package | |
| US5136471A (en) | Laminate wiring board | |
| JP4592122B2 (en) | Flip chip package with reduced number of package layers | |
| US4888665A (en) | Customizable circuitry | |
| JP2988075B2 (en) | Semiconductor device | |
| JP2000164765A (en) | Low-crosstalk high-density signal insert having power supply and ground lap and its manufacture | |
| JP2003110084A (en) | Semiconductor device | |
| JP2001015929A (en) | Multilayer board | |
| JPH022699A (en) | High density hybrid integrated circuit | |
| US7057116B2 (en) | Selective reference plane bridge(s) on folded package | |
| JPH06163794A (en) | Multilayer lead frame of metal core type | |
| JP3549714B2 (en) | Semiconductor device | |
| JPH05136567A (en) | Thin film multilayer wiring board | |
| JP2001284488A (en) | Wiring board | |
| JPH06268370A (en) | Thin-film multi-layer wiring board | |
| JP3234045B2 (en) | Multilayer wiring board | |
| JPH0519983B2 (en) | ||
| JP3869220B2 (en) | Semiconductor device | |
| JP3057832B2 (en) | Semiconductor device | |
| JP3692353B2 (en) | Assembling method of semiconductor device | |
| JP3128324B2 (en) | Ceramic multilayer package for semiconductor | |
| JPH0632385B2 (en) | Multilayer wiring board | |
| JPH0685106A (en) | Hybrid semiconductor module | |
| JPS61225842A (en) | Semiconductor device | |
| JPH0855955A (en) | Multilayer substrate for integrated circuit and internal layer substrate for multilayer substrate for integrated circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990204 |