JPH06332403A - Pdp pseudo gradation display circuit - Google Patents

Abstract

PURPOSE:To expand a gradation display range falsely by displaying the present signal and an interpolation signal in a display device for PDP, etc. CONSTITUTION:In a PDP display device which displays an input video signal D1 of (N+2) bits as a signal of high-order N bits, an N-bit adder 1 which generates N-bit interpolation data comprised by carrying high-order N bits by (one), a switching circuit 2 which multiplexes the high-order N bits of present signal data and the N-bit interpolation data by switching by the double rate of a sampling rate, an interpolation control circuit 3 which generates a switch control signal S1 to switch the switching circuit 2 to interpolation data side when the low-order bit of the input video signal data D1 shows (10) or (11), and variable power conversion line memory 4 to convert an interlace signal to a non-interlace signal, are provided and the gradation display range of N-bit display can be expanded faslely by displaying the present signal and the interpolation signal relating to the interpolation data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention displays a current signal and an interpolation signal related to interpolation data in a display device such as a PDP which displays an (N + 2) -bit input video signal in N bits. Thus, the present invention relates to a PDP pseudo gradation display circuit that artificially expands the gradation display range in N-bit display.

[0002]

2. Description of the Related Art In the case of PDP display, the signal supplied to the PDP is a digital signal (pulse drive), unlike the case of a cathode ray tube. Conventionally, the input video signal is (N +
2) When it is composed of bits, a method of driving the PDP with a signal of upper N bits is implemented due to restrictions of the PDP itself and rationalization of the circuit. To describe this as a practical example, even if the input video signal is an 8-bit (N is 6) signal (in this case, 256 gradations), the drive signal of the PDP is a 6-bit (N) signal due to the restriction. (64 gradations in this case). The display method is as shown in FIG.
2 interlaced signals (odd and even fields)
It is written repeatedly and displayed as non-interlaced.
That is, two pixels display data for one pixel. When the input video signal is (N + 2) bits and the PDP drive signal is N bits in the above number of bits, the latter signal gradation reproduction range is 1/4 of the former due to the difference between these 2 bits. This means that the change for each gradation in the case of the N-bit signal is larger than that of the (N + 2) -bit signal, so that an unnatural gradation change may be noticeable depending on the signal content.

[0003]

SUMMARY OF THE INVENTION In order to improve the above-mentioned unnatural gradation change when the PDP drive signal has the same number of bits (N) as in the prior art, the present invention is originally expressed in the N-bit configuration. It is an object of the present invention to provide a PDP pseudo gradation display circuit in which an intermediate gradation that cannot be produced is pseudo-produced so that the gradation change can be seen visually smoothly.

[0004]

SUMMARY OF THE INVENTION The present invention provides a PDP display device adapted to display an input video signal consisting of (N + 2) bits by a signal consisting of upper N bits. In the present signal data, the N-bit adder for creating N-bit interpolated data by incrementing the upper N-bits by "1", and the upper N-bit data and the N-bit interpolated data of the current signal data are sampled at a sampling rate of 2 A switching circuit for switching and multiplexing at a double rate and an interpolation for generating a switching control signal for switching the switching circuit to the interpolation data side when the lower 2 bits of the input video signal data are "10" or "11". It is equipped with a control circuit and a double speed conversion line memory for converting an interlaced signal into a non-interlaced signal. There is provided a PDP pseudo gradation display circuit so as to extend the gray scale display range in a pseudo-N-bit display by displaying the interpolated signal in accordance with the data.

[0005]

In the N-bit adder, the upper N-bit data of the input video signal consisting of (N + 2) bits and the separately generated N-bit data of "1" in decimal notation are added, The added data is used as interpolation data. The switching circuit switches between the signal composed of the upper N bits of the input video signal and the interpolation data. This switching control is based on the switching control signal generated by the interpolation control circuit. The interpolation control circuit selects the interpolation data when the lower 2 bits of the (N + 2) -bit input video signal is "10" or "11", and selects the input video signal itself otherwise. Is switched at a rate twice the sample rate. A signal group consisting of the input video signal itself from the switching circuit and the interpolation data is converted into a non-interlaced signal by the double speed conversion line memory.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A PDP pseudo gradation display circuit according to the present invention will be described below with reference to the drawings. FIG. 1 shows a PDP according to the present invention.
FIG. 2 is a block diagram of an essential part showing an embodiment of the pseudo gradation display circuit, and FIG. 2 is an explanatory diagram for understanding FIG. In addition, in FIG.
FIG. 3 is a circuit diagram for one color of the primary color signal. Therefore, actually, the circuit of FIG. 1 is provided for each color. In FIG. 1, 1 is an N-bit adder, 2 is a switching circuit, 3 is an interpolation control circuit, and 4 is a double speed conversion line memory. D1 is an input video signal composed of (N + 2) bits, D2 is a video signal composed of upper N bits of the D1, and D3 is a signal composed of lower 2 bits of the D1. In this embodiment, the input video signal
It is assumed that D1 is an 8-bit signal and therefore D2 is a 6-bit signal.

Next, the operation of the present invention will be described. The first input terminal (A2 to A7) of the adder 1 has D2, and the second input terminal (B2 to B7) thereof has the same bit number as D2 and is "1" (= 000001) in decimal notation. Is input, and the addition data of both are output to the output terminals (S2 to S7). This addition data becomes interpolation data. Here, the nature of the interpolation data will be described.
When the input video signal D1 is an 8-bit signal, the change range of the gradation level can be expressed as shown in FIG. The upper 6 bits of the D1 become D2, but the least significant bit (D1
Then, the 3rd bit from the lower order is incremented by "1" in every 4 steps of D1, and within the range, it is at the same level (gradation) regardless of the change of the lower 2 bits of D1. This is the reason why the gradation change range of the 6-bit signal becomes narrower than that of the 8-bit signal.

In the present invention, a signal which is carried up (added) by "1" is prepared for the current signal D2, and when the data of the lower 2 bits (= D3) of D1 is "10" or "11", The data (6 bit configuration) carried up by 1 "is selected as a video signal (interpolation data). Of the above, the adder 1 is for obtaining the addition data that is incremented by "1" with respect to the current signal, and the lower 2 bits (=
The switching circuit 2 selectively switches either the current signal or the added data based on the data of D3). Switching circuit 2
For such switching, the first input terminal (A2 to A7)
The current signal D2 to the second input terminal (B2 to B7) of the adder 1
The signals related to the addition data are input. The switching control signal S1 required for switching the switching circuit 2 is generated by the interpolation control circuit 3. In this embodiment, the interpolation control circuit 3 is composed of a NAND gate 3a, a first OR gate 3b and a second OR gate 3c as shown in the figure.

The NAND gate 3a has two lower bits of D1.
The signal D3, which is a bit, the clock signal fs, and the horizontal blanking signal (HBLK) are input to perform a predetermined logical operation. With this circuit configuration, the second OR gate 3c
Output (= output of interpolation control circuit 3) S1 is D3 is “10”
Or, when it is “11”, the “high (H) level” signal is
In other cases (“00” or “01”), “low (L) level” signals are output. Switching circuit 2
D3 is "10" or "1" by this switching control signal S1.
When it is "1", it is switched to the interpolation data (B2 to B7) side and to the current signal D2 (A2 to A7) side otherwise, and output to the output terminals (S2 to S7). This switching is twice the sample rate, that is, 2 fs. This is done so that the previously described two pixels, which have been written twice as one pixel, are displayed for each pixel. The current signal D2 or the interpolation signal D4 selected by the switching circuit 2 is converted by the double speed conversion memory 4 from an interlaced signal to a non-interlaced signal. The frequency of the clock signal supplied to the double speed conversion memory 4 for this non-interlacing is 2 fs.

[0010]

As described above, according to the present invention, the interpolation signal is generated from the current signal and displayed together with the current signal, so that the following effects are produced. FIG. 3 is a diagram conceptually showing a case where the effect of the present invention when D1 is an 8-bit signal and D2 is a 6-bit signal is compared with the conventional method as in the above-mentioned embodiment. In FIG. 3, (A) and (B) are the displays by the conventional method, and (A) is the same as “8” when the gradation (see FIG. 2) of the video signal D1 is “4”. “C” represents the display according to the present invention and represents the case where the signal gradation is “6”. As described above, a 6-bit signal cannot display all 8-bit signals. For example, it is an intermediate gradation such as 6 or 10 of an 8-bit signal. Therefore, the "4" display in (A) is 8
Includes bit signal gradations "4 to 7" and includes "8" in (B)
The display includes the gradation "8 to 11" of the 8-bit signal. Conventionally, writing is performed twice with this gradation. In (C) according to the present invention, when the gray scale of D1 is "6", "4" similar to the conventional method is first displayed as the current signal, and then "8" which is advanced by one gray scale as the interpolation signal. Is displayed. By this display, it seems that the average "6" of both is displayed visually. When this is expressed from the waveform of the signal, as shown in (D),
The same effect as displaying a gradation of "6" that cannot be originally expressed is obtained. That is, according to the present invention, it is possible to expand the reproduction range of gradation. In the embodiment of FIG. 1, the gradation reproduction range of the conventional method can be doubled for each color. Therefore, the total of three colors can be expanded to eight times (about 2 million colors). From the above, the present invention largely contributes to the improvement of the image quality of a display device driven by a digital signal such as a PDP.

[Brief description of drawings]

FIG. 1 is a principal block diagram showing an embodiment of a PDP pseudo gradation display circuit according to the present invention.

FIG. 2 is an explanatory diagram of FIG.

FIG. 3 is a diagram conceptually showing an effect of the PDP pseudo gradation display circuit according to the present invention.

FIG. 4 is a diagram illustrating the principle of conventional PDP display.

[Explanation of symbols]

 1 N-bit adder 2 Switching circuit 3 Interpolation control circuit 4 Double speed conversion line memory 3a NAND gate 3b First OR gate 3c Second OR gate S1 Switching control signal

Claims (2)

[Claims] 1. A PD adapted to display an input video signal composed of (N + 2) bits by a signal composed of upper N bits.
In the P display device, an N-bit adder for creating N-bit interpolated data obtained by moving up the upper N bits of the current signal data in the input video signal composed of the (N + 2) bits by “1”, and the current signal data The upper N-bit data and the N-bit interpolation data are set to the sample rate 2
A switching circuit for switching and multiplexing at a double rate,
An interpolation control circuit for generating a switching control signal for switching the switching circuit to the interpolation data side when the lower 2 bits of the input video signal data is "10" or "11", and for converting an interlaced signal into a non-interlaced signal. A PDP pseudo gradation display characterized by including a double speed conversion line memory, and displaying a current signal and an interpolation signal related to interpolation data to artificially expand a gradation display range in N-bit display. circuit. 2. A clock signal is input to one end of the interpolation control circuit, and the other end is related to the input video signal (N + 2).
A NAND gate to which the data of the lower 2 bits of the bit is input, a first OR gate to which the output signal of the NAND gate is input to one end and a horizontal blanking signal to the other end, and the first OR gate to one end Output signal of
The PDP pseudo gray scale display circuit according to claim 1, wherein the PDP pseudo gray scale display circuit comprises a second OR gate to which the carrier signal in the N-bit adder is input at the other end.