JPH06326591A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To realize a high speed operation and to improve the driving capability of an output transistor by controlling the output voltage of an 'H' level and an 'L' level at the time of a no load state to an absolute value which is smaller than the absolute value of voltage equivalent to a power source. CONSTITUTION:The output voltage of the 'H' level for reference voltage VTT is controlled so that it becomes a voltage level VCC1 which is lower than power source voltage VCC by a power source circuit P1 at the time of the no load state. On the other hand, the output voltage of the 'L' level is controlled so that it becomes a voltage level VSS1 which is higher than power source voltage VSS. Thus, the source potential of output transistors Q1 and Q2 is suitably selected and the on-resistance of Q1 and Q2 can freely be selected. Thus, the driving capability of the transistor is improved without damaging a small amplitude operation for high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit adapted to perform a small amplitude operation for high speed operation, which is provided in an output stage of an LSI chip and drives an external device or the like. Output circuit configuration. The output circuit according to the present invention can be suitably used as an inter-chip input / output interface on a board on which a plurality of LSI chips are mounted, for example.

Conventionally, the input / output level of an LSI is TTL or L.
VTTL (interface specification of 3.3V power supply standardized by JEDEC) was generally used, but the transfer data (input / output data) frequency is 50M at this level.
From around about Hz, the influence of signal reflection becomes large, and waveform distortion due to ringing or the like occurs and normal data transfer cannot be performed. Therefore, the amplitude of transfer data is ± 3
Attention has been focused on a technology for miniaturizing the voltage to about 00 to ± 500 mV. This technique enables high-speed data transfer at 100 MHz or more, which is far higher than 50 MHz.

[0003]

2. Description of the Related Art FIG. 13 shows an application example of a conventional output circuit. The illustrated example shows a configuration applied to an input / output interface between LSI chips. An output circuit is provided on one chip and a high potential power supply line V is provided.
It is composed of a CMOS transistor (p-channel transistor Q1, n-channel transistor Q2) connected between _CC (5V) and a low potential power supply line V _SS (0V). Further, on the other chip, a differential amplifier DA for processing a signal V _IN (the same potential as the output signal V _OUT of the output circuit in the steady state) input through a transmission line TML connecting between the chips, and a termination. A resistor RT and the like are provided. This terminating resistor RT is necessary to operate the output circuit at high speed and to prevent waveform distortion due to signal reflection, and is set to the same impedance as the intrinsic impedance of the transmission line TML. There is. On the receiving side, the terminal voltage V _TT is set by the differential amplifier DA.
It is detected whether the input signal V _IN is high or low with respect to (= V _CC / 2).

In the configuration shown, the output circuits (Q1, Q
When the signal input to 2) (the signal of the node N1) is at "L" level, the p-channel transistor Q1 is turned on, a current flows through the path of V _CC → Q1 → RT → V _TT , and the input signal V _IN Is higher than the termination voltage V _TT . on the other hand,
When the input signal of the output circuit is "H" level, the n-channel transistor Q2 is turned on, and conversely V _TT → RT → Q
A current flows through the path of 2 → V _SS , and the level of the input signal V _IN becomes lower than the termination voltage V _TT .

[0005]

In order to perform high-speed operation in the above-mentioned conventional structure, input / output signals V _OUT, V _IN
The voltage (at the same potential in the steady state) needs to be suppressed to about V _TT ± 400 mV. Here, the termination resistor RT is determined by the impedance of the transmission line TML (normally 50
.OMEGA.), The on resistance of each of the transistors Q1 and Q2 of the output circuit is naturally determined. That is, since the size of each of the transistors Q1 and Q2 is uniquely determined, the transistors Q1 and Q2 have a driving capability corresponding to the size.

Therefore, for example, one chip (output circuit)
However, even if it is desired to drive a plurality of other chips, the driving capability of the output circuit is limited, so that it becomes extremely difficult to drive all the chips to be driven at high speed. In this way, in the conventional output circuit, when trying to realize a small amplitude operation for speeding up,
There is a problem in that the output transistors cannot be made larger than necessary, and as a result, the driving capability of each transistor is relatively reduced.

The present invention was created in view of the above problems in the prior art, and it is an object of the present invention to provide a semiconductor integrated circuit having an output circuit capable of realizing high-speed operation and enhancing the driving capability of an output transistor. To aim.

[0008]

In order to solve the above problems, the semiconductor integrated circuit according to the present invention has a first output voltage and an "L" level which define an "H" level with respect to a predetermined reference voltage.
An output circuit that provides a second output voltage that defines a level, and the first and second output voltages in a substantially unloaded state have absolute values that are smaller than the absolute value of the power supply equivalent voltage, respectively. And a means for controlling the voltage level to a predetermined voltage level.

[0009]

According to the above-described structure, the first output voltage ("H" level) and the second output voltage ("L" level) in the substantially no-load state are respectively the absolute value of the power supply equivalent voltage. It is controlled to have an absolute value smaller than the value. Therefore, for example, when the output circuit is composed of a typical CMOS transistor, by appropriately selecting the source potential of each transistor (in this case, a voltage level having an absolute value smaller than the absolute value of the power supply equivalent voltage), The on-resistance of the output transistor, and thus the drive capability of the transistor, can be freely selected.

As a result, the driving capability of the output transistor can be increased without impairing the small-amplitude operation for speeding up. Further, when there is no terminating resistor (when it is desired to eliminate the DC current), the small amplitude operation cannot be performed in the conventional circuit. However, according to the circuit configuration of the present invention, even if there is no terminating resistor, a small amplitude operation is possible. It is possible to realize the operation, that is, the high speed operation.

The details of other structural features and operations of the present invention will be described with reference to the embodiments described below with reference to the accompanying drawings.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the structure of a main part of a semiconductor integrated circuit, that is, an output circuit, as a first embodiment of the present invention. The circuit shown in the figure has a power supply circuit P1 that receives a high-potential power supply voltage V _CC (5 V) and a predetermined reference voltage V _TT to generate a high-potential internal power supply voltage V _CC1 (<V _CC ), and a low-potential circuit. Power supply circuit P2 that generates a low-potential internal power supply voltage V _SS1 (> V _SS ) by receiving the power supply voltage V _SS (0 V) and the reference voltage V _TT of each of the power supply circuits P1 and P2 (internal A CMOS-structure transistor (p-channel transistor Q1 and n-channel transistor Q2) connected between the power supply voltages V _CC1 and V _SS1 ) and a power supply line V
Connected between _CC1, V _SS1 to and a capacitor C for stabilizing the supply voltage V _CC1, V _SS1. The output transistors Q1 and Q2 function as a driving circuit and provide an output voltage V _OUT . The reference voltage V _TT is internally generated and set to V _CC / 2.

When the circuit configuration of this embodiment is applied to the configuration of FIG. 13, the internal power supply voltages V _CC1 and V _SS1 to be supplied from the power supply circuits P1 and P2 are the same as the resistance value of the terminating resistor RT. It is determined from the voltages of the output signals V _{OUT and} V _IN and the driving ability (ON resistance) of the output transistors Q1 and Q2.
For example, the internal power supply voltage V _SS1 on the low potential side is set under the following conditions,
That is, assuming that the resistance value of the terminating resistor RT is 50Ω, the voltages of the input / output signals V _{OUT and} V _IN are V _TT -400 mV, and the on-resistances of the output transistors Q1 and Q2 are 25Ω, V
_SS1 is set to (V _TT -600 mV).

FIG. 2 shows an example of the configuration of the power supply circuit.
The illustrated power supply circuit has a power supply line V _CC and a reference voltage line V
Resistors R1, R1 'and n connected in series between _TT
The gate is connected to the connection point (node N2) of the channel transistor Q3 (the gate of which is connected to the drain) and the resistors R1 and R1 ′, and the power supply line V _CC.
And an n-channel transistor Q4 whose drain is connected to. Then, the internal power supply voltage V _CC1 having a higher potential is taken out from the source terminal of the transistor Q4.

In the example shown in FIG. 2, the power supply circuit P on the high potential side is shown.
However, it is possible for those skilled in the art to similarly configure the power supply circuit P2 on the low potential side by replacing the corresponding power supply lines V _CC and V _CC1 with V _SS and V _SS1 , respectively. Would be obvious to. For reference, FIG. 3 shows operation waveforms of the circuit shown in FIG.

According to the configuration of the first embodiment (FIG. 1), the output voltage V _OH at the "H" level is lower than the power supply voltage V _{CC in} the no-load state (that is, when there is no termination in FIG. 13). Control is performed so that the voltage level becomes low _CC V1 and the output voltage V _OL at "L" level becomes voltage level V _SS1 higher than the power supply voltage V _SS . Therefore, by appropriately selecting the source potentials of the output transistors Q1 and Q2, that is, the internal power supply voltages V _CC1 and V _SS1 , it is possible to freely select the ON resistance of each output transistor, that is, the driving capability.

As a result, the driving capability of the output transistors Q1 and Q2 can be enhanced without impairing the small-amplitude operation for speeding up. FIG. 4 shows the second embodiment of the present invention.
A configuration of a main part of a semiconductor integrated circuit as an example, that is, an output circuit is shown. In the above-described first embodiment (FIG. 1), since a relatively large current flows through the output transistors Q1 and Q2 during operation, the internal power supply voltages V _CC1 and V _SS1
In order to suppress the level fluctuation of the power supply circuits P1 and P2, it is necessary to increase the capacitance of the power supply circuits P1 and P2. The second embodiment is improved so that the capacity of the power supply circuit used can be reduced.

That is, as shown in FIG. 4, the output circuit in this embodiment receives a power supply voltage V _CC and a reference voltage V _TT to generate a high potential internal power supply voltage V _CC2 (<V _CC ). Circuit P3, power supply voltage V _SS and reference voltage V _TT
Is connected between the power supply circuit P4 that generates a low potential internal power supply voltage V _SS2 (> V _SS ) and each output line (internal power supply voltage V _CC2 , V _SS2 ) of the power supply circuits P3 and P4. CM
OS configuration transistor (p-channel transistor Q5
And n-channel transistor Q6), and a CMOS transistor (n-channel transistor Q7 and p-channel transistor Q8) which is responsive to the output of the transistor (signal of node N3) and is connected between power supply lines V _CC and V _SS. have. And this last stage C
The output voltage V _OUT is taken out from the MOS gates (Q7, Q8).

The feature of this embodiment is that the final stage CMO is
With respect to the S gate, a connection configuration opposite to the normal one, that is, n
The channel transistor Q7 is connected to the high potential (V _CC ) side, and the p-channel transistor Q8 is connected to the low potential (V _SS ) side. According to this configuration, the source potential of the transistor Q7, that is, the output voltage V _OUT is the CMO of the preceding stage.
It is determined by a voltage value that is lower than the output voltage (signal of the node N3) of the S gates (Q5, Q6) by the threshold voltage of the transistor Q7. Therefore, the current for driving the output flows through the path of V _CC → Q7 → OUT, and the problem of the first embodiment (FIG. 1) described above can be avoided.

FIG. 5 shows an example of the configuration of the power supply circuit.
The illustrated power supply circuit has a power supply line V _CC and a reference voltage line V
Resistors R2, R2 'and n connected in series between _TT
Channel transistors Q9 and Q10 (each gate connected to a corresponding drain) and resistors R2 and R2 '.
An n-channel transistor Q11 having a gate connected to the connection point (node N2 ') and a drain connected to the power supply line V _CC . Then, the internal power supply voltage V _CC2 having a higher potential is taken out from the source terminal of the transistor Q11.

Note that the illustration of FIG. 5 shows the configuration of the power supply circuit P3 on the high potential side as in the case of FIG. 2, but the corresponding power supply lines V _CC and V _CC2 are connected to V _SS and V _SS , respectively.
By replacing with V _SS2 , the power supply circuit P on the low potential side
It will be apparent to those skilled in the art that 4 can be similarly configured. For reference, FIG. 6 shows operation waveforms of the circuit of FIG.

FIG. 7 shows the structure of the main part of the semiconductor integrated circuit as the third embodiment of the present invention, that is, the output circuit. In the above-described second embodiment (FIG. 4), the output of the CMOS gates (Q5, Q6) (the signal of the node N3) swings between the voltage levels V _CC2 and V _SS2 (see FIG. 6). However, the final CMOS gate (transistors Q7, Q
Considering the operation of 8), the n-channel transistor Q7 can be sufficiently cut off without lowering the potential of the node N3 to the level of V _SS2 , and the potential of the node N3 must be raised to the level of V _CC2. Also, the p-channel transistor Q8 can be sufficiently cut off. Therefore, for higher speed operation, it is preferable to reduce the amplitude of the gate potential of the output transistors Q7 and Q8. This third
In the embodiment, this inconvenience is remedied.

That is, as shown in FIG. 7, as a feature of this embodiment, the gate voltages of the output transistors Q7 and Q8 are separately supplied. For this reason,
Regarding the MOS circuit portion, two sets of CMOS gates (p-channel transistor Q12 and n-channel transistor Q13 and p-channel transistor Q14 and n-channel transistor Q15) are provided, and the reference voltage V _TT is supplied to the sources of the transistors Q13 and Q14. A reference voltage power supply circuit P5 is provided for this purpose.

FIG. 8 shows a configuration example of the reference voltage power supply circuit P5. The illustrated reference voltage power supply circuit includes resistors R connected in series between power supply lines V _CC and V _SS.
3, p-channel transistor Q16 (its gate is connected to the source), n-channel transistor Q17
(Its gate is connected to the source), and resistor R4 and the source of transistor Q16 (node N6).
A p-channel transistor Q18 having a gate connected to the power supply line V _CC and a source connected to the power supply line V _CC , and an n-channel transistor Q19 having a gate connected to the source (node N7) of the transistor Q17 and a source connected to the power supply line V _SS. And have. And the transistor Q
The reference voltage V _TT is input to the drains of 16 and Q17,
The reference voltage V _TT is taken out from each drain of the transistors Q18 and Q19.

For reference, operation waveforms of the circuit of FIG. 7 are shown in FIG. FIG. 10 shows a main part of a semiconductor integrated circuit as a fourth embodiment of the present invention, that is, a configuration of a power supply circuit. In each of the above-described embodiments, the terminating resistance has been described as always having a constant value (for example, 50Ω).
The terminating resistance is not always a constant value. If it is desired to eliminate the direct current, there may be no terminating resistor. In such a case, for example, in the second embodiment (see FIGS. 4 and 5), the potentials of the internal power supply voltages V _CC2 and V _SS2 vary depending on the presence or absence of the terminating resistor. This inconvenience is improved in the fourth embodiment.

That is, as shown in FIG. 10, a feature of this embodiment is that the voltage level of the internal power supply voltage V _CC2 can be controlled based on information that can be arbitrarily set from the outside. To this end, instead of the resistors R2, R2 ′ in FIG. 5, a plurality of resistors (3 in the example shown for simplification)
Only one resistor R5-R7) and a plurality of n-channel transistors Q20-Q22 connected between the connection point of each resistor and the gate of transistor Q11.
And control information from outside (a row address strobe signal RASX, a column address strobe signal CASX, a write enable signal WEX, a reference voltage V _REF (this may be generated internally), a clock signal CLK,
Each transistor Q20 based on the address signal ADD)
~ Output level control circuit O for selectively turning on / off Q22
LC is provided.

FIG. 11 shows an example of the structure of the output level control circuit OLC, and FIG. 12 shows its operation waveform.
The example of FIG. 12 shows operation waveforms when data (D) is written from the outside, and in this example, synchronous DR
It is illustrated assuming AM. Synchronous DRAM
Operates in synchronization with the rising edge of the clock signal CLK. Immediately after power-on, at clock 0, the row address strobe signal RASX, the column address strobe signal CASX, and the write enable signal WEX
Are all set to the "L" level, the output condition setting mode is set. At this time, the address signal ADD is input to each address input terminal.
And set. Once the output conditions are set, it is basically a normal DRA except that it is synchronized with the clock signal.
The same operation as M is performed, and column selection and writing / reading are performed.

The circuit shown in FIG. 11 is for realizing this. In the figure, DA _{0 to} DA ₆ denote differential amplifiers, and each input signal CL with respect to the reference voltage V _REF (= 1.5 V).
It is detected whether K, RASX, CASX, WEX, A _{0 to} An are high or low. Output phi ₀ of the differential amplifier DA ₀ is input to each gate G ₀ ~G _5, the differential amplifier DA ₁ to DA ₆
Latch each output φ _{1 to} φ ₆ . Then the gate G ₆
Signal φ corresponding to RASX _, CASX and WEX
It is detected that ₁ , φ ₂ and φ ₃ are all at the “L” level, and the gates G _{7 to} G ₉ are opened by the output NG. As a result, the information A _{0 to} An at the address input terminal is latched in the corresponding flip-flops FF _{0 to} FFn via the switches SW _{0 to} SWn, respectively. The latched data is output to the nodes N8 to N10, and the transistor Q
It is supplied to each gate of 20 to Q22 (see FIG. 10).

On the other hand, in addition to this, a function of fixedly storing by a fuse is also prepared. To this end, fuses F _{0 to} Fn and Fx are provided, and the fuses F _{0 to} Fn store information to be sent to the nodes N8 to N10.
Information for switching each of the switches SW _{0 to} SWn to the fuse side is stored in x. Each fuse F ₀ ~
Fn and Fx can be arbitrarily cut by irradiating ultraviolet rays from the outside.

As described above, according to the circuit configuration shown in FIG. 11, it is possible to arbitrarily set an output condition from the outside and also to store the output condition fixedly by using a fuse. Therefore, according to the fourth embodiment (see FIGS. 10 to 12),
It is possible to appropriately select the potentials of the internal power supply voltages V _CC2 and V _SS2 according to the presence or absence of the terminating resistor or the fluctuation thereof.

In the fourth embodiment, the structure of the power supply circuit is described in comparison with the second embodiment (see FIGS. 4 and 5). However, the power supply circuit used in the fourth embodiment is the first embodiment. (Fig. 1,
It will be apparent to those skilled in the art that the same applies to (see FIG. 2).

[0032]

As described above, according to the present invention, it is possible to enhance the driving capability of the output transistor while realizing a small amplitude operation for speeding up. Further, even if there is no terminating resistor, it is possible to realize a small amplitude operation.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a main part of a semiconductor integrated circuit as a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a power supply circuit in FIG.

FIG. 3 is an operation waveform diagram of the circuit of FIG.

FIG. 4 is a circuit diagram showing a configuration of a main part of a semiconductor integrated circuit as a second embodiment of the present invention.

5 is a circuit diagram showing a configuration example of a power supply circuit in FIG.

6 is an operation waveform diagram of the circuit of FIG.

FIG. 7 is a circuit diagram showing a configuration of a main part of a semiconductor integrated circuit as a third embodiment of the present invention.

8 is a circuit diagram showing a configuration example of a reference voltage power supply circuit in FIG.

9 is an operation waveform diagram of the circuit of FIG.

FIG. 10 is a circuit diagram showing a configuration of a main part of a semiconductor integrated circuit as a fourth embodiment of the present invention.

11 is a circuit diagram showing a configuration example of an output level control circuit in FIG.

12 is an operation waveform diagram of the circuit of FIG.

FIG. 13 is a diagram illustrating an application example of a conventional output circuit.

[Explanation of symbols]

OLC ... Output level control circuit P1-P5 ... Power supply circuit Q1, Q5, Q8, Q12, Q14 ... P-channel transistor Q2, Q6, Q7, Q13, Q15, Q20, Q21,
Q22 ... n-channel transistors V _CC , V _SS ... Power supply equivalent voltage (external power supply voltage) V _CC2, V _SS2 ... Power supply equivalent voltage V _OH ... First output voltage (V _OUT ) V _OL ... Second output voltage (V _OUT ) V _TT that defines the “L” level ... Predetermined reference voltage (= V _CC / 2)

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03K 19/017 8321-5J

Claims (8)

[Claims] 1. A “H” with respect to a predetermined reference voltage (V _TT ).
An output circuit providing a first output voltage (V _OH ) defining a level and a second output voltage (V _OL ) defining an "L"level; and the first and The second output voltages are respectively converted into power supply equivalent voltages (V _CC , V _SS ; V _CC2, V
_And a means for controlling to a predetermined voltage level having an absolute value smaller than the absolute value of ( _SS2 ). 2. The output circuit comprises an external power supply voltage (V _CC ,
V _SS ) and the predetermined reference voltage to generate an internal power supply voltage smaller than the external power supply voltage (P1, P2; P3, P4), and the internal power supply voltage to supply the internal power supply voltage. 2. The semiconductor integrated circuit according to claim 1, further comprising a drive circuit that provides first and second output voltages. 3. The drive circuit includes a CMOS circuit section (Q5, Q) which operates by receiving the supply of the internal power supply voltage.
6; Q12 to Q15), an n-channel transistor (Q7) that provides the first output voltage in response to the output of the circuit section, and the second output voltage in response to the output of the circuit section. The p-channel transistor (Q8) provided is provided, The semiconductor integrated circuit of Claim 2 characterized by the above-mentioned. 4. The circuit section having the CMOS structure has a set of transistors (Q5, Q6) having the CMOS structure which are operated by receiving the supply of the internal power supply voltage, and the n-th transistor is provided by the output of the transistor having the CMOS structure. The semiconductor integrated circuit according to claim 3, wherein the gate potentials of the channel transistor and the p-channel transistor are commonly controlled. 5. The CMOS circuit section has two sets of CMOS transistors (Q12 to Q15) connected in series that are operated by receiving the supply of the internal power supply voltage, and one of the CMOS transistors is formed. 4. The semiconductor integrated circuit according to claim 3, wherein the gate potential of the n-channel transistor is controlled by the output of the n-channel transistor, and the gate potential of the p-channel transistor is controlled by the output of the other CMOS transistor. 6. The power supply circuit (P5) according to claim 5, further comprising a power supply circuit (P5) for supplying the reference voltage to a connection point between the one CMOS-structure transistor and the other CMOS-structure transistor. Semiconductor integrated circuit. 7. The power supply circuit comprises a plurality of resistors (R5 to R) connected between lines of an external power supply voltage and the reference voltage.
7) and switch means (Q20 to Q22) for selectively selecting a plurality of voltage levels divided by the resistors,
A circuit (OLC) for controlling on / off of the switch means based on control information from the outside, and variably controlling the voltage level of the internal power supply voltage based on the control information from the outside. The semiconductor integrated circuit according to any one of claims 2 to 6. 8. The predetermined reference voltage (V _TT ) is internally generated and is set to an intermediate potential between the external power supply voltages (V _CC , V _SS ). The semiconductor integrated circuit according to claim 1.