JPH06326359A - Semiconductor light emission/detection device and its manufacture - Google Patents

Semiconductor light emission/detection device and its manufacture

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JPH06326359A
JPH06326359A JP3967894A JP3967894A JPH06326359A JP H06326359 A JPH06326359 A JP H06326359A JP 3967894 A JP3967894 A JP 3967894A JP 3967894 A JP3967894 A JP 3967894A JP H06326359 A JPH06326359 A JP H06326359A
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light emitting
semiconductor light
detecting device
manufacturing
method
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JP2559999B2 (en
Inventor
Jonathan D Chapple-Sokol
Seshadri Subbanna
Manu J Tejwani
ジョナサン・ダニエル・チャップル−ソコル
セシャドリ・サバンナ
マニュ・ジャムナダス・テジュワニ
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Internatl Business Mach Corp <Ibm>
インターナショナル・ビジネス・マシーンズ・コーポレイション
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y20/00Nanooptics, e.g. quantum optics or photonic crystals
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS, OR APPARATUS
    • G02B6/00Light guides
    • G02B6/24Coupling light guides
    • G02B6/42Coupling light guides with opto-electronic elements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L31/00Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L31/00Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • H01L31/101Devices sensitive to infra-red, visible or ultra-violet radiation
    • H01L31/102Devices sensitive to infra-red, visible or ultra-violet radiation characterised by only one potential barrier or surface barrier
    • H01L31/105Devices sensitive to infra-red, visible or ultra-violet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26Materials of the light emitting region
    • H01L33/34Materials of the light emitting region containing only elements of group IV of the periodic system
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/099LED, multicolor
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/962Quantum dots and lines

Abstract

PURPOSE: To provide a semiconductor light emission/detection device which realizes the optical interconnection in a silicon base semiconductor device. CONSTITUTION: A semiconductor light emission/detection device comprises the first doped silicon layer 10, the first intrinsic silicon epitaxial layer 15 formed on the layer 10, at least one quantum dot 20 buried in the intrinsic silicon epitaxial layer 15 and the second doped silicon layer 30 formed on the second intrinsic silicon epitaxial layer 25.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は、一般的に半導体デバイスに関し、特に、半導体デバイスの光相互接続に関する。 The present invention relates generally to semiconductor devices, and more particularly, to an optical interconnection of semiconductor devices.

【0002】 [0002]

【従来の技術】半導体集積回路技術の進歩にしたがって、回路設計者は、回路性能を改良をするために絶え間ぬ努力をしてきた。 In accordance with the progress of a semiconductor integrated circuit technology, circuit designers, it has been a constant bran effort in order to improve the circuit performance. 回路性能を著しく改良できる1つの方策は、回路速度の増大である。 One strategy that can significantly improve the circuit performance is an increase in circuit speed. 回路速度は、構成要素および/またはチップ間の相互接続を改良することにより増大できる。 Circuit speed can be increased by improving the interconnection between components and / or chips. 伝統的には、一般の配線が、このような相互接続に使用されてきた。 Traditionally, common wiring have been used for such interconnection. 一般の配線方法に共通に関連する欠点は、過度のノイズ,著しい遅延時間,クロストーク等を含む。 Disadvantages associated with the common wiring method generally, excessive noise, a significant delay, including crosstalk. 相互接続を改良することにより回路速度を最適化しようとする場合、これらの欠点は、回路速度悪影響を及ぼすことがあり、それ故、集積回路設計者により考慮されねばならない。 When trying to optimize circuit speed by improving the interconnection, these disadvantages, may adversely circuit speed adversely, therefore, must be taken into account by the integrated circuit designer.

【0003】一般の配線への代替案は、光接続である。 [0003] Alternatively to the general interconnect is an optical connection.
一般の配線に関連する欠点の多くは、光相互接続について存在せず、それ故、光相互接続は、回路速度を増大できる。 Many of the drawbacks associated with the common wiring, absent for optical interconnects, therefore, the optical interconnect can increase circuit speed. 従って、光相互接続の利用は、半導体回路性能を増大し、改良することを追及する回路設計者にとって興味がある。 Therefore, the use of optical interconnects increases the semiconductor circuit performance, there is interest for circuit designers to pursue to improve.

【0004】光相互接続は、III−V族半導体技術、 [0004] The optical interconnects, III-V group semiconductor technology,
特に、ガリウム砒素ベース(based)の技術の直接バンドギャップ材料を用いて以前から実行されてきた。 In particular, it has been performed previously using a direct bandgap material technology gallium arsenide base (based).
実際には、GaAsベースの技術において、光接続の使用は、周知の、ありふれたものであり、配線に関する上記略述した問題を排除することにより、配線より更に速く動作しおよび配線より更に効果的に機能することが証明されてきた。 In fact, in the GaAs based technology, the use of optical connections, known is commonplace, by eliminating the problems outlined above relating to wire, it operates faster than the wiring and more effective than the wiring it has been proven to function. この点に関し、直接バンドギャップ材料を、容易にレーザ放射または発光するようにして、光相互接続を形成できることがGaAsベースの技術において明らかにされてきた。 In this regard, the direct band gap material, readily so as to laser radiation or light emitting, it is possible to form the optical interconnect have been demonstrated in GaAs based technology.

【0005】しかしながら、III−V族半導体技術の直接バンドギャップ材料と対照的に、IV族半導体技術、バイポーラまたはCMOSのような特にシリコンベースの技術の間接バンドギャップ材料で光相互接続は容易に実現されない。 However, in contrast to the direct band gap material of the III-V semiconductor technology, IV group semiconductor technology, optical interconnects in an indirect bandgap material, especially silicon-based technologies such as bipolar or CMOS is easily realized not. 間接バンドギャップ材料は通常は発光しないので、このような材料から発光デバイスまたは光相互接続を作ることは特に困難である。 Since the indirect bandgap material typically does not emit light, it is especially difficult to make the light emitting device or optical interconnect of such a material.

【0006】特に、2次元Si−Ge量子井戸は発光能力を有しないことが明らかであるので、1次元または量子ドット(dots)(0次元)が、Si−Geベースの技術において要求される。 [0006] In particular, two-dimensional Si-Ge quantum wells since it is clear that not have an emission capacity, one-dimensional or quantum dots (dots) (0-dimensional), is required in Si-Ge-based technology. 例えば、量子ドットの存在を示す、SiO 2に埋込まれたGeの微細結晶からのルミネッセンスを論じている、20th Interna For example, indicating the presence of the quantum dots, it discusses the luminescence from the fine crystals of Ge embedded in SiO 2, 20th Interna
tional Confarence on the tional Confarence on the
Physics ofSemiconductors, Physics ofSemiconductors,
Vol. Vol. 3,pp2375−2378(1990)の“Quantum Dots of Ge Embed 3, "Quantum Dots of Ge Embed of pp2375-2378 (1990)
ded inSiO 2 Thin Film:Opti ded inSiO 2 Thin Film: Opti
cal Properties”を参照されたい。 See cal Properties ".

【0007】シリコンは、今日の半導体技術において使用された最初の材料であるので、シリコン半導体技術において回路速度を改良する、相互接続の改良のような、 [0007] Silicon, since the first material used in semiconductor technology today to improve the circuit speed in silicon semiconductor technology, such as the improvement of the interconnection,
いかなる方策も極めて望ましいものである。 Any strategy is also highly desirable. 従って、シリコンベースの半導体技術において、光相互接続、それ故、発光/検出デバイスの必要性が存在する。 Thus, the silicon-based semiconductor technology, optical interconnects, therefore, there is a need for a light emitting / detecting devices.

【0008】 [0008]

【発明が解決しようとする課題】それ故、本発明の目的は、シリコンベースの半導体回路/サブシステムの性能を改良することにある。 [SUMMARY OF THE INVENTION It is therefore an object of the present invention to improve the performance of silicon-based semiconductor circuit / subsystem.

【0009】本発明の他の目的は、高速のシリコンベースの半導体回路を提供することにある。 Another object of the present invention is to provide a high speed silicon-based semiconductor circuit.

【0010】本発明の更なる目的は、シリコンベースの半導体デバイスにおける相互接続を改良することにある。 It is a further object of the present invention is to improve the interconnects in silicon-based semiconductor devices.

【0011】本発明の更に他の目的は、シリコンベースの半導体デバイスにおける光相互接続を提供することにある。 A further object of the present invention is to provide an optical interconnects in silicon-based semiconductor devices.

【0012】 [0012]

【課題を解決するための手段】前述の目的を達成するために、半導体発光/検出デバイスおよびその製造方法が提供される。 To SUMMARY OF THE INVENTION To achieve the foregoing object, a semiconductor light emitting / detecting device and a method for producing the same. 半導体発光/検出デバイスは、第1のドープシリコン層と、第1のドープシリコン層上に形成された真性シリコン・エピタキシャル層とを有する。 The semiconductor light emitting / detecting device comprises a first doped silicon layer, and intrinsic silicon epitaxial layer formed on the first doped silicon layer. 少なくとも1つの量子ドットが、第1の真性シリコン・エピタキシャル層内に埋込まれ、導電型が第1のドープシリコンの導電型と反対の第2のドープシリコン層が、第2の真性シリコン・エピタキシャル層上に形成される。 At least one quantum dot, embedded in the first intrinsic silicon epitaxial layer, the second doped silicon layer of conductivity type opposite to the conductivity type of the first doped silicon, a second intrinsic silicon epitaxial It is formed on the layer.

【0013】半導体発光/検出デバイスが製造される基板は、デバイスへの電気的接触が必要とされるか、またはデバイスの分離が必要とされるかによって、第1または第2のシリコン層の導電型とすることができる。 [0013] substrate having a semiconductor light emitting / detecting devices are manufactured, depending on whether electrical contact to the device is required, or the device isolation is required, conductive first or second silicon layer it can be of a type.

【0014】 [0014]

【実施例】以下、P−I−Nデバイスを製造するものとして説明するが、N−I−Pデバイスも本発明により製造でき、動作できることを理解すべきである。 EXAMPLES The following description, it is assumed that the production of P-I-N device, N-I-P devices also can be produced by the present invention, it should be understood that operation. デバイスの種類の選択は、デバイスが使用される特定の応用に依存する。 Selection of the type of device will depend on the particular application the device is used.

【0015】まず図1に示すように、N +ドープシリコン層10を設ける。 [0015] First, as shown in FIG. 1, provided N + doped silicon layer 10. このシリコン層は、基板、あるいは普通の技術を使用して基板内または基板上に成長されまたは打ち込みされる層とすることができる。 The silicon layer may be a substrate or common technique is grown in the substrate or on the substrate using or implantation is the layer. この例において、もしデバイスが、N型の基板上に作製されるならば、他のデバイスへの低抵抗の相互接続部を設け、もし基板がP型であるならば、他のデバイスからの分離部を設ける。 In this example, if the device, if it is fabricated on N-type substrate, provided interconnects low resistance to other devices, if the substrate is P-type, isolated from other devices providing a part. 図2に示されるように、第1の真性シリコン・ As shown in FIG. 2, the first intrinsic silicon
エピタキシャル層15を、N +シリコン層10上に一般的な方法で成長する。 The epitaxial layer 15 is grown in a conventional manner on the N + silicon layer 10.

【0016】次に、図3に示すように、元素の周期表のIV族に属する間接バンドギャップ材料である、約10 [0016] Next, as shown in FIG. 3, is an indirect bandgap material belonging to group IV of the periodic table of the elements, about 10
〜30nmのゲルマニウムまたはシリコン−ゲルマニウム合金を、第1の真性シリコン・エピタキシャル層15 Germanium or silicon to 30 nm - germanium alloy, a first intrinsic silicon epitaxial layer 15
上に堆積して、第1の真性シリコン・エピタキシャル層15上に、結晶またはアモルファスのゲルマニウム“ボール”の不連続層、すなわちまたは分離されるゲルマニウムのアイランド(islands)を形成する。 Deposited on, on the first intrinsic silicon epitaxial layer 15 to form a discontinuous layer of germanium "ball" of crystalline or amorphous, i.e. or germanium islands separated (islands). この点に関し、GeとSiとの間に格子不整合が存在し、G In this regard, lattice mismatch is present between the Ge and Si, G
eがSi上に堆積すると、材料間の格子不整合が、応力を生じさせて、Geが平滑な層として形成されず、ゲルマニウムの“ボール”またはアイランドとして形成されることを引き起こす。 When e is deposited on Si, the lattice mismatch between the materials is to bring about stress, Ge is not formed as a smooth layer, causing it to be formed as a "ball" or islands of germanium. これらの“ボール”またはアイランドを、この明細書では量子ドット20と称する。 These "balls" or islands, in this specification referred to as quantum dots 20. シリコン上に成長された、約数十nmサイズの、準安定結晶性Geクラスタ(clusters)の存在を確認するために低エネルギー回折の使用を論じている、アメリカ物理学会のAppl. Have been grown on silicon, of about a few tens of nm size, it discusses the use of low energy diffraction in order to confirm the presence of the metastable crystalline Ge cluster (clusters), Appl of the American Physical Society. Phys. Phys. Lett. Lett. 59(9) 59 (9)
1991年8月26日号,1061〜1063頁“Di August 26, 1991 issue, 1061-1063, pp. "Di
ffraction Determination o ffraction Determination o
f the Structure of Metast f the Structure of Metast
able Three−dimensional Cr able Three-dimensional Cr
ystals of Ge Grown on Si ystals of Ge Grown on Si
(001)”を、また、Si上にGeアイランドを成長するために分子線ビームエピタキシーの使用を論じている、Japanese Journal of App The (001) ", also discusses the use of molecular beam epitaxy in order to grow the Ge islands on Si, Japanese Journal of App
liedPhysics,Vol. liedPhysics, Vol. 28,No. 28, No. 4,1 4,1
989年4月号,L690〜L693頁“Initia 989 years April, L690~L693 pages "Initia
l Stage of Grown of Ge on l Stage of Grown of Ge on
(100) Si by Gas Sourse Mo (100) Si by Gas Sourse Mo
lecular Beam Epitaxy Usin lecular Beam Epitaxy Usin
g GeH 4 ”を、一般に参照されたい。 the g GeH 4 ", see generally.

【0017】一般的に、シリコン上のゲルマニウム量子ドット20の形成は、広いプロセス範囲にわたって達成可能であるが、しかし、約550℃以下の低い温度が、 [0017] Generally, formation of the germanium quantum dots 20 on silicon, but can be achieved over a wide process range, however, the lower temperatures than about 550 ° C.,
ドットサイズを制御し、SiとGeが相互拡散することを防止するために重要となる。 Controls dot size, Si and Ge is important to prevent mutual diffusion. この点に関し、Geの薄膜層は、高い成長速度の故に、より高い温度で成長することが困難となる。 In this regard, a thin film layer of Ge is due to the high growth rate, it is difficult to grow at higher temperatures. SiでなくGeのみを、一般の減圧化学気相成長(LPCVD)を使用して低温で成長できる。 Only Ge instead of Si, can be grown at low temperature by using ordinary pressure chemical vapor deposition (LPCVD). しかしながら、GeとSiの両方を、超高真空化学気相成長(UHVCVD),低温常圧気化学気相成長(APCVD),分子線ビームエピタキシー(MB However, both Ge and Si, ultra-high vacuum chemical vapor deposition (UHVCVD), low-temperature atmospheric-pressure gas chemical vapor deposition (APCVD), molecular beam epitaxy (MB
E),または他の低温エピタキシャル技術のいずれかを使用して成長できる。 E), or other can be grown using any of the low-temperature epitaxial technique. 更にまた、これらの技術を用いて、種々の層を堆積することができ、このときこれらの層を、層の品質および発光効率を劣化させる堆積間の有害な環境へ曝すことはない。 Furthermore, using these techniques, it is possible to deposit the various layers, these layers this time, not be exposed to harmful environment between deposition degrading the quality and luminous efficiency of the layer. それ故、UHVCVD,低温APCVD,またはMBEのいずれかを、Ge量子ドット20を形成するために使用できる。 Therefore, UHVCVD, either the low temperature APCVD or MBE,, can be used to form a Ge quantum dots 20. このとき、Si In this case, Si
も同じ技術を用いて成長させることができる。 It can also be grown using the same technique. 超高真空化学気相成長または低温APCVDは、製造能力の観点からMBE以上に好適とされる。 Ultra-high vacuum chemical vapor deposition or low temperature APCVD is a preferred in view of production capacity or MBE.

【0018】一例として、UHVCVDを使用してGe [0018] As an example, Ge using UHVCVD
量子ドット20を形成するおおよその処理パラメータは以下のとおりである。 Approximate process parameters for forming the quantum dots 20 is as follows. 温度:415〜550℃ He内の10%Ge:1〜100mTorr 時間:1〜60分 これらのパラメータは、“所定の(tailore Temperature: 415 to 550 10% in ℃ He Ge: 1~100mTorr Time: 1-60 minutes These parameters "predetermined (Tailore
d)”Ge粒子サイズの範囲を与える。例えば、約51 d) providing a range of "Ge particle size. For example, about 51
5℃で,約4分間に約15mTorrで堆積するGe At 5 ° C., Ge is deposited at about 15mTorr for about four minutes
は、約10nmの直径を有するGe粒子サイズまたはG Is, Ge particle size or G having a diameter of about 10nm
e量子ドットを作製する。 Making the e quantum dot.

【0019】一例として、各量子ドット20は、約10 [0019] As an example, the quantum dots 20 is about 10
〜20nmの高さまたは厚さおよび約10nmの程度の直径を有することができ、各量子ドット20は、隣合う量子ドット20から約10〜20nmの間隔をあけることができる。 It may have a degree of diameter height or thickness and about 10nm of to 20 nm, the quantum dots 20 can be from adjacent quantum dots 20 spaced about: 10 to 20 nm. しかしながら、量子ドット20の寸法および各量子ドット20間の間隔は、特定の応用および製造されるデバイスの条件に従って適合できる。 However, the size and spacing between the individual quantum dots 20 of the quantum dots 20 may be adapted according to the conditions of the device specified in the application and manufacturing. 例えば、発光の波長を、光信号伝送用の導波路および/または検出器に整合できる。 For example, the wavelength of emission can be matched to the waveguide and / or the detector of the optical signal transmission.

【0020】次に、図4に示すように、第2の真性シリコン・エピタキシャル層25を、第1の真性シリコン・ Next, as shown in FIG. 4, a second intrinsic silicon epitaxial layer 25, a first intrinsic silicon
エピタキシャル層15上に、および量子ドット20上に量子ドットを埋込むように堆積する。 On the epitaxial layer 15, and is deposited to fill the quantum dots on the quantum dots 20. より具体的には、 More specifically,
第2の真性シリコン・エピタキシャル層25を、量子ドット20間の第1の真性シリコン・エピタキシャル層1 A second intrinsic silicon epitaxial layer 25, a first intrinsic silicon epitaxial layer between the quantum dots 20 1
5上に堆積し、および量子ドット20上に堆積する。 5 is deposited on and is deposited on the quantum dots 20. その結果、量子ドット20が、第2の真性シリコン・エピタキシャル層25の材料内に埋込まれて、平滑な単一結晶層を形成する。 As a result, the quantum dots 20, is embedded in the material of the second intrinsic silicon epitaxial layer 25, to form a smooth single crystal layer. この点に関し、第2の真性シリコン・ In this regard, the silicon second intrinsic
エピタキシャル層25を、Ge量子ドット20上の横方向オーバ成長で、第1の真性シリコン・エピタキシャル層15上に広く行き渡るように成長させることを確実にするために、Ge量子ドット20の密度は適当に低くなるべきであり、すなわち、Ge量子ドット20が、相互に十分に間隔されるべきである。 The epitaxial layer 25, laterally over the growth on Ge quantum dots 20, in order to ensure that the growing as spread widely over the first intrinsic silicon epitaxial layer 15, the density of Ge quantum dots 20 is suitably in should be low, i.e., Ge quantum dots 20 should be sufficiently spaced from one another. これは、第2の真性シリコン・エピタキシャル層25内で結晶配列を維持する。 This maintains the crystal array in a second intrinsic silicon epitaxial layer within 25. 結晶配列は、、エピタキシャル成長の特性であり、 Crystal array is a characteristic of ,, epitaxial growth,
およびデバイスの電気的動作にとって重要である。 And it is important for the electrical operation of the device. 有利なことには、量子ドット20が不連続であり、第2の真性シリコン・エピタキシャル層25と比較して薄いので、第2の真性シリコン・エピタキシャル層25は、低い転位密度をもつ。 Advantageously, a quantum dot 20 is discontinuous, because thinner than the second intrinsic silicon epitaxial layer 25, a second intrinsic silicon epitaxial layer 25 has a low dislocation density.

【0021】第2の真性シリコン・エピタキシャル層2 [0021] The second intrinsic silicon epitaxial layer 2
5を、Ge量子ドット20が成長される同じ温度で成長でき、このような温度が、第2の真性シリコン・エピタキシャル層25を成長させるため使用される他のプロセス・パラメータを制御する。 5, can be grown at the same temperature for Ge quantum dots 20 is grown, such temperature controls the other process parameters used for growing the second intrinsic silicon epitaxial layer 25. 一例として515℃の温度を使用して、第2の真性シリコン・エピタキシャル層2 Using a temperature of 515 ° C. As an example, a second intrinsic silicon epitaxial layer 2
5を、UHVCVDを使用し、約30分間、約1〜3m 5, using UHVCVD, about 30 minutes, about 1~3m
Torrでシランを用い、約20nmの厚さに成長できる。 Using silane in Torr, it can be grown to a thickness of about 20 nm.

【0022】第2の真性シリコン・エピタキシャル層2 [0022] The second intrinsic silicon epitaxial layer 2
5を成長した後、第1の真性シリコン・エピタキシャル層15と第2の真性シリコン・エピタキシャル層25との間の界面は全く存在しない。 5 After growing the the interface between the first intrinsic silicon epitaxial layer 15 second intrinsic silicon epitaxial layer 25 does not exist at all. このように、量子ドット20は、単一の同質なイントリンシック層に完全に埋込まれる。 Thus, the quantum dots 20 is completely filled with a single homogeneous intrinsic layer. 従って、図4と図5における層15と25との間の線、および図6における線は、作製プロセスにおける工程、すなわち単結晶金属遷移を反映しており、真の界面ではない。 Thus, lines lines, and in FIG. 6 between the layers 15 and 25 in FIG. 4 and FIG. 5, step in the fabrication process, i.e. reflects the single crystal metal transition, not a true interface.

【0023】一例として、第2の真性シリコン・エピタキシャル層25は、全ての処理の終了の後に約50nm [0023] As an example, a second intrinsic silicon epitaxial layer 25 is about 50nm after the completion of all processing
の全厚を有することができる。 The total thickness of the can have. この点に関し、Ge量子ドット20の量を増加するためには、GeおよびSiの薄膜層を、第1の真性シリコン・エピタキシャル層15 In this regard, in order to increase the amount of Ge quantum dots 20, the thin film layer of Ge and Si, a first intrinsic silicon epitaxial layer 15
上に各々交互に成長できる。 Each can grow alternately on top. 交互成長を、Ge量子ドット20の所望の量が達成されるまで、繰り返すことができる。 The alternating growth, until the desired amount of Ge quantum dots 20 can be achieved, can be repeated. このようなデバイスは、図6に示される。 Such devices are shown in FIG. 図6 Figure 6
は、Ge層およびSi層の3つの交互する繰返しを示しているが、本発明によるデバイスは3つのこのような繰返しに限定されず、必要とされる多数の交互GeおよびSi層を、作製できることを理解するべきである。 , While indicating repetition of three alternating Ge layers and Si layers, the device according to the present invention is not limited to three such repeating, a number of alternating Ge and Si layers required, can be prepared a it is to be understood. 交互に成長するGeおよびSiにより生じる界面での汚染を、その場(in suit)成長を行うことにより防止できる。 Contamination at the interface caused by Ge and Si is grown alternately, it can be prevented by performing the in situ (in suit) growth. その場成長では、各層の成長に従って大気または他の有害な環境に曝すことなく単一の反応器で連続的に層を成長する。 In situ growth, it grows continuously layers in a single reactor without exposure to the atmosphere or other deleterious environment in accordance with each of the growth.

【0024】次に、約50〜150nmの厚さを有するP +シリコン層30を、第2の真性シリコン・エピタキシャル層25上に堆積する。 Next, a P + silicon layer 30 having a thickness of about 50 to 150 nm, is deposited on the second intrinsic silicon epitaxial layer 25.

【0025】次に、Ge量子ドット20をもつこれらの層を、一般のリソグラフィ技術および反応性イオンエッチングを使用して活性領域内にパターニングして画成し、図5に示されるような、個々の発光/検出デバイスを形成することができる。 Next, these layers having a Ge quantum dots 20, and patterned define the active region by using an ordinary lithography technique and reactive ion etching, as shown in FIG. 5, each it is possible to form the light emitting / detecting device. 次に、発光/検出デバイスを、他の発光/検出デバイスとの中間チップまたは内部チップ光通信に使用できる。 Next, the light emitting / detecting devices, can be used in the intermediate chip or the chip optical communication with other emission / detection device.

【0026】図5に示すように、次に、薄い半透明金属コンタクト層60を発光/検出デバイス上に堆積でき、 As shown in FIG. 5, it can then deposited on the light emitting / detecting devices a thin semi-transparent metal contact layer 60,
他のシリコン回路構成要素へ接続するための薄い金属コンタクトパッド/相互接続部65を次いで堆積する。 Deposited is then a thin metal contact pads / interconnects 65 for connecting to other silicon circuitry. これらの金属層60,65は、一般の技術を使用して堆積でき、次に、標準のリフトオフまたは反応性イオンエッチング処理を使用してパターニングする。 These metal layers 60 and 65 can deposited using general techniques, then, it is patterned using standard lift-off or reactive ion etching process. 例えば、コンタクト層60は、光ファイバへの光コンタクト用の窓として機能する。 For example, the contact layer 60 functions as a window for optical contact to the optical fiber.

【0027】一例として、図7は、シリコン回路、例えば論理回路またはメモリ回路が内部に作製されたシリコンチップ50上に形成された本発明による発光/検出デバイス構造35,40および45を示す。 [0027] As an example, FIG. 7 shows a silicon circuit, for example, a logic circuit or a light emitting according to the invention, the memory circuit is formed on a silicon chip 50 fabricated therein / detection device structures 35,40 and 45. 製造プロセスでは低温が用いられるので、CMOSデバイス特性は損なわれない。 Since the low temperature is used in the manufacturing process, CMOS device characteristics are not impaired. 各発光/検出デバイス35,40および4 Each light emitting / detecting devices 35, 40 and 4
5は、図1〜図5に基づいて説明したように製造され、 5 is manufactured as described with reference to FIGS. 1 to 5,
バイポーラまたはCMOSとすることのできるシリコン回路の完成後に製造できる。 It can be prepared after completion of the silicon circuit, which may be bipolar or CMOS. しかしながら、発光/検出デバイスを、個々の個別オプトエレクトロニクス構成要素、すなわち、他の回路と集積されない構成要素として、本発明によりまた製造できることを理解すべきである。 However, the light emitting / detecting devices, each individual optoelectronic components, i.e., as a component that is not integrated with other circuits, it should be understood that also can be produced by the present invention.

【0028】各発光/検出デバイス35,40および4 [0028] Each light emitting / detecting devices 35, 40 and 4
5を、金属線,拡散等のような一般の相互接続手段により、シリコン回路の適切な対応する構成要素に電気的に結合する。 5, the metal wire, the ordinary interconnection means such as diffusion or the like, electrically coupled to a suitable corresponding components of the silicon circuit. 光信号を、1つの発光/検出デバイスから普通のシリコンベースの光検出器へ、またはフォトダイオードとして機能する本発明による他の発光/検出デバイスへ、等方的に伝送できる。 An optical signal, to one common silicon-based from the light emitting / detecting devices of the photodetector, or to other light emitting / detecting device according to the present invention that functions as a photodiode, can be isotropically transmitted. すなわち、光導波路55を形成して、所望どおりに光信号を指向するために、複数の発光/検出デバイスをオプトエレクトロニクス的に接続することができる。 That is, by forming an optical waveguide 55, to direct optical signals as desired can be connected to the plurality of light emitting / detecting devices optoelectronic manner. このような光導波路55は、例えば、酸化物,二酸化シリコン,窒化シリコン,またはいずれの透明材料を使用して、一般的に製造できる。 Such an optical waveguide 55, for example, oxides, using silicon dioxide, silicon nitride, or any transparent material, can generally produced. もちろん、光導波路55を、光信号を正確に反射し,指向するための適切な角度をもつようにパターニングしなければならない。 Of course, an optical waveguide 55, an optical signal accurately reflected, must be patterned to have an appropriate angle to direct.

【0029】各発光/検出デバイス35,40および4 [0029] Each light emitting / detecting devices 35, 40 and 4
5は、光信号を電気インパルスに変換し、および電気インパルスを光信号に変換することにより変換器として機能でき、光を光学的に伝送し,受光することができる。 5 converts the optical signals into electrical impulses, and electrical impulses can function as a transducer by converting the optical signal, light is optically transmitted, it can be received.
一例として、発光/検出デバイス35へ結合されたシリコン回路が発光/検出デバイス40または45へ結合されたシリコン回路と通信することを必要とする場合について、動作を説明する。 As an example, the case where the silicon circuitry coupled to the light emitting / detecting device 35 needs to communicate with the silicon circuit coupled to the light emitting / detecting device 40 or 45, the operation will be described.

【0030】発光/検出デバイス35に結合されたシリコン回路が、発光/検出デバイス35を介して電流を送って、発光/検出デバイス35を順方向にバイアスし、 The silicon circuit coupled to the light emitting / detecting device 35 sends a current through a light emitting / detecting device 35, biases the light emitting / detecting device 35 in the forward direction,
電荷キャリア(すなわち正孔および電子)を、それ故、 Charge carriers (i.e. holes and electrons), thus,
発光/検出デバイスの第1,第2真性シリコン・エピタキシャル層(図1の参照番号15と25)内に注入する。 First light emitting / detecting device, it is injected into the second intrinsic silicon epitaxial layer (reference numeral 15 in FIG. 1 and 25). GeはSiと比較して小さいバンドギャップを有するので、Siに埋め込まれたGeは、一連の0次元量子井戸(ドット)を形成する。 Since Ge has a smaller band gap compared to Si, Ge embedded in Si forms a series of zero-dimensional quantum well (dots). 各量子井戸は、高い補集率を有する。 Each quantum well has a high collecting rate. 高い補集率の故に、電荷キャリアは、量子井戸に、より具体的には、発光/検出デバイス35内の量子ドットに、捕獲され,閉じ込こめられる。 Because of the high collecting rate, charge carriers in the quantum well, and more particularly, to a quantum dot light emitting / detecting devices 35 are captured, is put confinement. このとき、 At this time,
電荷キャリアは、量子ドットで放射的に(radiat Charge carriers radiatively quantum dots (Radiat
ively)再結合する。 ively) recombine. このように、量子ドットは電気的に“ポンプ作用し(pumped)”、シリコン回路から流れる電流を、発光または光信号に変換する。 Thus, quantum dots electrically "by pumping action (pumped)", the current flowing from the silicon circuit, and converts the light-emitting or light signals. これらの光信号を、発光/検出デバイス35により、中間レベルの誘電体または空気を経て等方的に、発光/検出デバイス45へ、または導波路55を経て発光/検出デバイス35から発光/検出デバイス40へ伝達する。 These optical signals, by the light emitting / detecting device 35, isotropically through the interlevel dielectric or air emission / to the detection device 45 or through the waveguide 55 to emit light from the light emitting / detecting device 35 / detection device, transmitted to the 40. どちらの場合においても、発光/検出デバイス40または45が光信号を受けた後、発光/検出デバイス40または45は、光信号を電気信号に再変換する。 In either case, after the light emitting / detecting device 40 or 45 receives an optical signal, the light emitting / detecting device 40 or 45 reconverts the optical signal into an electric signal. 電気信号は、発光/検出デバイス40または45に結合されたシリコン回路へ送られる。 Electrical signal is transmitted to the silicon circuit coupled to the light emitting / detecting device 40 or 45.

【0031】本発明の発光/検出デバイスは、デバイスの空乏化されたイントリンシック領域で電子−正孔対に変換される吸収光によって普通のシリコンフォトダイオードとして機能できる。 The light emitting / detecting device of the present invention is the intrinsic region that has been depleted of the device electronic - can function as an ordinary silicon photodiode by absorbing light that is converted into hole pairs. そのように形成された電子および正孔は、分離されて、ダイオードのnおよびp拡散領域に送られる。 The so-formed electrons and holes, are separated and sent to the n and p diffusion region of the diode. このようにして、電気信号を発生する。 In this way, it generates electrical signals.
この点において、本発明により必ずしも製造されない、 In this regard, not necessarily produced by the present invention,
いずれの適切な検出器も、光信号を検出するために使用できる。 Any suitable detector may be used to detect optical signals.

【0032】特定の実施例として、Ge量子ドットは、 [0032] As a specific example, Ge quantum dots,
P−I−Nダイオードの空乏領域内の狭バンドギャップの領域として機能する。 It serves as a narrow band gap region within the depletion region of the P-I-N diode. 図8において、シリコンのバンドギャップ内にあるGe量子ドットのエネルギーバンド間のキャリアの移動は、起こらないことを示している。 8, movement of the carrier between the energy band of Ge quantum dots within the band gap of silicon shows that it does not.
図8の点線は、フェルミ準位を示している。 The dotted line in FIG. 8 shows the Fermi level.

【0033】図9に示すように、正の電圧が、ダイオードのp拡散側(n側に対して)に供給されると、空乏領域が消失し、キャリアがドープ領域間を流れる。 As shown in FIG. 9, a positive voltage and supplied to the p diffusion side of the diode (for n-side), the depletion region is lost, carriers flow between the doped regions. 供給される電界は、正孔がn拡散側へ移動し、電子がp拡散側へ移動する導電型によりキャリアの分離を生じる。 Electric field is supplied, holes are moved to the n diffusion side, resulting in separation of the carrier by conductive type electron moves to the p diffusion side. この電荷の分離は、Ge量子ドットをキャリアで充填させる。 This separation of charge, to fill the Ge quantum dots carrier. これらのキャリアは、それらの波長と比較して小さい幾何学的体積内に閉じ込められ、再結合時に、Ge量子ドットのサイズの関数である所定の波長で発光する。 These carriers are confined in these wavelengths as compared to small geometric within the volume recombination during emits light at a predetermined wavelength is a function of the size of the Ge quantum dots.
逆方向バイアスモード時には、このデバイスは、周知のP−I−Nダイオード検出器のように振る舞う。 The reverse bias mode, the device behaves like a known P-I-N diode detector. 換言すれば、光吸収は、電界により分離される電子−正孔対を作り出し、光電流を発生する。 In other words, the light absorption electrons are separated by an electric field - creating a hole pairs to generate a photocurrent. この光電流は、増幅されて検出される。 This photocurrent is detected and amplified.

【0034】本発明を特定の実施例により説明したが、 [0034] The present invention has been described by way of specific examples,
当業者には多くの変更,変形が可能なことは明らかである。 Those skilled in the art many modifications will be apparent that deformable possible. 従って、本発明の範囲および趣旨内の全てのこのような変更,変形を包含するものである。 Accordingly, all such modifications within the scope and spirit of the present invention is intended to cover modifications.

【0035】 [0035]

【発明の効果】本発明により、シリコンベースの半導体回路/サブシステムの性能が改良される。 According to the present invention, the performance of silicon-based semiconductor circuit / sub-system is improved.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の一実施例による半導体発光/検出デバイスの製造中の処理の種々の段階での基板の一部を示した断面図である。 1 is a cross-sectional view showing a part of a substrate at various stages of processing during fabrication of semiconductor light emitting / detecting device according to an embodiment of the present invention.

【図2】本発明の一実施例による半導体発光/検出デバイスの製造中の処理の種々の段階での基板の一部を示した断面図である。 2 is a cross-sectional view showing a part of a substrate at various stages of processing during fabrication of semiconductor light emitting / detecting device according to an embodiment of the present invention.

【図3】本発明の一実施例による半導体発光/検出デバイスの製造中の処理の種々の段階での基板の一部を示した断面図である。 3 is a sectional view showing a part of a substrate at various stages of processing during fabrication of semiconductor light emitting / detecting device according to an embodiment of the present invention.

【図4】本発明の一実施例による半導体発光/検出デバイスの製造中の処理の種々の段階での基板の一部を示した断面図である。 4 is a sectional view showing a part of a substrate at various stages of processing during fabrication of semiconductor light emitting / detecting device according to an embodiment of the present invention.

【図5】本発明の一実施例による半導体発光/検出デバイスの製造中の処理の種々の段階での基板の一部を示した断面図である。 5 is a cross-sectional view showing a part of a substrate at various stages of processing during fabrication of semiconductor light emitting / detecting device according to an embodiment of the present invention.

【図6】本発明によるSiに埋め込まれた量子ドットの複数の層を示す図である。 6 is a diagram showing a plurality of layers of quantum dots embedded in Si according to the present invention.

【図7】本発明によるシリコンチップに形成された半導体発光/検出デバイスを示す図である。 7 is a diagram showing a semiconductor light emitting / detecting device formed on a silicon chip according to the present invention.

【図8】本発明のデバイスのバンド構造を示す図である。 8 is a diagram showing the band structure of the device of the present invention.

【図9】本発明のデバイスのバンド構造を示す図である。 9 is a diagram showing the band structure of the device of the present invention.

【符号の説明】 DESCRIPTION OF SYMBOLS

10 N +シリコン層 15 第1のエピタキシャル層 20 量子ドット 25 第2のエピタキシャル層 30 P +エピタキシャル層 35,40,45 発光/検出デバイス 50 シリコンチップ 55 光導波路 60,65 金属コンタクト層 10 N + silicon layer 15 first epitaxial layer 20 quantum dots 25 second epitaxial layer 30 P + epitaxial layer 35, 40, 45 light emitting / detecting device 50 silicon chip 55 waveguide 60, 65 metal contact layer

───────────────────────────────────────────────────── フロントページの続き (72)発明者 セシャドリ・サバンナ アメリカ合衆国 ニューヨーク州 ホープ ウェル ジャンクション ルート 376 ホープウェル ガーデンエイピーアールテ ィーエス #エフ−15 (72)発明者 マニュ・ジャムナダス・テジュワニ アメリカ合衆国 ニューヨーク州 ヨーク タウン ハイツ エサン コート 1327 ────────────────────────────────────────────────── ─── of the front page continued (72) inventor Seshadori Savannah United States, New York Hopewell junction route 376 Hopewell Garden rays copy Earl Te Iesu # F -15 (72) inventor Manufacturing, Jamunadasu-Tejuwani United States New York Yorktown Heights, Ehsan Court 1327

Claims (17)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】半導体発光/検出デバイスの製造方法において、 (a)第1の導電型の第1のドープシリコン層を設ける工程と (b)前記第1のドープシリコン層上に第1の真性シリコン・エピタキシャル層を形成する工程と、 (c)前記第1の真性シリコン・エピタキシャル層に少なくとも1つの量子ドットを形成する工程と、 (d)第2の真性シリコン・エピタキシャル層を、第1 1. A method for manufacturing a semiconductor light emitting / detecting device, (a) a first intrinsic to the first conductivity type providing a first doped silicon layer of step and (b) said first doped silicon layer forming a silicon epitaxial layer, at least one of the steps of forming a quantum dot, (d) is a second intrinsic silicon epitaxial layer on the first intrinsic silicon epitaxial layer (c), first
    の真性シリコン・エピタキシャル層におよび前記少なくとも1つの量子ドット上に形成して、前記少なくとも1 Intrinsic silicon epitaxial layer and said formed on at least one quantum dot, wherein at least 1
    つの量子ドットを埋込む工程と、 (e)前記第2の真性シリコン・エピタキシャル層上に第2の導電型の第2のドープシリコン層を形成する工程と、 (f)前記層および前記少なくとも1つの量子ドットをもつ発光/検出デバイスを画成する工程と、 を含むことを特徴とする半導体発光/検出デバイスの製造方法。 One of the steps of embedding quantum dots, (e) forming a second doped silicon layer of the second conductivity type in the second intrinsic silicon epitaxial layer, (f) said layer and said at least one One method of manufacturing the semiconductor light emitting / detecting device comprising the steps of defining a light emission / detection device with quantum dots, characterized in that it comprises a.
  2. 【請求項2】請求項1記載の半導体発光/検出デバイスの製造方法において、 前記工程(c)が、元素の周期表のIV族の間接バンドギャップ材料を使用して、前記少なくとも1つの量子ドットを形成することを特徴とする半導体発光/検出デバイスの製造方法。 2. A method for manufacturing a semiconductor light emitting / detecting device of claim 1, wherein said step (c), using an indirect bandgap material of group IV of the periodic table of the elements, the at least one quantum dot the method of manufacturing a semiconductor light emitting / detecting device and forming a.
  3. 【請求項3】請求項2記載の半導体発光/検出デバイスの製造方法において、 前記間接バンドギャップ材料が、ゲルマニウムより成ることを特徴とする半導体発光/検出デバイスの製造方法。 3. A method for manufacturing a semiconductor light emitting / detecting device according to claim 2, wherein the indirect bandgap material, manufacturing method of the semiconductor light emitting / detecting device, characterized in that consists of germanium.
  4. 【請求項4】請求項2記載の半導体発光/検出デバイスの製造方法において、 前記間接バンドギャップ材料が、シリコン−ゲルマニウム合金より成ることを特徴とする半導体発光/検出デバイスの製造方法。 4. A method for manufacturing a semiconductor light emitting / detecting device according to claim 2, wherein the indirect bandgap materials, silicon - a method of manufacturing a semiconductor light emitting / detecting device, characterized in that consists of germanium alloy.
  5. 【請求項5】請求項1記載の半導体発光/検出デバイスの製造方法において、 前記工程(f)が、リソグラフィックにパターニングし、反応性イオンエッチングすることを特徴とする半導体発光/検出デバイスの製造方法。 5. A method for manufacturing a semiconductor light emitting / detecting device according to claim 1, producing said step (f) is patterned lithographically, the semiconductor light emitting / detecting device, characterized in that reactive ion etching Method.
  6. 【請求項6】請求項1記載の半導体発光/検出デバイスの製造方法において、 工程(f)が、リソグラフィックにパターニングし、ウエット化学エッチングすることを特徴とする半導体発光/検出デバイスの製造方法。 6. A method for manufacturing a semiconductor light emitting / detecting device of claim 1 wherein the step (f) is patterned lithographically, a method of manufacturing a semiconductor light emitting / detecting device, characterized in that wet chemical etching.
  7. 【請求項7】請求項1記載の半導体発光/検出デバイスの製造方法において、 前記工程(c)および前記工程(d)が、ゲルマニウムおよびシリコンを交互に成長し、 ゲルマニウムが量子ドットを形成し、シリコンが第2の真性シリコン・エピタキシャル層を形成し、 量子ドットの量が、前記交互成長により増加する、 ことを特徴とする半導体発光/検出デバイスの製造方法。 7. A method for manufacturing a semiconductor light emitting / detecting device of claim 1 wherein step (c) and the step (d) to grow germanium and silicon alternately, germanium forms a quantum dot, silicon forms a second intrinsic silicon epitaxial layer, the amount of quantum dots is increased by the alternating deposition, a method of manufacturing a semiconductor light emitting / detecting device, characterized in that.
  8. 【請求項8】請求項1記載の半導体発光/検出デバイスの製造方法において、 前記工程(c)および前記工程(d)の各々が、低温エピタキシャル技術を使用することを特徴とする半導体発光/検出デバイスの製造方法。 8. The manufacturing method of the semiconductor light emitting / detecting device according to claim 1, wherein each of said steps (c) and the step (d), the semiconductor light emitting / detecting characterized by using a low temperature epitaxial technique a device manufacturing method.
  9. 【請求項9】請求項8記載の半導体発光/検出デバイスの製造方法において、 前記少なくとも1つの量子ドットおよび第2の真性シリコン・エピタキシャル層は、低温エピタキシャル技術を使用してほぼ同じ温度で成長させることを特徴とする半導体発光/検出デバイスの製造方法。 9. The manufacturing method of the semiconductor light emitting / detecting device according to claim 8, wherein the at least one quantum dot and the second intrinsic silicon epitaxial layer is grown at about the same temperature using a low temperature epitaxial technique the method of manufacturing a semiconductor light emitting / detecting device, characterized in that.
  10. 【請求項10】請求項1記載の半導体発光/検出デバイスの製造方法において、 前記工程(c)が、約415〜550℃の温度で、約1 10. A method for manufacturing a semiconductor light emitting / detecting device of claim 1, wherein said step (c), at a temperature of about from 415 to 550 ° C., about 1
    〜100mTorrでHe中に約10%のGeを用いて、約1〜60分間、超高真空化学気相成長を使用することを特徴とする半導体発光/検出デバイスの製造方法。 Using about 10% Ge in He at ~100MTorr, about 1 to 60 minutes, the method of manufacturing a semiconductor light emitting / detecting device characterized by the use of ultra-high vacuum chemical vapor deposition.
  11. 【請求項11】請求項1記載の半導体発光/検出デバイスの製造方法において、 前記第2の真性シリコン・エピタキシャル層を、前記少なくとも1つの量子ドット上の横方向のオーバ成長で、 11. A method for manufacturing a semiconductor light emitting / detecting device according to claim 1, said second intrinsic silicon epitaxial layer, in the transverse direction of the over-growth on the at least one quantum dot,
    前記第1の真性シリコン・エピタキシャル層上に、広く行き渡るように成長させることを特徴とする半導体発光/検出デバイスの製造方法。 The method of manufacturing a semiconductor light emitting / detecting device, characterized in that the first intrinsic silicon epitaxial layer is grown so spread widely.
  12. 【請求項12】請求項1記載の半導体発光/検出デバイスの製造方法において、 前記工程(c)および前記工程(d)を、その場実行することを特徴とする半導体発光/検出デバイスの製造方法。 12. A method for manufacturing a semiconductor light emitting / detecting device of claim 1 wherein step (c) is and wherein step (d), a method of manufacturing a semiconductor light emitting / detecting device, characterized by in situ run .
  13. 【請求項13】第1の導電型の第1のドープシリコン層と、 前記第1のドープシリコン層に形成された真性シリコン・エピタキシャル層と、 前記真性シリコン・エピタキシャル層内に埋込まれた少なくとも1つの量子ドットと、 前記真性シリコン・エピタキシャル層上に形成された第2の導電型の第2のドープシリコン層と、 を備えることを特徴とする半導体発光/検出デバイス。 13. A first doped silicon layer of the first conductivity type, wherein the first intrinsic silicon epitaxial layer formed on the doped silicon layer, at least the embedded into intrinsic silicon epitaxial layer the semiconductor light emitting / detecting device, characterized in that it comprises a single quantum dot, the second doped silicon layer of the second conductivity type formed in the intrinsic silicon epitaxial layer, the.
  14. 【請求項14】請求項13記載の半導体発光/検出デバイスにおいて、 前記少なくとも1つの量子ドットが、元素の周期表のI 14. The semiconductor light emitting / detecting device of claim 13, wherein the at least one quantum dot, of the Periodic Table of the Elements I
    V族の半導体材料より成ることを特徴とする半導体発光/検出デバイス。 The semiconductor light emitting / detecting device, characterized by comprising a semiconductor material of group V.
  15. 【請求項15】請求項14記載の半導体発光/検出デバイスにおいて、 前記半導体材料が、ゲルマニウムより成ることを特徴とする半導体発光/検出デバイス。 15. The semiconductor light emitting / detecting device according to claim 14, wherein the semiconductor material is a semiconductor light emitting / detecting device, characterized in that consists of germanium.
  16. 【請求項16】請求項14記載の半導体発光/検出デバイスにおいて、 前記半導体材料が、シリコン−ゲルマニウム合金をより成ることを特徴とする半導体発光/検出デバイス。 16. The semiconductor light emitting / detecting device according to claim 14, wherein the semiconductor material is silicon - the semiconductor light emitting / detecting device characterized by comprising more germanium alloy.
  17. 【請求項17】請求項13記載の半導体発光/検出デバイスにおいて、 各層が、少なくとも1つの量子ドットを備える多層が、 17. The semiconductor light emitting / detecting device according to claim 13, each layer, a multilayer comprising at least one quantum dot,
    前記真性シリコン・エピタキシャル層に埋込まれていることを特徴とする半導体発光/検出デバイス。 The semiconductor light emitting / detecting device, characterized in that is embedded in the intrinsic silicon epitaxial layer.
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