JPH06326231A - Semiconductor device, manufacture thereof, and lead frame employed therein - Google Patents

Abstract

PURPOSE:To prevent the moisture resistance from deteriorating due to voids in a semiconductor device having an LOC structure. CONSTITUTION:In the method for manufacturing a semiconductor device 1 by bonding a semiconductor chip 4 to the rear surface at the inner end part 5 of lead through an insulation tape 6 and then sealing the semiconductor chip 4 with a resin package 2, the resin flows better through the upper space than through the lower space of the chip 4 when the package 2 is formed by transfer molding in conventional structure, and the resin flowed through the lower space advances to the end part of the upper space thus generating a plenty of voids. Furthermore, the advanced resin blocks the air vent at the resin part containing a plenty of voids. In order to solve the problem, the flow rate of resin is substantially equalized between the upper and lower spaces and a fluid resistor 9 is applied to the rear surface of the chip 4 in the vicinity of a gate 25 so that the air vent is not blocked at the resin part at the tip of the upper and lower spaces.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, in particular, a LOC (lead on chip) in which an inner lead portion of a metal lead is connected to one surface of a semiconductor chip and an electrode of the semiconductor chip and an inner lead are electrically connected. The present invention relates to a semiconductor device having a structure, a manufacturing method thereof, and a lead frame used in the manufacturing method.

[0002]

2. Description of the Related Art As one of resin package type semiconductor devices, an inner lead of a metal lead frame is adhered to one surface of a semiconductor chip via an insulating tape (polyimide tape having adhesive applied on both sides).・ L that connects the lead and the electrode of the semiconductor chip with a conductive wire
The OC structure is known. For the semiconductor device of LOC structure, "Nikkei Microdevice" 19 issued by Nikkei BP
Issued on February 1, 1991, issued on February 1, the same year, and described in P89 to P97. This document uses 16 LOC structure.
SO for MDRAM (Dynamic Random Access Memory)
J (Small Outline J-Leaded) is described. This document describes a conventional structure in which a chip is mounted on a die pad, a COL (Chip on Lead) structure in which a chip is mounted on a lead via an insulating tape, and a LOC for fixing the lead on the chip via an insulating tape. The structure is illustrated. In addition, in this document, "Since there are leads over the entire surface of the chip, it is easy to impede the flow of the mold. Therefore, the upper and lower surfaces of the chip are filled at the same time at the time of molding, the upper and lower balances that do not generate voids, and the molding conditions are determined by simulation. "There is".

On the other hand, "Electronic Materials" issued by the Industrial Research Group 198
Issued in August 1972, issued on August 1, 1987, P73-P79
Describes a plastic package. In this reference, in transfer molding, "a tablet preheated by a preheater is put into a pot.
It is injected in the order of (cal → runner → gate → cavity → air vent) by the plunger at the transfer tip. Flow resistance is eliminated by the runner size and shape, air entrapment is suppressed to a minimum, and the gate has an injection angle,
By controlling size, defects such as voids and gold wire flow are reduced, and the installation of air vents is an important factor for improving the filling property (molding appearance). The overrunner of Figure 1,
The dummy cavity is a means to reduce voids in the molded product and defective flow of the gold wire, and it seems that the dummy cavity is used in some way in the currently manufactured mold. Is stated. "

[0004]

The semiconductor device of the LOC structure has a structure in which a lead on the semiconductor chip, strictly speaking, a resin on the upper surface side of the lead (hereinafter, referred to as "on-chip resin") is compared with the thickness of the lead. The thickness of the lower resin (hereinafter referred to as "chip lower resin") is increased. Further, as pointed out in the above-mentioned document, since the LOC structure has leads on the entire surface of the chip, the flow of the resin on the upper surface side of the chip is obstructed during transfer molding in the manufacturing thereof. In the cavity formed by the upper and lower molds, the lower space for forming the lower chip resin is thicker than the upper space for forming the upper resin, and the lower surface of the chip is flat. Since the flow resistance is low, the resin injected from the gate into the cavity flows faster than the resin flowing in the upper space, and a phenomenon of wrapping around the upper space occurs. In the upper space, the flow is disturbed by the resin flowing directly from the gate and flowing in from the lower space. As a result, bubbles (voids) remain in the cavity. Further, when the resin flowing in the lower space goes around to the upper space, the phenomenon of pushing up the chip may occur, and the sealing may be completed while the posture of the chip or the lead is collapsed. The imbalance of the posture of the chip or the lead causes the thickness of the resin covering the chip or the lead to be locally thin, which causes a decrease in moisture resistance.

An object of the present invention is to provide a manufacturing method and a lead frame in which voids do not remain in a package in transfer molding in manufacturing a semiconductor device in which a resin on a chip and a resin under a chip have a large difference in thickness. It is in.

Another object of the present invention is to provide LO excellent in moisture resistance.
It is to provide a semiconductor device having a C structure or a COL structure. The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

[0007]

The outline of the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, the LOC structure semiconductor device of the present invention includes a package made of a resin, a plurality of metal leads extending inside and outside the package,
A semiconductor chip that is adhered to the lower surfaces of the inner ends of the leads in the package through an insulating tape whose both surfaces are coated with an adhesive, and the electrodes of the semiconductor chip and the inner ends of the leads are electrically connected in the package. A semiconductor device composed of a wire, and a resin under the chip is thicker than a resin on the chip, and an insulating tape is partially formed on a lower surface of the semiconductor chip of the package on which the resin is injected. A flow resistor consisting of is attached.

In the method of manufacturing a semiconductor device having a LOC structure according to the present invention, a step of adhering a semiconductor chip through an insulating tape having an adhesive applied on both sides to the lower surface of the lead inner end of the lead frame, and the lead frame. And a step of forming a package by injecting a resin into the cavity from the gate after sandwiching between the transfer mold upper and lower molds, since the lower space is thicker than the upper space of the semiconductor chip in the cavity, There is a step of adhering a flow resistance body serving as a flow resistance to the lower surface of the semiconductor chip near the gate side. The flow resistance body has a thickness as a flow resistance body such that the speed of the resin flowing through the upper space and the lower space becomes uniform. In addition, the upper and lower molds form a flow cavity connected to the air vent. The resin flowing into the cavity and overflowing from the cavity flows into the flow cavity through the air vent.

A semiconductor device having a LOC structure according to another embodiment of the present invention includes a package made of resin, a plurality of metal leads extending inside and outside the package,
The semiconductor chip is connected to one surface of the inner ends of the plurality of leads in the package via an insulating adhesive, and the leads on the semiconductor chip are thinned from the middle to the tip.

In a method of manufacturing a semiconductor device having a LOC structure according to another embodiment of the present invention, there is prepared a lead frame according to the present invention in which inner ends of leads attached to a semiconductor chip are thinly formed from the middle to the tip. And then
After a semiconductor chip is bonded to one surface of the inner end of the lead of the lead frame via an insulating adhesive, the lead frame is sandwiched between the upper and lower molds of a transfer molding device, and resin is injected into the cavity from the gate. To form a package. In addition, the upper and lower molds form a flow cavity connected to the air vent. The resin flowing into the cavity and overflowing from the cavity flows into the flow cavity through the air vent.

[0011]

In the manufacture of the LOC structure semiconductor device in which the flow resistor according to the present invention is attached to the semiconductor chip, the upper space above the semiconductor chip during transfer molding and the lower space of the semiconductor chip thicker than this upper space are used. A flow resistor is attached to the lower surface of the semiconductor chip on the resin inflow side so that the resin is uniformly injected. For this reason, the resin flowing from the gate into the cavity has a resistance in the lower space due to the resistance of the flow resistor, so that the flow velocity decreases and the resin velocity flowing through the lower space and the upper space becomes the same. Therefore,
The resin does not violently flow into the other space from one space, and the resin that has flowed through the upper space and the lower space merges at the air vent part at the same time, and together, inside the flow cavity. Since it flows into the flow cavity, the generated void also flows into the flow cavity, and the void does not remain in the cavity portion. As a result, the semiconductor device of the present invention manufactured by the manufacturing method of the present invention has no voids in the package and is excellent in moisture resistance.

Further, in the manufacture of the semiconductor device having the LOC structure of the present invention, during transfer molding, the resin flowing above and below the semiconductor chip due to the effect of the flow resistor is located on the air vent side opposite to the gate. Since the semiconductor chips are not joined together, the resin thickness above and below the semiconductor chip does not exceed the design value as in the conventional case, and high moisture resistance can be maintained.

In the manufacture of a LOC structure semiconductor device in which the inner ends of the leads are thinned according to another embodiment of the present invention, the inner ends of the leads to which the semiconductor chips are attached are thinned from the middle to the tip. A lead frame is used, and a semiconductor chip is adhered to the inner ends of the leads of the lead frame, and then a package is formed by transfer molding. During the transfer molding, the resin flowing into the cavity from the gate is a semiconductor chip. The upper inner space and the lower space are separated, but in the upper space, which is thinner than the lower space, the inner ends of the leads that project and extend in the center of the upper space become thin, and the resin flow path must be substantially deep. Therefore, it will be faster than the conventional one. Therefore, the resin does not violently flow into the other space from one space, and the resin flowing in the upper space and the lower space merge at the same time at the air vent part and flow together. Since it flows into the cavity, the generated void also flows into the flow cavity, and the void does not remain in the cavity portion.
As a result, the semiconductor device of the present invention manufactured by the manufacturing method of the present invention has no voids in the package and is excellent in moisture resistance. Moreover, the lead frame according to the present invention contributes to the manufacture of a semiconductor device having a LOC structure having excellent moisture resistance.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view of the same semiconductor device, FIG. 3 is a cross-sectional view showing the same part of a semiconductor device, and FIG. FIG. 5 is a plan view showing a lead frame used for manufacturing the semiconductor device of the invention, FIG. 5 is a plan view showing a lead frame to which a semiconductor chip is similarly fixed, and FIG. 6 is a lead having a flow resistor attached to the back surface of the semiconductor chip. FIG. 8 is a bottom view showing the frame, FIG. 7 is a schematic plan view showing the same molded state, and FIG. 8 is a sectional view showing the same molded state.

The semiconductor device 1 of the present invention is shown in FIG.
As shown in FIG. 3, the package 2 is made of resin, and the leads 3 are made of metal and project from both sides of the package 2. The lead 3 is a J-lead whose tip wraps around the lower side of the package 2. A chip (semiconductor chip) 4 having an LSI (Large Scale Integrated Circuit Device) formed therein is provided in the package 2. This semiconductor chip 4 is a package 2
It is bonded to the lower surface of the inner end portion (inner lead) 5 of the inner lead via an insulating adhesive 6 to form a LOC structure. The insulating adhesive body 6 is, for example, an insulating tape 6 made of a polyimide tape having a thickness of 80 μm and having an adhesive applied on both sides. Also, inner lead 5
Of the semiconductor chip 4 and an electrode (not shown) of the semiconductor chip 4 are electrically connected by a wire 7 made of a gold wire having a diameter of 30 μm.

On the other hand, this is one of the features of the present invention. A cavity formed by the upper and lower molds of a transfer mold device when forming one end of the lower surface of the semiconductor chip 4, that is, the package 2. The flow resistor 9 is provided over the entire width of the semiconductor chip 4 on the side where the gate 25 indicated by the chain double-dashed line for flowing the resin therein is provided.
Is provided. The flow resistor 9 is made of, for example, a polyimide tape whose one surface is coated with an adhesive. Here, describing the thickness of each part, the semiconductor chip 4 has a thickness of 280 μm, and the insulating tape 6 has a thickness of 80 μm.
μm, and the thickness of the lead 3 is 125 μm. The thickness of the resin on the lower surface of the chip 4 (the resin under the chip) is 320 μm, and the thickness of the resin on the upper surface of the chip 4, strictly speaking, the resin on the upper surface of the leads 3 (on-chip resin) is 195 μm. , The thickness of package 2 is 1mm
Becomes The thickness of the flow resistor 9 is set so that the resin flowing into the lower space of the chip 4 does not flow into the upper space of the chip 4 during transfer molding in manufacturing the semiconductor device 1 so that the resin flows into the lower space. Can be controlled, for example, the thickness is about 120 to 130 μm. Further, it is desirable that the end of the flow resistor 9 be an inclined surface so as not to disturb the flow of the resin.

The semiconductor device 1 as described above will be described in detail in a later manufacturing method. Since no voids remain in the package 2, moisture resistance is good and the chip 4 also rises or tilts. Since this is not done, the resin thickness of the package 2 covering the chip 4, the inner leads 5, the wires 7, etc. does not become locally thin, and the coverage is high.

Next, a method of manufacturing the semiconductor device 1 of the present invention will be described with reference to FIGS. In manufacturing the semiconductor device 1, as shown in FIG.
A lead frame 12 for 5 μm SOJ is prepared.
The lead frame 12 is manufactured by patterning an Fe-Ni alloy plate or a Cu alloy plate by etching or pressing. Lead frame 12
Is a pair of parallel extending outer frames 13 as shown in FIG.
And a pair of inner frames 14 connected to each other and extending in a direction orthogonal to the outer frame 13 has a frame structure. In addition, from the inside of the inner frame 14 to the outer frame 1
A plurality of leads 3 extend in parallel with 3. These leads 3 are supported by a dam 15 at their midpoints. These dams 15 are parallel to the inner frame 14 and extend from the outer frame 13 to the outer frame 13. In the inner lead portion (inner lead) 5 inside the dam 15, the inner leads 5 on both sides are bent toward the center of the frame.

Next, as shown in FIG. 5, a semiconductor chip 4 made of an LSI having a thickness of 280 μm is attached to such a lead frame 12 as shown in FIG. 1 and FIG. It is adhered via a tape 6. The insulating tape 6 is made of a polyimide tape whose both surfaces are coated with an adhesive, and has a thickness of 80 μm. The insulating tape 6 is partially opened so that an electrode portion (not shown) of the semiconductor chip 4 is exposed.

Next, as shown in FIGS. 1, 5 and 6, a flow resistor 9 is attached to the lower surface of the chip 4. The flow resistor 9 is made of, for example, a polyimide tape whose one surface is coated with an adhesive, and is 120 to 130 μm.
It has a thickness of m. This flow resistor 9 slows down the inflow speed of the resin that flows into the lower space of the chip 4 when the resin flows from the gate into the cavity formed by the upper and lower molds during transfer molding in the subsequent process. , Which acts to make the speed of the resin traveling in the upper space and the lower space of the tip 4 approximately the same, and to suppress the generation of a large amount of voids by violently flowing the resin from one space to the other space, or The resin that precedes the space serves to prevent the resin containing voids from being confined in the cavity. For this reason, as shown in FIGS. 7 and 8, the flow resistor 9 is provided near the gate 25 into which the resin 24 is injected and over the entire width of the chip 4.

Next, as shown in FIG. 7, the inner lead 5 and the electrode (not shown) of the chip 4 are electrically connected by a wire 7 made of a gold wire having a diameter of 30 μm.

Next, the lead frame 12 after the wire bonding is completed, as shown in FIGS. 7 and 8, the upper and lower molds 20, 21 of the transfer molding apparatus.
The mold is clamped in between and the molding is performed. Since the upper and lower molds 20 and 21 are provided with depressions, respectively, a cavity 23 having a thickness of 1 mm is formed by mold clamping. In addition, by clamping the upper and lower molds 20 and 21, the resin 24 is inserted into the cavity 23.
A gate 25 for injecting air, a space (air vent 26) for allowing air in the cavity 23 to escape, and a flow cavity 27 continuous with the air vent 26 are also formed. Then, the resin 24 melted from the gate 25 into the cavity 23
Is injected. Since the cavity 23 is divided into upper and lower parts by the inner leads 5 of the lead frame 12 and the chips 4, the resin 24 is
4 is an upper space 30 on the chip 4 in the cavity 23
And the cavity 23 separated into the lower space 31 under the chip 4.
Proceed in the direction of air vent 26.

The upper space 30 is 40 above the chip 4.
The thickness is 0 μm, which is thicker than the thickness 320 μm of the lower space 31, but thin as 195 μm on the inner lead 5 bonded to the chip 4 via the insulating tape 6 having a thickness of 80 μm. . As a result, the resin flow path in the upper space 30 becomes 400 along the flow direction of the resin 24.
The depth of .mu.m and the depth of 195 .mu.m are alternately formed, and the flow path is uneven, and the wire 7 having a thickness of 30 .mu.m obstructs the flow of the resin. The lower space 31 has a lower surface and both side surfaces that are flat surfaces formed by the upper mold 20, and most of the upper surface is a flat surface formed by the lower surface of the chip 4, so that the resin 24 easily flows. Therefore, the resin 24
Becomes easier to flow in the lower space 31 than in the upper space 30. on the other hand,
Since air is entrained in the tip portion of the resin 24 as it advances, a large amount of bubbles (voids) are generated. If the tip resin portion quickly flows into the flow cavity 27 through the air vent 26, no void will remain in the cavity 23. However, in the conventional case, the resin 24 that has flowed into the upper space 30 through the lower space 31 flows ahead into the upper space 30, so that the resin 24 that has flowed through the upper space 30 and the lower space The resin 24 wrapping around from 31 collides violently and more bubbles are generated. Then, the resin containing many voids becomes difficult to smoothly flow into the air vent 26 due to the resin that goes ahead in the lower space 31 and closes the air vent 26, which causes many voids to remain in the cavity 23.

On the other hand, in the case of the present invention, the flow resistor 9 is provided on the lower surface of the chip 4 facing the lower space 31. As a result, as shown in FIG. 8, the flow resistance body 9 acts so that the flow of the resin 24 in the lower space 31 becomes substantially the same as the flow of the resin 24 in the upper space 30. Therefore, the resin 2 flowing through the upper space 30 and the lower space 31
The tip portions of No. 4 flow into the flow cavity 27 through the air vents 26 at the same time or sequentially without disturbing the flow, so that the tip resin portion containing a large amount of voids does not remain in the cavity 23. As a result, voids do not exist in the package 2 formed after the sealing (molding) is completed. In order to prevent the flow of the resin 24 from being disturbed, it is desirable that both end portions of the flow resistor 9 be inclined surfaces as shown in FIG.

Further, in this transfer mold, the resin 24 flowing in the upper space 30 and the resin 24 flowing in the lower space 31 advance in the upper space 30 and the lower space 31 at substantially the same speed, so that the chip 4 is pushed up or pushed down. The large force that acts on the tip 4 does not act on the tip 4 or the like, and the tip 4 does not rise, twist, or tilt, and the coverage with the resin becomes good.

Next, the lead frame 1 is removed from the upper and lower molds 20 and 21, the unnecessary lead frame portions are cut and removed, and lead molding is performed. For example, as shown in FIG. The lead type semiconductor device 1 is manufactured.

[0027]

(1) According to the method of manufacturing a semiconductor device of the present invention, at the time of transfer molding, the speed of the resin flowing in the upper and lower spaces of the work in the cavity is made uniform, so that the resin flow is disturbed. Instead, the tip resin containing voids quickly flows into the flow cavity through the air vent, and an effect that a package not containing voids can be formed is obtained.

(2) According to the above method (1), the semiconductor device manufacturing method according to the present invention makes the speed of the resin flowing in the upper and lower spaces of the work in the cavity uniform during transfer molding. The effect that the filling property of the resin inside is stable is obtained.

(3) According to the method of manufacturing a semiconductor device of the present invention according to the above (1), the speed of the resin flowing in the upper and lower spaces of the work in the cavity becomes uniform during transfer molding. Does not push up or push down the semiconductor chip or the like (workpiece), and the chip 4 does not rise, twist, or tilt,
It is possible to obtain the effect that the resin does not become extremely thin and the coverage with the resin becomes good.

(4) Due to the above (3), according to the method of manufacturing a semiconductor device of the present invention, it is possible to obtain the effect that the thinning of the package can be achieved.

(5) From the above (1) to (3), according to the method of manufacturing a semiconductor device of the present invention, it is possible to provide a semiconductor device having a LOC structure in which no void is present in the package and which is excellent in moisture resistance. The synergistic effect of being able to do is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say, for example,
Even if another material such as a silicon material is used as the flow resistor 9, the same effect as in the above embodiment can be obtained.

9 to 11 show an example of manufacturing a semiconductor device according to another embodiment of the present invention. FIG. 9 is a cross-sectional view showing a main part of a semiconductor device having a LOC structure, FIG. 10 is a plan view showing a lead frame used for manufacturing the semiconductor device, and FIG. 11 is a schematic plan view showing a molding state in manufacturing the semiconductor device. It is a figure. In the semiconductor device 1 according to another embodiment of the present invention, the flow resistor 9 is not provided on the lower surface of the chip 4, but as shown in FIG. ) 5 is thin from the middle (thin portion 35: in FIGS. 10 and 11,
The thinned thin portion 35 is shown by hatching) to reduce the flow resistance along the resin flow direction, as shown in FIG. Lead 3 is 125 μm
However, the thin portion 35 has a thickness of about 60 μm, which is about half the thickness of the thin portion 35. Therefore, the resin flow path in the upper space 30 is 4 along the flow direction of the resin 24.
The flow path has irregularities in which a depth of 00 μm and a depth of 255 μm alternate. As a result, also in the case of this embodiment, the flow of the resin 24 in the upper space 30 is improved, and the resin 24 flowing in the upper space 30 and the lower space 31 are improved as compared with the conventional case. Since the flowing resin 24 flows through each space at substantially the same speed, the tip resin portions flowing through the upper space 30 and the lower space 31 pass through the air vent 26 and the flow cavity 27 either together or before or after without disturbing the flow. Therefore, the voids do not remain in the cavity 23. The thin portion 35 is formed by press molding or etching. Further, the length of the thin portion 35 of each inner lead 5 is, for example, short on the side close to the gate 25 and gradually increases as the distance increases, thereby increasing the support strength of the chip 4 and the inner lead 5 as a whole. It may be done.

In the above description, the LOC which is the field of application of the invention mainly made by the present inventor was the background.
The case where the invention is applied to the manufacturing technology of a semiconductor device having a structure has been described, but the invention is not limited thereto.
It can be applied to manufacturing technology of semiconductor devices having a COL structure.
INDUSTRIAL APPLICABILITY The present invention can be applied to a molding technique in which the resin flow velocity is extremely different between the upper space of the work and the lower space of the work at least in the cavity during transfer molding.

[Brief description of drawings]

FIG. 1 is a vertical sectional view showing a main part of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a lateral cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a plan view showing a lead frame used for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a plan view showing a lead frame to which a semiconductor chip is fixed in manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a bottom view showing a lead frame in which a flow resistor is attached to the back surface of a semiconductor chip in the manufacture of a semiconductor device according to an embodiment of the present invention.

FIG. 7 is a schematic plan view showing a molded state in the manufacture of a semiconductor device according to an example of the present invention.

FIG. 8 is a cross-sectional view showing a molded state in the manufacture of a semiconductor device according to an embodiment of the present invention.

FIG. 9 is a sectional view showing a main part of a semiconductor device according to another embodiment of the present invention.

FIG. 10 is a plan view showing a lead frame used for manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 11 is a schematic plan view showing a molded state in the manufacture of a semiconductor device according to another embodiment of the present invention.

[Explanation of symbols]

1 ... Semiconductor device, 2 ... Package, 3 ... Lead, 4 ... Semiconductor chip, 5 ... Lead inner end portion (inner lead),
6 ... Insulating adhesive (insulating tape), 7 ... Wire, 9 ... Flow resistor, 12 ... Lead frame, 13 ... Outer frame, 14 ...
Inner frame, 15 ... Dam, 20 ... Mold upper mold, 21 ... Mold lower mold, 23 ... Cavity, 24 ... Resin, 25 ... Gate, 26 ... Air vent, 27 ... Flow cavity, 3
0 ... upper space, 31 ... lower space, 35 ... thin part.

Claims (5)

[Claims] 1. A package made of a resin, a plurality of metal leads extending inside and outside the package, and connected to one surface of an inner end portion of the leads in the package via an insulating adhesive. A semiconductor device having a semiconductor chip formed therein, wherein a flow resistor is partially provided on a surface of the semiconductor chip on a side of the package where the resin is injected. 2. A package made of a resin, a plurality of metallic leads extending inside and outside the package, and connected to one surface of an inner end portion of the leads in the package via an insulating adhesive. A semiconductor device having a semiconductor chip as described above, wherein the lead on the semiconductor chip is thinned from the middle to the tip. 3. A step of bonding a semiconductor chip to one surface of a lead inner end portion of a lead frame via an insulating adhesive.
A method of manufacturing a semiconductor device, comprising the steps of sandwiching the lead frame between upper and lower molds of a transfer mold and injecting a resin from a gate into a cavity to form a package, wherein the gate is formed before the transfer molding. A method of manufacturing a semiconductor device, characterized in that a flow resistor, which serves as a resistance against a resin flow, is previously provided on a side surface of a semiconductor chip. 4. A step of adhering a semiconductor chip to one surface of a lead inner end portion of a lead frame via an insulating adhesive.
A method of manufacturing a semiconductor device, comprising the steps of sandwiching the lead frame between upper and lower molds of a transfer mold and injecting a resin from a gate into a cavity to form a package, wherein the semiconductor chip of the lead frame is provided. A method of manufacturing a semiconductor device, comprising: forming an inner end portion of a lead to be thinned in advance from the middle to a front end so as to be thin, and thereafter bonding a semiconductor chip through an insulating adhesive. 5. A package made of a resin, a plurality of metal leads extending inside and outside the package, and connected to one surface of an inner end portion of the leads in the package via an insulating adhesive. A lead frame used in the manufacture of a semiconductor device having a semiconductor chip, wherein an inner end portion of the lead attached to the semiconductor chip is thinly formed from the middle to the front end. .