JPH06326055A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH06326055A JPH06326055A JP11354993A JP11354993A JPH06326055A JP H06326055 A JPH06326055 A JP H06326055A JP 11354993 A JP11354993 A JP 11354993A JP 11354993 A JP11354993 A JP 11354993A JP H06326055 A JPH06326055 A JP H06326055A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- opening
- etching
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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- Electroplating Methods And Accessories (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に係り、詳しくは、層間絶縁膜に有機絶縁膜を使用した
半導体集積回路装置の配線構造に適用することができ、
特に、Ａｕ鍍金配線層の開口部内へのカバレッジを良好
にして信頼性の高い安定した配線構造を実現することが
できる半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, it can be applied to a wiring structure of a semiconductor integrated circuit device using an organic insulating film as an interlayer insulating film,
In particular, the present invention relates to a method for manufacturing a semiconductor device which can realize a highly reliable and stable wiring structure by providing good coverage in the opening of an Au-plated wiring layer.
【０００２】近年、コンピュータ、通信の高度化に伴な
い、これらに使用される半導体装置の高集積化、素子サ
イズ縮小化、高機能化及び定価格化が求められている。
最近では、平坦性向上・浮遊容量低減及び工程短縮のた
めに、層間絶縁膜への有機絶縁膜の適用が検討されてい
る。また、半導体集積回路装置は、配線の微細化に伴な
い、電極コンタクトホール及びビア・ホールの微細化も
進められており、微細化に対応した信頼性の高い金系配
線に於ける有機絶縁膜のコンタクトホール、ビア・ホー
ルの接続が要求されている。In recent years, with the advancement of computers and communications, there has been a demand for higher integration, smaller element size, higher functionality, and lower price of semiconductor devices used therein.
Recently, application of an organic insulating film to an interlayer insulating film has been studied in order to improve flatness, reduce stray capacitance, and shorten the process. Further, in semiconductor integrated circuit devices, electrode contact holes and via holes are being miniaturized along with the miniaturization of wiring, and the organic insulating film in highly reliable gold-based wiring corresponding to miniaturization is being advanced. It is required to connect the contact holes and via holes.
【０００３】[0003]
【従来の技術】図４は従来の半導体装置の製造方法を示
す図である。まず、図４（ａ）に示すように、蒸着法等
によりＧａＡｓ等の基板31上にＡｕＧｅＮｉ等の配線層
32を形成し、ＣＶＤ法等によりＡｕＧｅＮｉ配線層32上
にＳｉＯ2 等の絶縁膜33を形成した後、異方性エッチン
グによりＳｉＯ2 絶縁膜33をエッチングして配線層32が
露出された開口部34を形成する。この時、開口部34内の
絶縁膜33側壁（エッチング面）は垂直形状となる。2. Description of the Related Art FIG. 4 is a diagram showing a conventional method of manufacturing a semiconductor device. First, as shown in FIG. 4A, a wiring layer of AuGeNi or the like is formed on a substrate 31 of GaAs or the like by a vapor deposition method or the like.
32 is formed, after forming an insulating film 33 of SiO 2 or the like on the AuGeNi wiring layer 32 by CVD or the like, opening the wiring layer 32 is exposed by etching the SiO 2 insulating film 33 by anisotropic etching Forming 34. At this time, the side wall (etching surface) of the insulating film 33 in the opening 34 has a vertical shape.
【０００４】そして、スパッタリング法等により開口部
34内の配線層32とコンタクトを取るようにＷＳｉ（下
層）／Ｔｉ（中間層）／Ａｕ（上層）等の金属層35を形
成した後、この金属層35を鍍金電極とし、電界鍍金によ
り開口部34内を埋め込むように金属層35上にＡｕ等のＡ
ｕ鍍金配線層36を形成することにより、図４（ｂ）に示
すような配線構造を得ることができる。Then, the opening is formed by a sputtering method or the like.
After forming a metal layer 35 such as WSi (lower layer) / Ti (intermediate layer) / Au (upper layer) so as to make contact with the wiring layer 32 in 34, this metal layer 35 is used as a plating electrode and is opened by electric field plating. A such as Au is formed on the metal layer 35 so as to fill the inside of the portion 34.
By forming the u-plated wiring layer 36, a wiring structure as shown in FIG. 4B can be obtained.
【０００５】[0005]
【発明が解決しようとする課題】上記した従来の半導体
装置の製造方法では、異方性エッチングにより絶縁膜33
側壁が垂直形状となる開口部34を形成しており、開口部
34の直径が大きく集積度がそれ程要求されない場合に
は、図４（ｂ）に示す如く、開口部34内のＡｕ鍍金配線
層36を良好なカバレッジで形成することができる。電界
鍍金膜は、等方的に成長するため、開口部のアスペクト
比（絶縁膜の厚さ／開口部の幅）がある程度大きくなっ
てもボイドが出来ないと信じられていた。ところが実際
には、アスペクト比0.6という比較的に小さいアスペク
ト比からボイドが発生することがわかった。これは、通
常鍍金液は、攪拌されており、開口部以外の表面では、
メッキの流れが速いためＡｕ鍍金膜の成長速度が速い
が、開口部内部では鍍金液の流れが遅く、Ａｕ鍍金の成
長速度も遅いため、開口部中に鍍金液が閉じ込められる
ため、ボイドが発生するものと考えられる。集積度が要
求されて開口部34の直径が小さく厳しくなりアスペクト
比が0.6以上になると、図５に示す如く、Ａｕ鍍金配線
層36の開口部34内へのカバレッジが悪くなり、開口部34
内のＡｕ鍍金配線層36にボイド41等が生じたりして断線
不良が生じ易くなるという問題があった。In the conventional method of manufacturing a semiconductor device described above, the insulating film 33 is formed by anisotropic etching.
The side wall has an opening 34 having a vertical shape.
When the diameter of 34 is large and the degree of integration is not so required, the Au plated wiring layer 36 in the opening 34 can be formed with good coverage, as shown in FIG. 4B. Since the electroplated film grows isotropically, it was believed that voids could not be formed even when the aspect ratio of the opening (thickness of the insulating film / width of the opening) was increased to some extent. However, it was found that voids actually occur from a relatively small aspect ratio of 0.6. This is because the plating solution is usually agitated, and the surface other than the opening is
Since the plating flow is fast, the growth rate of the Au plating film is fast, but the flow of the plating solution is slow inside the opening, and the growth rate of the Au plating is also slow, so the plating solution is trapped in the opening and a void occurs. It is supposed to do. When the degree of integration is required and the diameter of the opening 34 becomes small and becomes severe and the aspect ratio becomes 0.6 or more, as shown in FIG. 5, the coverage of the Au-plated wiring layer 36 into the opening 34 is deteriorated and the opening 34
There has been a problem that voids 41 and the like are generated in the Au plated wiring layer 36 in the inside and disconnection defects are likely to occur.
【０００６】そこで、本発明は、Ａｕ鍍金配線層の開口
部内へのカバレッジを良好にすることができ、開口部内
のＡｕ鍍金配線層にボイド等を生じ難くして配線不良を
生じ難くすることができ、信頼性の高い安定した配線構
造を実現することができる半導体装置の製造方法を提供
することを目的としている。Therefore, according to the present invention, it is possible to improve the coverage of the Au-plated wiring layer in the opening, and it is possible to prevent voids and the like from occurring in the Au-plated wiring layer in the opening and prevent wiring failure. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can realize a reliable and stable wiring structure.
【０００７】[0007]
【課題を解決するための手段】本発明による半導体装置
の製造方法は上記目的達成のため、下地の膜上に導電性
膜を形成する工程と、次いで、該導電性膜上に厚さＴの
絶縁膜を形成する工程と、次いで、該絶縁膜上に開口幅
ＷがＴ／0.6以下の窓を有するマスクを形成する工程
と、次いで、該マスクを用い、該窓内に等方性エッチン
グにより、該導電性膜を露出させないように該絶縁膜を
途中までエッチングして該絶縁膜上部に開口幅Ｗより広
い幅の溝を形成する工程と、次いで、該マスクを用い、
該窓内に異方性エッチングにより該溝を介して該絶縁膜
をエッチングして該導電性膜が露出される開口幅Ｗと同
等の開口部を形成する工程と、次いで、該導電性膜に電
流を流して、該開口部及び該溝を露うように鍍金層を形
成する工程とを含むものである。In order to achieve the above object, the method of manufacturing a semiconductor device according to the present invention comprises a step of forming a conductive film on a base film, and then a step of forming a thickness T on the conductive film. A step of forming an insulating film, a step of forming a mask having a window having an opening width W of T / 0.6 or less on the insulating film, and a step of isotropic etching in the window using the mask. A step of etching the insulating film halfway so as not to expose the conductive film to form a groove having a width wider than the opening width W in the upper portion of the insulating film, and then using the mask,
A step of etching the insulating film in the window through the groove through anisotropic etching to form an opening having a width equal to the opening width W exposing the conductive film; And applying a current to form a plating layer so as to expose the opening and the groove.
【０００８】本発明に係る、下地の膜には、Ｓｉ含有ポ
リイミド樹脂等のポリイミド樹脂膜、ＳｉＮ等の無機絶
縁膜等絶縁膜やＧａＡｓ、Ｓｉ等の基板等が挙げられ、
また、絶縁膜には、Ｓｉ含有ポリイミド樹脂等のポリイ
ミド樹脂膜、シリコ−ン樹脂膜等が挙げられる。また、
マスクには、ＳｉＮ，ＳｉＯ2 等の無機絶縁膜やＳｉ含
有レジスト等のプラズマ耐性レジスト等が挙げられる。Examples of the underlying film according to the present invention include a polyimide resin film such as a Si-containing polyimide resin, an insulating film such as an inorganic insulating film such as SiN, and a substrate such as GaAs and Si.
Examples of the insulating film include a polyimide resin film such as a Si-containing polyimide resin and a silicone resin film. Also,
Examples of the mask include an inorganic insulating film such as SiN and SiO 2 and a plasma resistant resist such as Si-containing resist.
【０００９】本発明においては、前記絶縁膜を、下層が
無機絶縁膜で上層が有機絶縁膜からなる２層の絶縁膜で
構成し、等方性ドライエッチングにより有機絶縁膜の膜
厚の途中までエッチングを行った後に、異方性ドライエ
ッチングにより残りの有機絶縁膜と下層の無機絶縁膜を
エッチングするようにしてもよく、この場合、無機絶縁
膜にＳｉＮ膜等を用いれば、このＳｉＮ無機絶縁膜を介
してポリイミド樹脂等の有機絶縁膜とＡｕＧｅＮｉ等の
導電性膜との密着度を向上させることができる。In the present invention, the insulating film is composed of a two-layer insulating film in which the lower layer is an inorganic insulating film and the upper layer is an organic insulating film, and isotropic dry etching is performed until the middle of the film thickness of the organic insulating film. After etching, the remaining organic insulating film and the lower inorganic insulating film may be etched by anisotropic dry etching. In this case, if a SiN film or the like is used as the inorganic insulating film, the SiN inorganic insulating film Through the film, the degree of adhesion between the organic insulating film such as polyimide resin and the conductive film such as AuGeNi can be improved.
【００１０】本発明においては、鍍金後の前記鍍金層及
び該鍍金電極を全面エッチングして該開口部及び該溝内
のみに埋め込むビアホール配線構造の場合に好ましく適
用させることができる。本発明において、前記マスク
は、前記異方性エッチングと同時に除去するか、又は前
記異方性エッチング後に除去するようにしてもよく、前
者によれば工程数を減らすことができる。The present invention can be preferably applied to a via-hole wiring structure in which the plating layer and the plating electrode after plating are entirely etched to fill only the opening and the groove. In the present invention, the mask may be removed simultaneously with the anisotropic etching or after the anisotropic etching. According to the former, the number of steps can be reduced.
【００１１】[0011]
【作用】本発明では、後述する実施例の図１，２に示す
如く、層間絶縁膜としては、平坦性向上、浮遊容量低減
及び工数短縮のため無機絶縁膜ではなく、ポリイミド有
機絶縁膜４を用い、層間絶縁膜４，３に対してまず、等
方性エッチングを行った後、異方性エッチングを行って
絶縁膜４上部にテーパの付いたコンタクトホール11を形
成している。このため、等方性エッチングと異方性エッ
チングを行うことにより、絶縁膜４側壁上部にテーパ形
状を有するコンタクトホール11を形成するので、従来の
異方性エッチングのみを行ってテーパを有さないエッチ
ング面がストレートのコンタクトホールを形成する場合
よりもテーパ部分の絶縁膜４側壁上部でＡｕ鍍金配線層
13を厚く形成することができる。従って、従来の異方性
エッチングのみでコンタクトホールを形成する場合より
もＡｕ鍍金配線層13のコンタクトホール11内へのカバレ
ッジを良好にすることができ、コンタクトホール11内の
Ａｕ鍍金配線層13にボイド等を生じ難くして断線不良を
生じ難くすることができ、信頼性の高い安定した配線構
造を実現することができる。In the present invention, as shown in FIGS. 1 and 2 of the embodiment to be described later, as the interlayer insulating film, the polyimide organic insulating film 4 is used instead of the inorganic insulating film in order to improve the flatness, reduce the stray capacitance and reduce the number of steps. First, isotropic etching is performed on the interlayer insulating films 4 and 3 and then anisotropic etching is performed to form a tapered contact hole 11 on the insulating film 4. Therefore, the contact hole 11 having a tapered shape is formed on the upper side wall of the insulating film 4 by performing the isotropic etching and the anisotropic etching. Therefore, only the conventional anisotropic etching is performed and the tapered contact hole 11 is not formed. As compared with the case where a contact hole having a straight etched surface is formed, an Au plated wiring layer is formed on the sidewall of the insulating film 4 in the tapered portion.
13 can be formed thick. Therefore, the coverage of the Au plated wiring layer 13 in the contact hole 11 can be made better than in the case where the contact hole is formed only by the conventional anisotropic etching, and the Au plated wiring layer 13 in the contact hole 11 is covered. Voids and the like can be made less likely to occur and disconnection defects can be made less likely to occur, and a highly reliable and stable wiring structure can be realized.
【００１２】[0012]
【実施例】以下、本発明の実施例を図面に基づいて説明
する。図１，２は本発明の一実施例に則した半導体装置
の製造方法を示す図である。本実施例では、まず、図１
（ａ）に示すように、蒸着法等によりＧａＡｓ等の基板
１上に膜厚2000Å程度のＡｕＧｅＮｉ等の配線層２を形
成し、プラズマＣＶＤ（Ｐ−ＣＶＤ）法等によりＡｕＧ
ｅＮｉ配線層２上に膜厚 1000 オングストローム程度の
ＳｉＮ等の絶縁膜３を形成した後、絶縁膜３上にポリイ
ミドを塗布しキュアして膜厚１μｍ程度のポリイミド等
の絶縁膜４を形成する。次いで、ＰＣＶＤ法等によりポ
リイミド絶縁膜４上に膜厚 1000 オングストローム程度
のＳｉＮ膜５を形成した後、ＳｉＮ膜５上に膜厚１μｍ
程度のフォトレジスト６を塗布する。Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. In this embodiment, first, as shown in FIG.
As shown in (a), a wiring layer 2 of AuGeNi or the like having a film thickness of about 2000Å is formed on a substrate 1 of GaAs or the like by a vapor deposition method or the like, and AuG is formed by a plasma CVD (P-CVD) method or the like.
After forming an insulating film 3 of SiN or the like having a film thickness of about 1000 angstroms on the eNi wiring layer 2, polyimide is coated on the insulating film 3 and cured to form an insulating film 4 of polyimide or the like having a film thickness of about 1 μm. Then, a SiN film 5 having a film thickness of about 1000 angstrom is formed on the polyimide insulating film 4 by the PCVD method or the like, and then a film thickness of 1 μm is formed on the SiN film 5.
About the amount of photoresist 6 is applied.
【００１３】次に、図１（ｂ）に示すように、塗布後の
フォトレジスト６を露光・現像によりパターニングして
開口部７を形成し、このフォトレジスト６をマスクにし
てＳｉＮ膜５をドライエッチングして開口部８を形成し
た後、ダウンフロー型アッシング装置を用い、フォトレ
ジスト６及びＳｉＮ膜５をマスクにし、開口部７，８内
の絶縁膜４を0.6 μｍの深さまで等方性エッチングして
絶縁膜４上部に溝９を形成する。この時、等方性エッチ
ングの横方向のエッチング量（サイドエッチング量）
は、深さ方向の約半分の0.3 μｍとなる。また、ＳｉＮ
膜５エッチングにマスクとして用いたフォトレジスト６
は、この等方性エッチングと同時に除去される。Next, as shown in FIG. 1B, the photoresist 6 after application is patterned by exposure and development to form an opening 7, and the SiN film 5 is dried using the photoresist 6 as a mask. After forming the opening 8 by etching, the downflow type ashing device is used, and the insulating film 4 in the opening 7 and 8 is isotropically etched to a depth of 0.6 μm using the photoresist 6 and the SiN film 5 as a mask. Then, a groove 9 is formed on the insulating film 4. At this time, the lateral etching amount of isotropic etching (side etching amount)
Is 0.3 μm, which is about half of the depth direction. Also, SiN
Photoresist 6 used as mask for etching film 5
Are removed at the same time as this isotropic etching.
【００１４】次に、図１（ｃ）に示すように、Ｍ−ＲＩ
Ｅ（マグネトロンリアクティブイオンエッチング）装置
を用い、ＳｉＮ膜５をマスクにし、溝９を介して残りの
ポリイミド絶縁膜４を異方性エッチングし、更に、図２
（ａ）に示すように、異方性エッチングによってホール
底のＳｉＮ絶縁膜３部分とポリイミド絶縁膜４上のＳｉ
Ｎ膜５とを同時に除去して溝９から配線層２まで貫通す
る配線層２が露出される開口部10を形成する。この時、
溝９及び開口部10からなる上部エッチング面がテーパ形
状で下部エッチング面が垂直形状のコンタクトホール11
が形成される。Next, as shown in FIG. 1C, the M-RI
Using an E (magnetron reactive ion etching) device, the remaining polyimide insulating film 4 is anisotropically etched through the groove 9 using the SiN film 5 as a mask.
As shown in (a), the SiN on the hole bottom and the Si on the polyimide insulating film 4 are anisotropically etched.
The N film 5 is removed at the same time to form an opening 10 that exposes the wiring layer 2 penetrating from the groove 9 to the wiring layer 2. At this time,
A contact hole 11 in which the upper etching surface including the groove 9 and the opening 10 is tapered and the lower etching surface is vertical.
Is formed.
【００１５】次に、図２（ｂ）に示すように、メッキ下
地メタルとしてＷＳｉ膜（膜厚1000Å）／Ｔｉ膜（膜厚
100Å）／Ａｕ（膜厚1000Å）等の鍍金電極12をコンタ
クトホール11内の配線層２とコンタクトするようにスパ
ッタリング等により形成する。そして、ＷＳｉ／Ｔｉ／
Ａｕ鍍金電極12を用い、電界鍍金法によりコンタクトホ
ール11を覆うようにＷＳｉ／Ｔｉ／Ａｕ鍍金電極12上に
膜厚１μｍ程度のＡｕ鍍金配線層13を形成することによ
り、図２（ｃ）に示すような配線構造を得ることができ
る。Next, as shown in FIG. 2B, a WSi film (film thickness 1000Å) / Ti film (film thickness
A plating electrode 12 of 100 Å) / Au (thickness of 1000 Å) or the like is formed by sputtering or the like so as to be in contact with the wiring layer 2 in the contact hole 11. And WSi / Ti /
By using the Au-plated electrode 12 and forming the Au-plated wiring layer 13 with a film thickness of about 1 μm on the WSi / Ti / Au-plated electrode 12 so as to cover the contact hole 11 by the electroplating method, as shown in FIG. The wiring structure as shown can be obtained.
【００１６】このように、本実施例では、層間絶縁膜と
しては、平坦性向上、浮遊容量低減及び工数短縮のた
め、無機絶縁膜ではなくポリイミド有機絶縁膜４を用
い、層間絶縁膜４，３に対してまず、等方性エッチング
を行った後、異方性エッチングを行って絶縁膜４上部に
テーパの付いたコンタクトホール11を形成している。こ
のため、等方性エッチングと異方性エッチングを行うこ
とにより、絶縁膜４側壁上部にテーパ形状を有するコン
タクトホール11を形成するので、従来の異方性エッチン
グのみを行ってテーパを有さないエッチング面がストレ
ートのコンタクトホールを形成する場合よりもテーパ部
分の絶縁膜４側壁上部でＡｕ鍍金配線層13を厚く形成す
ることができる。従って、従来の異方性エッチングのみ
でコンタクトホールを形成する場合よりもＡｕ鍍金配線
層13のコンタクトホール11内へのカバレッジを良好にす
ることができ、コンタクトホール11内のＡｕ鍍金配線層
13にボイド等を生じ難くして断線不良を生じ難くするこ
とができ、信頼性の高い安定した配線構造を実現するこ
とができる。As described above, in this embodiment, as the interlayer insulating film, the polyimide organic insulating film 4 is used instead of the inorganic insulating film in order to improve the flatness, reduce the floating capacitance, and shorten the man-hours. On the other hand, first, isotropic etching is performed and then anisotropic etching is performed to form a tapered contact hole 11 on the insulating film 4. Therefore, the contact hole 11 having a tapered shape is formed on the upper side wall of the insulating film 4 by performing the isotropic etching and the anisotropic etching. Therefore, only the conventional anisotropic etching is performed and the tapered contact hole 11 is not formed. The Au-plated wiring layer 13 can be formed thicker on the sidewall of the insulating film 4 in the tapered portion than in the case of forming a contact hole having a straight etched surface. Therefore, the coverage of the Au-plated wiring layer 13 in the contact hole 11 can be improved as compared with the conventional case where the contact hole is formed only by anisotropic etching, and the Au-plated wiring layer in the contact hole 11 is formed.
It is possible to prevent voids and the like from occurring in 13 and to prevent disconnection failure, and it is possible to realize a highly reliable and stable wiring structure.
【００１７】また、本実施例では、有機絶縁膜４として
Ｓｉ含有ポリイミド樹脂等のポリイミド樹脂を用いたた
め、工程を容易にすることができる他、等方性ドライエ
ッチングとしてダウンフロー・アッシング装置を用いた
ため、等方性エッチングのウェーハ面内均一性を向上さ
せることができる。また、有機絶縁膜４のマスクとして
ＳｉＮ膜５（ＳｉＯ2 等の無機絶縁膜でもよい）を用い
たため、有機絶縁膜４のエッチングの選択性を良好にす
ることができる他、マスクとしてＳｉ含有レジスト等の
プラズマ耐性レジスト６を用いた場合にはＳｉＮ膜５が
不用となり、工程を容易にすることができる。更には、
絶縁膜４と配線層２間に絶縁膜３を用いたため、密着性
を向上させることができる。Further, in this embodiment, since the polyimide resin such as the Si-containing polyimide resin is used as the organic insulating film 4, the process can be facilitated and the downflow ashing device is used as the isotropic dry etching. Therefore, the in-plane uniformity of the isotropic etching can be improved. Further, since the SiN film 5 (which may be an inorganic insulating film such as SiO 2 ) is used as the mask of the organic insulating film 4, the etching selectivity of the organic insulating film 4 can be improved, and the Si-containing resist can be used as the mask. When the plasma resistant resist 6 such as is used, the SiN film 5 becomes unnecessary and the process can be facilitated. Furthermore,
Since the insulating film 3 is used between the insulating film 4 and the wiring layer 2, the adhesion can be improved.
【００１８】なお、上記実施例では、Ａｕ鍍金配線層13
上絶縁膜４上にまで覆うように形成する場合について説
明したが、図３に示すように、鍍金後のＡｕ鍍金配線層
13を全面ミリングによりＡｕをミリングし、更にＷＳｉ
／Ｔｉ鍍金電極12をドライエッチングすることにより、
コンタクトホール11内のみにメタルを残すようにしても
よい。In the above embodiment, the Au plated wiring layer 13
The case where the upper insulating film 4 is formed so as to cover the upper insulating film 4 has been described, but as shown in FIG. 3, the Au plated wiring layer after plating is formed.
13 is milled over the entire surface to mill Au and then WSi
By dry-etching the / Ti plated electrode 12,
The metal may be left only in the contact hole 11.
【００１９】[0019]
【発明の効果】本発明によれば、Ａｕ鍍金配線層の開口
部内へのカバレッジを良好にすることができ、開口部内
のＡｕ鍍金配線層にボイド等を生じ難くして断線不良を
生じ難くすることができ、信頼性の高い安定した配線構
造を実現することができるという効果がある。According to the present invention, it is possible to improve the coverage of the Au-plated wiring layer in the opening, and to prevent voids and the like from occurring in the Au-plated wiring layer in the opening and to prevent disconnection failure. Therefore, there is an effect that a reliable and stable wiring structure can be realized.
【図１】本発明の一実施例に則した半導体装置の製造方
法を示す図である。FIG. 1 is a diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施例に則した半導体装置の製造方
法を示す図である。FIG. 2 is a diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図３】本発明に適用できる半導体装置の製造方法を示
す図である。FIG. 3 is a diagram showing a method of manufacturing a semiconductor device applicable to the present invention.
【図４】従来例の半導体装置の製造方法を示す図であ
る。FIG. 4 is a diagram showing a method for manufacturing a semiconductor device of a conventional example.
【図５】従来例の課題を説明する図である。FIG. 5 is a diagram illustrating a problem of a conventional example.
１ 基板 ２ 配線層 ３，４ 絶縁膜 ５ ＳｉＮ膜 ６ フォトレジスト ７，８，10 開口部 ９ 溝 11 コンタクトホール 12 鍍金電極 13 Ａｕ鍍金配線層 1 Substrate 2 Wiring Layer 3,4 Insulating Film 5 SiN Film 6 Photoresist 7, 8, 10 Opening 9 Groove 11 Contact Hole 12 Plating Electrode 13 Au Plating Wiring Layer
Claims (3)
成する工程と、 次いで、該導電性膜（２）上に厚さＴの絶縁膜（３，
４）を形成する工程と、次いで、該絶縁膜（３，４）上
に開口幅ＷがＴ／0.6以下の窓を有するマスク（５，
６）を形成する工程と、 次いで、該マスク（５，６）を用い、該窓内に等方性エ
ッチングにより該導電性膜（２）を露出させないように
該絶縁膜（３，４）を途中までエッチングして該絶縁膜
（３，４）上部に開口幅Ｗより広い幅の溝（９）を形成
する工程と、 次いで、該マスク（５，６）を用い、該窓内に異方性エ
ッチングにより該溝（９）を介して該絶縁膜（３，４）
をエッチングして該導電性膜（２）が露出される開口幅
Ｗと同等の開口部（10）を形成する工程と、 次いで、該導電性膜（２）に電流を流して、該開口部
（10）及び該溝（９）を覆うように鍍金層（13）を形成
する工程とを含むことを特徴とする半導体装置の製造方
法。1. A step of forming a conductive film (2) on an underlying film (1), and then an insulating film (3, 3) having a thickness T on the conductive film (2).
4), and then a mask (5, 5 having a window with an opening width W of T / 0.6 or less on the insulating film (3, 4)).
6) and then using the masks (5, 6), the insulating film (3, 4) is formed in the window by isotropic etching so as not to expose the conductive film (2). A step of etching halfway to form a groove (9) having a width wider than the opening width W in the upper part of the insulating film (3, 4); and then, using the mask (5, 6), anisotropically in the window The insulating film (3, 4) through the groove (9) by a reactive etching.
A step of etching the conductive film (2) to form an opening (10) having the same opening width W as the exposed conductive film (2), and then applying a current to the conductive film (2) to form the opening. (10) and a step of forming a plating layer (13) so as to cover the groove (9), a method for manufacturing a semiconductor device.
極（12）を全面エッチングして該開口部（10）及び該溝
（９）内のみに埋め込むことを特徴とする請求項１記載
の半導体装置の製造方法。2. The plating layer (13) and the plating electrode (12) after plating are entirely etched to be embedded only in the opening (10) and the groove (9). A method for manufacturing a semiconductor device as described above.
ッチングと同時に除去するか、又は前記異方性エッチン
グ後に除去することを特徴とする請求項１，２記載の半
導体装置の製造方法。3. The manufacturing of a semiconductor device according to claim 1, wherein the masks (5, 6) are removed simultaneously with the anisotropic etching or after the anisotropic etching. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11354993A JPH06326055A (en) | 1993-05-17 | 1993-05-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11354993A JPH06326055A (en) | 1993-05-17 | 1993-05-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06326055A true JPH06326055A (en) | 1994-11-25 |
Family
ID=14615126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11354993A Withdrawn JPH06326055A (en) | 1993-05-17 | 1993-05-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06326055A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5917231A (en) * | 1997-02-17 | 1999-06-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including an insulative layer having a gap |
| US6268619B1 (en) | 1997-04-24 | 2001-07-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with high aspect ratio via hole including solder repelling coating |
| JP2002296760A (en) * | 2001-04-02 | 2002-10-09 | Nec Corp | Photo mask and production method for semiconductor device using the same |
| JP2007150367A (en) * | 1994-12-29 | 2007-06-14 | Stmicroelectronics Inc | Constitutional body and method of forming enlarged head of plug used for eliminating enclosure requirement |
| JP2009006453A (en) * | 2007-06-29 | 2009-01-15 | Fujitsu Ltd | Micro-structure manufacturing method and micro-structure |
-
1993
- 1993-05-17 JP JP11354993A patent/JPH06326055A/en not_active Withdrawn
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007150367A (en) * | 1994-12-29 | 2007-06-14 | Stmicroelectronics Inc | Constitutional body and method of forming enlarged head of plug used for eliminating enclosure requirement |
| US5917231A (en) * | 1997-02-17 | 1999-06-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including an insulative layer having a gap |
| US6268619B1 (en) | 1997-04-24 | 2001-07-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with high aspect ratio via hole including solder repelling coating |
| US6391770B2 (en) | 1997-04-24 | 2002-05-21 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device |
| JP2002296760A (en) * | 2001-04-02 | 2002-10-09 | Nec Corp | Photo mask and production method for semiconductor device using the same |
| JP2009006453A (en) * | 2007-06-29 | 2009-01-15 | Fujitsu Ltd | Micro-structure manufacturing method and micro-structure |
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Legal Events
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| A300 | Withdrawal of application because of no request for examination |
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